llvm.org GIT mirror llvm / bc21981
Convert assert(0) to llvm_unreachable git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
42 changed file(s) with 107 addition(s) and 152 deletion(s). Raw diff Collapse all Expand all
8383
8484 void EmitTextAttribute(unsigned Attribute, StringRef String) {
8585 switch (Attribute) {
86 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
8687 case ARMBuildAttrs::CPU_name:
8788 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
8889 break;
9192 case ARMBuildAttrs::VFP_arch:
9293 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
9394 break;
94 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
9595 }
9696 }
9797 void Finish() { }
195195 AttributeItemType item = Contents[i];
196196 Streamer.EmitULEB128IntValue(item.Tag, 0);
197197 switch (item.Type) {
198 default: llvm_unreachable("Invalid attribute type");
198199 case AttributeItemType::NumericAttribute:
199200 Streamer.EmitULEB128IntValue(item.IntValue, 0);
200201 break;
202203 Streamer.EmitBytes(item.StringValue.upper(), 0);
203204 Streamer.EmitIntValue(0, 1); // '\0'
204205 break;
205 default:
206 assert(0 && "Invalid attribute type");
207206 }
208207 }
209208
330329 unsigned TF = MO.getTargetFlags();
331330
332331 switch (MO.getType()) {
333 default:
334 assert(0 && "");
332 default: llvm_unreachable("");
335333 case MachineOperand::MO_Register: {
336334 unsigned Reg = MO.getReg();
337335 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
11171115 switch (Opc) {
11181116 default:
11191117 MI->dump();
1120 assert(0 && "Unsupported opcode for unwinding information");
1118 llvm_unreachable("Unsupported opcode for unwinding information");
11211119 case ARM::tPUSH:
11221120 // Special case here: no src & dst reg, but two extra imp ops.
11231121 StartOp = 2; NumOffset = 2;
11461144 switch (Opc) {
11471145 default:
11481146 MI->dump();
1149 assert(0 && "Unsupported opcode for unwinding information");
1147 llvm_unreachable("Unsupported opcode for unwinding information");
11501148 case ARM::MOVr:
11511149 case ARM::tMOVr:
11521150 Offset = 0;
11931191 OutStreamer.EmitPad(Offset);
11941192 } else {
11951193 MI->dump();
1196 assert(0 && "Unsupported opcode for unwinding information");
1194 llvm_unreachable("Unsupported opcode for unwinding information");
11971195 }
11981196 } else if (DstReg == ARM::SP) {
11991197 // FIXME: .movsp goes here
12001198 MI->dump();
1201 assert(0 && "Unsupported opcode for unwinding information");
1199 llvm_unreachable("Unsupported opcode for unwinding information");
12021200 }
12031201 else {
12041202 MI->dump();
1205 assert(0 && "Unsupported opcode for unwinding information");
1203 llvm_unreachable("Unsupported opcode for unwinding information");
12061204 }
12071205 }
12081206 }
12311229 // Check for manual lowerings.
12321230 unsigned Opc = MI->getOpcode();
12331231 switch (Opc) {
1234 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1232 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
12351233 case ARM::DBG_VALUE: {
12361234 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
12371235 SmallString<128> TmpStr;
155155 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
156156 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
157157 switch (AddrMode) {
158 default:
159 assert(false && "Unknown indexed op!");
160 return NULL;
158 default: llvm_unreachable("Unknown indexed op!");
161159 case ARMII::AddrMode2: {
162160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
163161 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
6161
6262 int ARMConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
6363 unsigned Alignment) {
64 assert(false && "Shouldn't be calling this directly!");
65 return -1;
64 llvm_unreachable("Shouldn't be calling this directly!");
6665 }
6766
6867 void
4040 case ARM::reloc_arm_machine_cp_entry:
4141 case ARM::reloc_arm_jt_base:
4242 case ARM::reloc_arm_pic_jt:
43 assert(0 && "unsupported ARM relocation type"); return 0;
44
43 llvm_unreachable("unsupported ARM relocation type");
44
4545 case ARM::reloc_arm_branch: return ELF::R_ARM_CALL;
4646 case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS;
4747 case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC;
5252
5353 long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
5454 long int Modifier) const {
55 assert(0 && "ARMELFWriterInfo::getDefaultAddendForRelTy() not implemented");
56 return 0;
55 llvm_unreachable("ARMELFWriterInfo::getDefaultAddendForRelTy() not "
56 "implemented");
5757 }
5858
5959 unsigned ARMELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
60 assert(0 && "ARMELFWriterInfo::getRelocationTySize() not implemented");
61 return 0;
60 llvm_unreachable("ARMELFWriterInfo::getRelocationTySize() not implemented");
6261 }
6362
6463 bool ARMELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
65 assert(0 && "ARMELFWriterInfo::isPCRelativeRel() not implemented");
66 return 1;
64 llvm_unreachable("ARMELFWriterInfo::isPCRelativeRel() not implemented");
6765 }
6866
6967 unsigned ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
70 assert(0 &&
71 "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
72 return 0;
68 llvm_unreachable("ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not "
69 "implemented");
7370 }
7471
7572 long int ARMELFWriterInfo::computeRelocation(unsigned SymOffset,
7673 unsigned RelOffset,
7774 unsigned RelTy) const {
78 assert(0 &&
79 "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
80 return 0;
75 llvm_unreachable("ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not "
76 "implemented");
8177 }
880880
881881 bool needsLowering = false;
882882 switch (VT.getSimpleVT().SimpleTy) {
883 default:
884 assert(false && "Unhandled load/store type!");
885 break;
883 default: llvm_unreachable("Unhandled load/store type!");
886884 case MVT::i1:
887885 case MVT::i8:
888886 case MVT::i16:
23602360 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
23612361 unsigned Opc = 0;
23622362 switch (VT.getSimpleVT().SimpleTy) {
2363 default: assert(false && "Illegal conditional move type!");
2364 break;
2363 default: llvm_unreachable("Illegal conditional move type!");
23652364 case MVT::i32:
23662365 Opc = Subtarget->isThumb()
23672366 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
30693069 unsigned Opc;
30703070
30713071 switch (Op.getOpcode()) {
3072 default:
3073 assert(0 && "Invalid opcode!");
3072 default: llvm_unreachable("Invalid opcode!");
30743073 case ISD::FP_TO_SINT:
30753074 Opc = ARMISD::FTOSI;
30763075 break;
31003099 unsigned CastOpc;
31013100 unsigned Opc;
31023101 switch (Op.getOpcode()) {
3103 default:
3104 assert(0 && "Invalid opcode!");
3102 default: llvm_unreachable("Invalid opcode!");
31053103 case ISD::SINT_TO_FP:
31063104 CastOpc = ISD::SIGN_EXTEND;
31073105 Opc = ISD::SINT_TO_FP;
31253123 unsigned Opc;
31263124
31273125 switch (Op.getOpcode()) {
3128 default:
3129 assert(0 && "Invalid opcode!");
3126 default: llvm_unreachable("Invalid opcode!");
31303127 case ISD::SINT_TO_FP:
31313128 Opc = ARMISD::SITOF;
31323129 break;
49564953 unsigned Opc;
49574954 bool ExtraOp = false;
49584955 switch (Op.getOpcode()) {
4959 default: assert(0 && "Invalid code");
4956 default: llvm_unreachable("Invalid code");
49604957 case ISD::ADDC: Opc = ARMISD::ADDC; break;
49614958 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
49624959 case ISD::SUBC: Opc = ARMISD::SUBC; break;
66666663 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
66676664 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
66686665 default:
6669 assert(0 && "Invalid vector element type for padd optimization.");
6666 llvm_unreachable("Invalid vector element type for padd optimization.");
66706667 }
66716668
66726669 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
73317328 if (isIntrinsic) {
73327329 unsigned IntNo = cast(N->getOperand(1))->getZExtValue();
73337330 switch (IntNo) {
7334 default: assert(0 && "unexpected intrinsic for Neon base update");
7331 default: llvm_unreachable("unexpected intrinsic for Neon base update");
73357332 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
73367333 NumVecs = 1; break;
73377334 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
73647361 } else {
73657362 isLaneOp = true;
73667363 switch (N->getOpcode()) {
7367 default: assert(0 && "unexpected opcode for Neon base update");
7364 default: llvm_unreachable("unexpected opcode for Neon base update");
73687365 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
73697366 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
73707367 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
3030 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
3131 OutContext);
3232 switch (MO.getTargetFlags()) {
33 default:
34 assert(0 && "Unknown target flag on symbol operand");
33 default: llvm_unreachable("Unknown target flag on symbol operand");
3534 case 0:
3635 break;
3736 case ARMII::MO_LO16:
6665 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
6766 MCOperand &MCOp) {
6867 switch (MO.getType()) {
69 default:
70 assert(0 && "unknown operand type");
71 return false;
68 default: llvm_unreachable("unknown operand type");
7269 case MachineOperand::MO_Register:
7370 // Ignore all non-CPSR implicit register operands.
7471 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
27242724 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
27252725 return Reg + 1;
27262726 switch(Reg) {
2727 default: assert(0 && "Invalid GPR number!");
2727 default: llvm_unreachable("Invalid GPR number!");
27282728 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
27292729 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
27302730 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
52215221
52225222 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
52235223 switch(Opc) {
5224 default: assert(0 && "unexpected opcode!");
5224 default: llvm_unreachable("unexpected opcode!");
52255225 // VST1LN
52265226 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
52275227 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
53305330
53315331 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
53325332 switch(Opc) {
5333 default: assert(0 && "unexpected opcode!");
5333 default: llvm_unreachable("unexpected opcode!");
53345334 // VLD1LN
53355335 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
53365336 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
70217021 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
70227022 if (SOpc == ARM_AM::rrx) return false;
70237023 switch (Inst.getOpcode()) {
7024 default: assert(0 && "unexpected opcode!");
7024 default: llvm_unreachable("unexpected opcode!");
70257025 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
70267026 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
70277027 case ARM::EORrsi: newOpc = ARM::EORrr; break;
532532 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
533533 MI.addOperand(MCOperand::CreateExpr(Expr));
534534 else
535 assert(0 && "bad SymbolicOp.VariantKind");
535 llvm_unreachable("bad SymbolicOp.VariantKind");
536536
537537 return true;
538538 }
644644
645645 if (getAvailableFeatures() & ARM::FeatureMClass) {
646646 switch (Op.getImm()) {
647 default: assert(0 && "Unexpected mask value!");
647 default: llvm_unreachable("Unexpected mask value!");
648648 case 0: O << "apsr"; return;
649649 case 1: O << "iapsr"; return;
650650 case 2: O << "eapsr"; return;
667667 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
668668 O << "APSR_";
669669 switch (Mask) {
670 default: assert(0);
670 default: llvm_unreachable("Unexpected mask value!");
671671 case 4: O << "g"; return;
672672 case 8: O << "nzcvq"; return;
673673 case 12: O << "nzcvqg"; return;
1515
1616 #include "llvm/ADT/APFloat.h"
1717 #include "llvm/ADT/APInt.h"
18 #include "llvm/Support/ErrorHandling.h"
1819 #include "llvm/Support/MathExtras.h"
1920 #include
2021
4243
4344 static inline const char *getShiftOpcStr(ShiftOpc Op) {
4445 switch (Op) {
45 default: assert(0 && "Unknown shift opc!");
46 default: llvm_unreachable("Unknown shift opc!");
4647 case ARM_AM::asr: return "asr";
4748 case ARM_AM::lsl: return "lsl";
4849 case ARM_AM::lsr: return "lsr";
5354
5455 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
5556 switch (Op) {
56 default: assert(0 && "Unknown shift opc!");
57 default: llvm_unreachable("Unknown shift opc!");
5758 case ARM_AM::asr: return 2;
5859 case ARM_AM::lsl: return 0;
5960 case ARM_AM::lsr: return 1;
7172
7273 static inline const char *getAMSubModeStr(AMSubMode Mode) {
7374 switch (Mode) {
74 default: assert(0 && "Unknown addressing sub-mode!");
75 default: llvm_unreachable("Unknown addressing sub-mode!");
7576 case ARM_AM::ia: return "ia";
7677 case ARM_AM::ib: return "ib";
7778 case ARM_AM::da: return "da";
568569 }
569570 EltBits = 64;
570571 } else {
571 assert(false && "Unsupported NEON immediate");
572 llvm_unreachable("Unsupported NEON immediate");
572573 }
573574 return Val;
574575 }
162162 unsigned Type = 0;
163163 if (IsPCRel) {
164164 switch ((unsigned)Fixup.getKind()) {
165 default: assert(0 && "Unimplemented");
165 default: llvm_unreachable("Unimplemented");
166166 case FK_Data_4:
167167 switch (Modifier) {
168168 default: llvm_unreachable("Unsupported Modifier");
170170 Type = ELF::R_ARM_REL32;
171171 break;
172172 case MCSymbolRefExpr::VK_ARM_TLSGD:
173 assert(0 && "unimplemented");
174 break;
173 llvm_unreachable("unimplemented");
175174 case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
176175 Type = ELF::R_ARM_TLS_IE32;
177176 break;
247246 case ARM::fixup_arm_thumb_cb:
248247 case ARM::fixup_arm_thumb_cp:
249248 case ARM::fixup_arm_thumb_br:
250 assert(0 && "Unimplemented");
251 break;
249 llvm_unreachable("Unimplemented");
252250 case ARM::fixup_arm_uncondbranch:
253251 Type = ELF::R_ARM_CALL;
254252 break;
165165 SmallVectorImpl &Fixups) const {
166166 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
167167 switch (Mode) {
168 default: assert(0 && "Unknown addressing sub-mode!");
168 default: llvm_unreachable("Unknown addressing sub-mode!");
169169 case ARM_AM::da: return 0;
170170 case ARM_AM::ia: return 1;
171171 case ARM_AM::db: return 2;
831831 // but this is good enough for now.
832832 static bool EvaluateAsPCRel(const MCExpr *Expr) {
833833 switch (Expr->getKind()) {
834 default: assert(0 && "Unexpected expression type");
834 default: llvm_unreachable("Unexpected expression type");
835835 case MCExpr::SymbolRef: return false;
836836 case MCExpr::Binary: return true;
837837 }
855855
856856 MCFixupKind Kind;
857857 switch (ARM16Expr->getKind()) {
858 default: assert(0 && "Unsupported ARMFixup");
858 default: llvm_unreachable("Unsupported ARMFixup");
859859 case ARMMCExpr::VK_ARM_HI16:
860860 if (!isTargetDarwin() && EvaluateAsPCRel(E))
861861 Kind = MCFixupKind(isThumb2()
2020
2121 void ARMMCExpr::PrintImpl(raw_ostream &OS) const {
2222 switch (Kind) {
23 default: assert(0 && "Invalid kind!");
23 default: llvm_unreachable("Invalid kind!");
2424 case VK_ARM_HI16: OS << ":upper16:"; break;
2525 case VK_ARM_LO16: OS << ":lower16:"; break;
2626 }
4444 static void AddValueSymbols_(const MCExpr *Value, MCAssembler *Asm) {
4545 switch (Value->getKind()) {
4646 case MCExpr::Target:
47 assert(0 && "Can't handle nested target expr!");
48 break;
47 llvm_unreachable("Can't handle nested target expr!");
4948
5049 case MCExpr::Constant:
5150 break;
693693 // register. The offset is already handled in the vreg value.
694694 MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
695695 } else {
696 assert(false && "Unexpected opcode!");
696 llvm_unreachable("Unexpected opcode!");
697697 }
698698
699699 // Add predicate back if it's needed.
20322032 int elt_byte = EltNo * VT.getSizeInBits() / 8;
20332033
20342034 switch (VT.getSimpleVT().SimpleTy) {
2035 default:
2036 assert(false && "Invalid value type!");
2035 default: llvm_unreachable("Invalid value type!");
20372036 case MVT::i8: {
20382037 prefslot_begin = prefslot_end = 3;
20392038 break;
23612360 DebugLoc dl = Op.getDebugLoc();
23622361
23632362 switch (VT.getSimpleVT().SimpleTy) {
2364 default:
2365 assert(false && "Invalid value type!");
2363 default: llvm_unreachable("Invalid value type!");
23662364 case MVT::i8: {
23672365 SDValue N = Op.getOperand(0);
23682366 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
13551355 case Instruction::PtrToInt: Out << "PtrToIntInst"; break;
13561356 case Instruction::IntToPtr: Out << "IntToPtrInst"; break;
13571357 case Instruction::BitCast: Out << "BitCastInst"; break;
1358 default: assert(0 && "Unreachable"); break;
1358 default: llvm_unreachable("Unreachable");
13591359 }
13601360 Out << "(" << opNames[0] << ", "
13611361 << getCppName(cst->getType()) << ", \"";
317317 if (Base.isReg())
318318 printOperand(MI, OpNo, O);
319319 else
320 assert(0 && "Unimplemented");
320 llvm_unreachable("Unimplemented");
321321
322322 if (Offset.isImm()) {
323323 if (Offset.getImm())
324324 O << " + #" << Offset.getImm();
325325 }
326326 else
327 assert(0 && "Unimplemented");
327 llvm_unreachable("Unimplemented");
328328
329329 return false;
330330 }
332332 void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI,
333333 unsigned OpNo,
334334 raw_ostream &O) {
335 assert(0 && "Unimplemented");
335 llvm_unreachable("Unimplemented");
336336 }
337337
338338
8383 break;
8484
8585 default:
86 assert(0 && "Cannot handle this case");
86 llvm_unreachable("Cannot handle this case");
8787 }
8888
8989 MI->setDesc(QII->get(NewOpcode));
10981098 ReplaceUses(N, RsPd);
10991099 return RsPd;
11001100 }
1101 assert(0 && "Unexpected value type");
1101 llvm_unreachable("Unexpected value type");
11021102 }
11031103 }
11041104 return SelectCode(N);
11441144 SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
11451145 Ops.push_back(SDVal);
11461146 } else {
1147 assert(0 && "Unimplemented");
1147 llvm_unreachable("Unimplemented");
11481148 }
11491149 }
11501150 EVT ReturnValueVT = N->getValueType(0);
448448 switch (VA.getLocInfo()) {
449449 default:
450450 // Loc info must be one of Full, SExt, ZExt, or AExt.
451 assert(0 && "Unknown loc info!");
451 llvm_unreachable("Unknown loc info!");
452452 case CCValAssign::Full:
453453 break;
454454 case CCValAssign::SExt:
13441344 SDValue
13451345 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13461346 switch (Op.getOpcode()) {
1347 default: assert(0 && "Should not custom lower this!");
1347 default: llvm_unreachable("Should not custom lower this!");
13481348 // Frame & Return address. Currently unimplemented.
13491349 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13501350 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13511351 case ISD::GlobalTLSAddress:
1352 assert(0 && "TLS not implemented for Hexagon.");
1352 llvm_unreachable("TLS not implemented for Hexagon.");
13531353 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
13541354 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
13551355 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
13811381 FuncInfo->addAllocaAdjustInst(MI);
13821382 return BB;
13831383 }
1384 default:
1385 assert(false && "Unexpected instr type to insert");
1384 default: llvm_unreachable("Unexpected instr type to insert");
13861385 } // switch
1387 return NULL;
13881386 }
13891387
13901388 //===----------------------------------------------------------------------===//
14001398 case 'r': // R0-R31
14011399 switch (VT.getSimpleVT().SimpleTy) {
14021400 default:
1403 assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
1401 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
14041402 case MVT::i32:
14051403 case MVT::i16:
14061404 case MVT::i8:
14091407 return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
14101408 }
14111409 default:
1412 assert(0 && "Unknown asm register class");
1410 llvm_unreachable("Unknown asm register class");
14131411 }
14141412 }
14151413
382382 .addFrameIndex(FI).addImm(0)
383383 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
384384 } else {
385 assert(0 && "Unimplemented");
385 llvm_unreachable("Unimplemented");
386386 }
387387 }
388388
394394 const TargetRegisterClass *RC,
395395 SmallVectorImpl &NewMIs) const
396396 {
397 assert(0 && "Unimplemented");
398 return;
397 llvm_unreachable("Unimplemented");
399398 }
400399
401400
426425 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427426 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
428427 } else {
429 assert(0 && "Can't store this register to stack slot");
428 llvm_unreachable("Can't store this register to stack slot");
430429 }
431430 }
432431
435434 SmallVectorImpl &Addr,
436435 const TargetRegisterClass *RC,
437436 SmallVectorImpl &NewMIs) const {
438 assert(0 && "Unimplemented");
437 llvm_unreachable("Unimplemented");
439438 }
440439
441440
822821 } else if (MO.isImm()) {
823822 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
824823 } else {
825 assert(false && "Unexpected operand type");
824 llvm_unreachable("Unexpected operand type");
826825 }
827826 }
828827
12681267 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
12691268 Offset <= Hexagon_MEMB_AUTOINC_MAX);
12701269 }
1271
1272 assert(0 && "Not an auto-inc opc!");
1273
1274 return false;
1270
1271 llvm_unreachable("Not an auto-inc opc!");
12751272 }
12761273
12771274
124124 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
125125 // Hexagon_TODO: add code
126126 } else {
127 assert(0 && "Cannot handle this call frame pseudo instruction");
127 llvm_unreachable("Cannot handle this call frame pseudo instruction");
128128 }
129129 MBB.erase(I);
130130 }
304304 }
305305
306306 unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
307 assert(0 && "What is the exception register");
308 return 0;
307 llvm_unreachable("What is the exception register");
309308 }
310309
311310 unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
312 assert(0 && "What is the exception handler register");
313 return 0;
311 llvm_unreachable("What is the exception handler register");
314312 }
315313
316314 #define GET_REGINFO_TARGET_DESC
101101 unsigned RelTy) const {
102102 if (RelTy == ELF::R_MICROBLAZE_32_PCREL || ELF::R_MICROBLAZE_64_PCREL)
103103 return SymOffset - (RelOffset + 4);
104 else
105 assert(0 && "computeRelocation unknown for this relocation type");
106104
107 return 0;
105 llvm_unreachable("computeRelocation unknown for this relocation type");
108106 }
215215 MachineBasicBlock *MBB)
216216 const {
217217 switch (MI->getOpcode()) {
218 default: assert(false && "Unexpected instr type to insert");
218 default: llvm_unreachable("Unexpected instr type to insert");
219219
220220 case MBlaze::ShiftRL:
221221 case MBlaze::ShiftRA:
8484 MCSymbol *MBlazeMCInstLower::
8585 GetBlockAddressSymbol(const MachineOperand &MO) const {
8686 switch (MO.getTargetFlags()) {
87 default:
88 assert(0 && "Unknown target flag on GV operand");
89
87 default: llvm_unreachable("Unknown target flag on GV operand");
9088 case 0: break;
9189 }
9290
2626
2727 static unsigned getFixupKindSize(unsigned Kind) {
2828 switch (Kind) {
29 default: assert(0 && "invalid fixup kind!");
29 default: llvm_unreachable("invalid fixup kind!");
3030 case FK_Data_1: return 1;
3131 case FK_PCRel_2:
3232 case FK_Data_2: return 2;
5353
5454 static unsigned GetMBlazeRegNum(const MCOperand &MO) {
5555 // FIXME: getMBlazeRegisterNumbering() is sufficient?
56 assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented.");
57 return 0;
56 llvm_unreachable("MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet "
57 "implemented.");
5858 }
5959
6060 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
6464 raw_ostream &O, const char *Modifier) {
6565 const MachineOperand &MO = MI->getOperand(OpNum);
6666 switch (MO.getType()) {
67 default: assert(0 && "Not implemented yet!");
67 default: llvm_unreachable("Not implemented yet!");
6868 case MachineOperand::MO_Register:
6969 O << MSP430InstPrinter::getRegisterName(MO.getReg());
7070 return;
592592 // Expand non-constant shifts to loops:
593593 if (!isa(N->getOperand(1)))
594594 switch (Opc) {
595 default:
596 assert(0 && "Invalid shift opcode!");
595 default: llvm_unreachable("Invalid shift opcode!");
597596 case ISD::SHL:
598597 return DAG.getNode(MSP430ISD::SHL, dl,
599598 VT, N->getOperand(0), N->getOperand(1));
10211020 unsigned Opc;
10221021 const TargetRegisterClass * RC;
10231022 switch (MI->getOpcode()) {
1024 default:
1025 assert(0 && "Invalid shift opcode!");
1023 default: llvm_unreachable("Invalid shift opcode!");
10261024 case MSP430::Shl8:
10271025 Opc = MSP430::SHL8r1;
10281026 RC = MSP430::GR8RegisterClass;
129129 MSP430CC::CondCodes CC = static_cast(Cond[0].getImm());
130130
131131 switch (CC) {
132 default:
133 assert(0 && "Invalid branch condition!");
134 break;
132 default: llvm_unreachable("Invalid branch condition!");
135133 case MSP430CC::COND_E:
136134 CC = MSP430CC::COND_NE;
137135 break;
296294 switch (Desc.TSFlags & MSP430II::SizeMask) {
297295 default:
298296 switch (Desc.getOpcode()) {
299 default:
300 assert(0 && "Unknown instruction size!");
297 default: llvm_unreachable("Unknown instruction size!");
301298 case TargetOpcode::PROLOG_LABEL:
302299 case TargetOpcode::EH_LABEL:
303300 case TargetOpcode::IMPLICIT_DEF:
313310 }
314311 case MSP430II::SizeSpecial:
315312 switch (MI->getOpcode()) {
316 default:
317 assert(0 && "Unknown instruction size!");
313 default: llvm_unreachable("Unknown instruction size!");
318314 case MSP430::SAR8r1c:
319315 case MSP430::SAR16r1c:
320316 return 4;
3838 MCSymbol *MSP430MCInstLower::
3939 GetExternalSymbolSymbol(const MachineOperand &MO) const {
4040 switch (MO.getTargetFlags()) {
41 default: assert(0 && "Unknown target flag on GV operand");
41 default: llvm_unreachable("Unknown target flag on GV operand");
4242 case 0: break;
4343 }
4444
8080 MCSymbol *MSP430MCInstLower::
8181 GetBlockAddressSymbol(const MachineOperand &MO) const {
8282 switch (MO.getTargetFlags()) {
83 default: assert(0 && "Unknown target flag on GV operand");
83 default: llvm_unreachable("Unknown target flag on GV operand");
8484 case 0: break;
8585 }
8686
115115 switch (MO.getType()) {
116116 default:
117117 MI->dump();
118 assert(0 && "unknown operand type");
118 llvm_unreachable("unknown operand type");
119119 case MachineOperand::MO_Register:
120120 // Ignore all implicit register operands.
121121 if (MO.isImplicit()) continue;
9191 MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
9292
9393 switch (Kind) {
94 default: assert(0 && "Invalid kind!");
94 default: llvm_unreachable("Invalid kind!");
9595 case MCSymbolRefExpr::VK_None: break;
9696 case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break;
9797 case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;
809809 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
810810 MachineBasicBlock *BB) const {
811811 switch (MI->getOpcode()) {
812 default:
813 assert(false && "Unexpected instr type to insert");
814 return NULL;
812 default: llvm_unreachable("Unexpected instr type to insert");
815813 case Mips::ATOMIC_LOAD_ADD_I8:
816814 case Mips::ATOMIC_LOAD_ADD_I8_P8:
817815 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
3636 const MCSymbol *Symbol;
3737
3838 switch(MO.getTargetFlags()) {
39 default: assert(0 && "Invalid target flag!");
39 default: llvm_unreachable("Invalid target flag!");
4040 case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
4141 case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
4242 case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
175175 MachineOperandType MOTy = MO.getType();
176176
177177 switch (MOTy) {
178 default:
179 assert(0 && "unknown operand type");
180 break;
178 default: llvm_unreachable("unknown operand type");
181179 case MachineOperand::MO_Register:
182180 // Ignore all implicit register operands.
183181 if (MO.isImplicit()) break;
314312 }
315313 default:
316314 // FIXME: need to add others
317 assert(0 && "unaligned instruction not processed");
315 llvm_unreachable("unaligned instruction not processed");
318316 }
319317
320318 MCInsts.push_back(Instr1);
299299 unsigned SrcReg, bool isKill, int FrameIdx,
300300 const TargetRegisterClass *RC,
301301 const TargetRegisterInfo *TRI) const {
302 assert(false && "storeRegToStackSlot should not be called for PTX");
302 llvm_unreachable("storeRegToStackSlot should not be called for PTX");
303303 }
304304
305305 void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
307307 unsigned DestReg, int FrameIdx,
308308 const TargetRegisterClass *RC,
309309 const TargetRegisterInfo *TRI) const {
310 assert(false && "loadRegFromStackSlot should not be called for PTX");
310 llvm_unreachable("loadRegFromStackSlot should not be called for PTX");
311311 }
312312
313313 // static helper routines
173173 unsigned CCReg = MI->getOperand(OpNo).getReg();
174174 unsigned RegNo;
175175 switch (CCReg) {
176 default: assert(0 && "Unknown CR register");
176 default: llvm_unreachable("Unknown CR register");
177177 case PPC::CR0: RegNo = 0; break;
178178 case PPC::CR1: RegNo = 1; break;
179179 case PPC::CR2: RegNo = 2; break;
9191 const MCInstFragment *DF,
9292 const MCAsmLayout &Layout) const {
9393 // FIXME.
94 assert(0 && "relaxInstruction() unimplemented");
95 return false;
94 llvm_unreachable("relaxInstruction() unimplemented");
9695 }
9796
9897
9998 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
10099 // FIXME.
101 assert(0 && "relaxInstruction() unimplemented");
100 llvm_unreachable("relaxInstruction() unimplemented");
102101 }
103102
104103 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
127126
128127 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
129128 uint64_t Value) const {
130 assert(0 && "UNIMP");
129 llvm_unreachable("UNIMP");
131130 }
132131
133132 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
45774577 DebugLoc dl = N->getDebugLoc();
45784578 switch (N->getOpcode()) {
45794579 default:
4580 assert(false && "Do not know how to custom type legalize this operation!");
4581 return;
4580 llvm_unreachable("Do not know how to custom type legalize this operation!");
45824581 case ISD::VAARG: {
45834582 if (!TM.getSubtarget().isSVR4ABI()
45844583 || TM.getSubtarget().isPPC64())
139139 switch (MO.getType()) {
140140 default:
141141 MI->dump();
142 assert(0 && "unknown operand type");
142 llvm_unreachable("unknown operand type");
143143 case MachineOperand::MO_Register:
144144 assert(!MO.getSubReg() && "Subregs should be eliminated!");
145145 MCOp = MCOperand::CreateReg(MO.getReg());
141141 std::string operand = "";
142142 const MachineOperand &MO = MI->getOperand(opNum);
143143 switch (MO.getType()) {
144 default: assert(0 && "Operand is not a register ");
144 default: llvm_unreachable("Operand is not a register");
145145 case MachineOperand::MO_Register:
146146 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
147147 "Operand is not a physical register ");