llvm.org GIT mirror llvm / bc20d3b
[X86] Remove useless target specific combine on TRUNCATE dag nodes. Before revision 171146, function 'PerformTruncateCombine' used to perform a premature lowering of TRUNCATE dag nodes. Revision 171146 then moved all the logic implemented by PerformTruncateCombine to a custom lowering hook. However, that revision forgot to delete function PerformTruncateCombine from the code. This patch removes function 'PerformTruncateCombine' since it has no effect on the SelectionDAG. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237122 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 5 years ago
1 changed file(s) with 0 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
15851585 setTargetDAGCombine(ISD::ANY_EXTEND);
15861586 setTargetDAGCombine(ISD::SIGN_EXTEND);
15871587 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1588 setTargetDAGCombine(ISD::TRUNCATE);
15891588 setTargetDAGCombine(ISD::SINT_TO_FP);
15901589 setTargetDAGCombine(ISD::SETCC);
15911590 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
2073320732 return SDValue();
2073420733 }
2073520734
20736 /// PerformTruncateCombine - Converts truncate operation to
20737 /// a sequence of vector shuffle operations.
20738 /// It is possible when we truncate 256-bit vector to 128-bit vector
20739 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20740 TargetLowering::DAGCombinerInfo &DCI,
20741 const X86Subtarget *Subtarget) {
20742 return SDValue();
20743 }
20744
2074520735 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
2074620736 /// specific shuffle of a load can be folded into a single element load.
2074720737 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
2430424294 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
2430524295 case ISD::SIGN_EXTEND_INREG:
2430624296 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24307 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
2430824297 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
2430924298 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
2431024299 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);