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[NFC] Rename minnan and maxnan to minimum and maximum Summary: Changes all uses of minnan/maxnan to minimum/maximum globally. These names emphasize that the semantic difference between these operations is more than just NaN-propagation. Reviewers: arsenm, aheejin, dschuff, javed.absar Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345218 91177308-0d34-0410-b5e6-96231b3b80d8 Thomas Lively 10 months ago
27 changed file(s) with 124 addition(s) and 127 deletion(s). Raw diff Collapse all Expand all
10721072 case Intrinsic::minnum:
10731073 ISDs.push_back(ISD::FMINNUM);
10741074 if (FMF.noNaNs())
1075 ISDs.push_back(ISD::FMINNAN);
1075 ISDs.push_back(ISD::FMINIMUM);
10761076 break;
10771077 case Intrinsic::maxnum:
10781078 ISDs.push_back(ISD::FMAXNUM);
10791079 if (FMF.noNaNs())
1080 ISDs.push_back(ISD::FMAXNAN);
1080 ISDs.push_back(ISD::FMAXIMUM);
10811081 break;
10821082 case Intrinsic::copysign:
10831083 ISDs.push_back(ISD::FCOPYSIGN);
576576 /// signaling NaN, returns a quiet NaN.
577577 FMINNUM_IEEE, FMAXNUM_IEEE,
578578
579 /// FMINNAN/FMAXNAN - NaN-propagating minimum/maximum that also treat -0.0
580 /// as less than 0.0. While FMINNUM/FMAXNUM follow IEEE 754-2008 semantics,
581 /// FMINNAN/FMAXNAN follow IEEE 754-2018 draft semantics.
582 FMINNAN, FMAXNAN,
579 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
580 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
581 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
582 FMINIMUM, FMAXIMUM,
583583
584584 /// FSINCOS - Compute both fsin and fcos as a single operation.
585585 FSINCOS,
20982098 case ISD::ADDE:
20992099 case ISD::FMINNUM:
21002100 case ISD::FMAXNUM:
2101 case ISD::FMINNAN:
2102 case ISD::FMAXNAN:
2101 case ISD::FMINIMUM:
2102 case ISD::FMAXIMUM:
21032103 return true;
21042104 default: return false;
21052105 }
412412 [SDNPCommutative]>;
413413 def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
414414 [SDNPCommutative]>;
415
416 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
417 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
415 def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp>;
416 def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp>;
418417 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
419418 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
420419 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
370370 SDValue visitFFLOOR(SDNode *N);
371371 SDValue visitFMINNUM(SDNode *N);
372372 SDValue visitFMAXNUM(SDNode *N);
373 SDValue visitFMINNAN(SDNode *N);
374 SDValue visitFMAXNAN(SDNode *N);
373 SDValue visitFMINIMUM(SDNode *N);
374 SDValue visitFMAXIMUM(SDNode *N);
375375 SDValue visitBRCOND(SDNode *N);
376376 SDValue visitBR_CC(SDNode *N);
377377 SDValue visitLOAD(SDNode *N);
15831583 case ISD::FFLOOR: return visitFFLOOR(N);
15841584 case ISD::FMINNUM: return visitFMINNUM(N);
15851585 case ISD::FMAXNUM: return visitFMAXNUM(N);
1586 case ISD::FMINNAN: return visitFMINNAN(N);
1587 case ISD::FMAXNAN: return visitFMAXNAN(N);
1586 case ISD::FMINIMUM: return visitFMINIMUM(N);
1587 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
15881588 case ISD::FCEIL: return visitFCEIL(N);
15891589 case ISD::FTRUNC: return visitFTRUNC(N);
15901590 case ISD::BRCOND: return visitBRCOND(N);
1215712157 return visitFMinMax(DAG, N, maxnum);
1215812158 }
1215912159
12160 SDValue DAGCombiner::visitFMINNAN(SDNode *N) {
12160 SDValue DAGCombiner::visitFMINIMUM(SDNode *N) {
1216112161 return visitFMinMax(DAG, N, minimum);
1216212162 }
1216312163
12164 SDValue DAGCombiner::visitFMAXNAN(SDNode *N) {
12164 SDValue DAGCombiner::visitFMAXIMUM(SDNode *N) {
1216512165 return visitFMinMax(DAG, N, maximum);
1216612166 }
1216712167
19091909 // Binary FP Operations
19101910 case ISD::FADD:
19111911 case ISD::FDIV:
1912 case ISD::FMAXNAN:
1913 case ISD::FMINNAN:
1912 case ISD::FMAXIMUM:
1913 case ISD::FMINIMUM:
19141914 case ISD::FMAXNUM:
19151915 case ISD::FMINNUM:
19161916 case ISD::FMUL:
355355 case ISD::FMAXNUM:
356356 case ISD::FMINNUM_IEEE:
357357 case ISD::FMAXNUM_IEEE:
358 case ISD::FMINNAN:
359 case ISD::FMAXNAN:
358 case ISD::FMINIMUM:
359 case ISD::FMAXIMUM:
360360 case ISD::FCOPYSIGN:
361361 case ISD::FSQRT:
362362 case ISD::FSIN:
114114 case ISD::FMAXNUM:
115115 case ISD::FMINNUM_IEEE:
116116 case ISD::FMAXNUM_IEEE:
117 case ISD::FMINNAN:
118 case ISD::FMAXNAN:
117 case ISD::FMINIMUM:
118 case ISD::FMAXIMUM:
119119 case ISD::SMIN:
120120 case ISD::SMAX:
121121 case ISD::UMIN:
785785 case ISD::FMUL:
786786 case ISD::FMINNUM:
787787 case ISD::FMAXNUM:
788 case ISD::FMINNAN:
789 case ISD::FMAXNAN:
788 case ISD::FMINIMUM:
789 case ISD::FMAXIMUM:
790790 case ISD::SDIV:
791791 case ISD::UDIV:
792792 case ISD::FDIV:
18031803 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
18041804 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
18051805 case ISD::VECREDUCE_FMAX:
1806 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN;
1806 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
18071807 break;
18081808 case ISD::VECREDUCE_FMIN:
1809 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN;
1809 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
18101810 break;
18111811 default:
18121812 llvm_unreachable("Unexpected reduce ISD node");
23552355 case ISD::XOR:
23562356 case ISD::FMINNUM:
23572357 case ISD::FMAXNUM:
2358 case ISD::FMINNAN:
2359 case ISD::FMAXNAN:
2358 case ISD::FMINIMUM:
2359 case ISD::FMAXIMUM:
23602360 case ISD::SMIN:
23612361 case ISD::SMAX:
23622362 case ISD::UMIN:
37293729 (isKnownNeverNaN(Op.getOperand(1), false, Depth + 1) &&
37303730 isKnownNeverSNaN(Op.getOperand(0), Depth + 1));
37313731 }
3732 case ISD::FMINNAN:
3733 case ISD::FMAXNAN: {
3732 case ISD::FMINIMUM:
3733 case ISD::FMAXIMUM: {
37343734 // TODO: Does this quiet or return the origina NaN as-is?
37353735 return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
37363736 isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
3737
37383737 }
37393738 case ISD::EXTRACT_VECTOR_ELT: {
37403739 return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
29712971 case SPF_FMINNUM:
29722972 switch (SPR.NaNBehavior) {
29732973 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2974 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2974 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
29752975 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
29762976 case SPNB_RETURNS_ANY: {
29772977 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
29782978 Opc = ISD::FMINNUM;
2979 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2980 Opc = ISD::FMINNAN;
2979 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
2980 Opc = ISD::FMINIMUM;
29812981 else if (UseScalarMinMax)
29822982 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2983 ISD::FMINNUM : ISD::FMINNAN;
2983 ISD::FMINNUM : ISD::FMINIMUM;
29842984 break;
29852985 }
29862986 }
29882988 case SPF_FMAXNUM:
29892989 switch (SPR.NaNBehavior) {
29902990 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2991 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2991 case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
29922992 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
29932993 case SPNB_RETURNS_ANY:
29942994
29952995 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
29962996 Opc = ISD::FMAXNUM;
2997 else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2998 Opc = ISD::FMAXNAN;
2997 else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
2998 Opc = ISD::FMAXIMUM;
29992999 else if (UseScalarMinMax)
30003000 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3001 ISD::FMAXNUM : ISD::FMAXNAN;
3001 ISD::FMAXNUM : ISD::FMAXIMUM;
30023002 break;
30033003 }
30043004 break;
55645564 case Intrinsic::minnum: {
55655565 auto VT = getValue(I.getArgOperand(0)).getValueType();
55665566 unsigned Opc =
5567 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)
5568 ? ISD::FMINNAN
5567 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)
5568 ? ISD::FMINIMUM
55695569 : ISD::FMINNUM;
55705570 setValue(&I, DAG.getNode(Opc, sdl, VT,
55715571 getValue(I.getArgOperand(0)),
55755575 case Intrinsic::maxnum: {
55765576 auto VT = getValue(I.getArgOperand(0)).getValueType();
55775577 unsigned Opc =
5578 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)
5579 ? ISD::FMAXNAN
5578 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)
5579 ? ISD::FMAXIMUM
55805580 : ISD::FMAXNUM;
55815581 setValue(&I, DAG.getNode(Opc, sdl, VT,
55825582 getValue(I.getArgOperand(0)),
55845584 return nullptr;
55855585 }
55865586 case Intrinsic::minimum:
5587 setValue(&I, DAG.getNode(ISD::FMINNAN, sdl,
5587 setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
55885588 getValue(I.getArgOperand(0)).getValueType(),
55895589 getValue(I.getArgOperand(0)),
55905590 getValue(I.getArgOperand(1))));
55915591 return nullptr;
55925592 case Intrinsic::maximum:
5593 setValue(&I, DAG.getNode(ISD::FMAXNAN, sdl,
5593 setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl,
55945594 getValue(I.getArgOperand(0)).getValueType(),
55955595 getValue(I.getArgOperand(0)),
55965596 getValue(I.getArgOperand(1))));
177177 case ISD::FMAXNUM: return "fmaxnum";
178178 case ISD::FMINNUM_IEEE: return "fminnum_ieee";
179179 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
180
181 case ISD::FMINNAN: return "fminnan";
182 case ISD::FMAXNAN: return "fmaxnan";
180 case ISD::FMINIMUM: return "fminimum";
181 case ISD::FMAXIMUM: return "fmaximum";
183182 case ISD::FNEG: return "fneg";
184183 case ISD::FSQRT: return "fsqrt";
185184 case ISD::STRICT_FSQRT: return "strict_fsqrt";
601601 setOperationAction(ISD::FMAXNUM, VT, Expand);
602602 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
603603 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
604 setOperationAction(ISD::FMINNAN, VT, Expand);
605 setOperationAction(ISD::FMAXNAN, VT, Expand);
604 setOperationAction(ISD::FMINIMUM, VT, Expand);
605 setOperationAction(ISD::FMAXIMUM, VT, Expand);
606606 setOperationAction(ISD::FMAD, VT, Expand);
607607 setOperationAction(ISD::SMIN, VT, Expand);
608608 setOperationAction(ISD::SMAX, VT, Expand);
384384 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
385385 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
386386 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
387 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
388 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
387 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
388 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
389389
390390 // promote v4f16 to v4f32 when that is known to be safe.
391391 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
449449 setOperationAction(ISD::FROUND, Ty, Legal);
450450 setOperationAction(ISD::FMINNUM, Ty, Legal);
451451 setOperationAction(ISD::FMAXNUM, Ty, Legal);
452 setOperationAction(ISD::FMINNAN, Ty, Legal);
453 setOperationAction(ISD::FMAXNAN, Ty, Legal);
452 setOperationAction(ISD::FMINIMUM, Ty, Legal);
453 setOperationAction(ISD::FMAXIMUM, Ty, Legal);
454454 }
455455
456456 if (Subtarget->hasFullFP16()) {
462462 setOperationAction(ISD::FROUND, MVT::f16, Legal);
463463 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
464464 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
465 setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
466 setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
465 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
466 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
467467 }
468468
469469 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
815815 // F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
816816 if (VT.isFloatingPoint() &&
817817 (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
818 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
819 ISD::FMINNUM, ISD::FMAXNUM})
818 for (unsigned Opcode :
819 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
820820 setOperationAction(Opcode, VT, Legal);
821821
822822 if (Subtarget->isLittleEndian()) {
98669866 case Intrinsic::aarch64_neon_umaxv:
98679867 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
98689868 case Intrinsic::aarch64_neon_fmax:
9869 return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),
9869 return DAG.getNode(ISD::FMAXIMUM, SDLoc(N), N->getValueType(0),
98709870 N->getOperand(1), N->getOperand(2));
98719871 case Intrinsic::aarch64_neon_fmin:
9872 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
9872 return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0),
98739873 N->getOperand(1), N->getOperand(2));
98749874 case Intrinsic::aarch64_neon_fmaxnm:
98759875 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
30493049 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
30503050 }
30513051 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
3052 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
3052 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>;
30533053 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
3054 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
3054 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>;
30553055 let SchedRW = [WriteFMul] in {
30563056 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
30573057 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
30583058 }
30593059 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
30603060
3061 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3061 def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
30623062 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
3063 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3063 def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
30643064 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
30653065 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
30663066 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
33863386 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
33873387 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>;
33883388 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;
3389 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>;
3389 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>;
33903390 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;
33913391 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>;
33923392 defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
3393 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
3393 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>;
33943394
33953395 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
33963396 // instruction expects the addend first, while the fma intrinsic puts it last.
11421142 if (Subtarget->hasNEON()) {
11431143 // vmin and vmax aren't available in a scalar form, so we use
11441144 // a NEON instruction with an undef lane instead.
1145 setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
1146 setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
1147 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1148 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1149 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1150 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1151 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1152 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1145 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1146 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1147 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1148 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1149 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1150 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1151 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1152 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
11531153
11541154 if (Subtarget->hasFullFP16()) {
11551155 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
11571157 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
11581158 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
11591159
1160 setOperationAction(ISD::FMINNAN, MVT::v4f16, Legal);
1161 setOperationAction(ISD::FMAXNAN, MVT::v4f16, Legal);
1162 setOperationAction(ISD::FMINNAN, MVT::v8f16, Legal);
1163 setOperationAction(ISD::FMAXNAN, MVT::v8f16, Legal);
1160 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1161 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1162 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1163 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
11641164 }
11651165 }
11661166
34073407 Op.getOperand(1), Op.getOperand(2));
34083408 }
34093409 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3410 ? ISD::FMINNAN : ISD::FMAXNAN;
3410 ? ISD::FMINIMUM : ISD::FMAXIMUM;
34113411 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
34123412 Op.getOperand(1), Op.getOperand(2));
34133413 }
55205520 "vmax", "u", umax, 1>;
55215521 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
55225522 "vmax", "f32",
5523 v2f32, v2f32, fmaxnan, 1>;
5523 v2f32, v2f32, fmaximum, 1>;
55245524 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
55255525 "vmax", "f32",
5526 v4f32, v4f32, fmaxnan, 1>;
5526 v4f32, v4f32, fmaximum, 1>;
55275527 def VMAXhd : N3VDInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBIND,
55285528 "vmax", "f16",
5529 v4f16, v4f16, fmaxnan, 1>,
5529 v4f16, v4f16, fmaximum, 1>,
55305530 Requires<[HasNEON, HasFullFP16]>;
55315531 def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ,
55325532 "vmax", "f16",
5533 v8f16, v8f16, fmaxnan, 1>,
5533 v8f16, v8f16, fmaximum, 1>,
55345534 Requires<[HasNEON, HasFullFP16]>;
55355535
55365536 // VMAXNM
55625562 "vmin", "u", umin, 1>;
55635563 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
55645564 "vmin", "f32",
5565 v2f32, v2f32, fminnan, 1>;
5565 v2f32, v2f32, fminimum, 1>;
55665566 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
55675567 "vmin", "f32",
5568 v4f32, v4f32, fminnan, 1>;
5568 v4f32, v4f32, fminimum, 1>;
55695569 def VMINhd : N3VDInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBIND,
55705570 "vmin", "f16",
5571 v4f16, v4f16, fminnan, 1>,
5571 v4f16, v4f16, fminimum, 1>,
55725572 Requires<[HasNEON, HasFullFP16]>;
55735573 def VMINhq : N3VQInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBINQ,
55745574 "vmin", "f16",
5575 v8f16, v8f16, fminnan, 1>,
5575 v8f16, v8f16, fminimum, 1>,
55765576 Requires<[HasNEON, HasFullFP16]>;
55775577
55785578 // VMINNM
70927092 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
70937093 def : N2VSPat;
70947094 def : N2VSPat;
7095 def : N3VSPatFP16, Requires<[HasFullFP16]>;
7096 def : N3VSPatFP16, Requires<[HasFullFP16]>;
7097 def : N3VSPat, Requires<[HasNEON]>;
7098 def : N3VSPat, Requires<[HasNEON]>;
7095 def : N3VSPatFP16, Requires<[HasFullFP16]>;
7096 def : N3VSPatFP16, Requires<[HasFullFP16]>;
7097 def : N3VSPat, Requires<[HasNEON]>;
7098 def : N3VSPat, Requires<[HasNEON]>;
70997099 def : NVCVTFIPat;
71007100 def : NVCVTFIPat;
71017101 def : NVCVTIFPat;
157157 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
158158 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
159159 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
160 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
161 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
160 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
161 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
162162
163163 setTargetDAGCombine(ISD::AND);
164164 setTargetDAGCombine(ISD::OR);
559559 }
560560 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
561561 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
562 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
563 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
562 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
563 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
564564
565565 // No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate.
566566 // No FPOW or FREM in PTX.
451451 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
452452
453453 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
454 setOperationAction(ISD::FMAXNAN, MVT::f64, Legal);
454 setOperationAction(ISD::FMAXIMUM, MVT::f64, Legal);
455455 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
456 setOperationAction(ISD::FMINNAN, MVT::f64, Legal);
456 setOperationAction(ISD::FMINIMUM, MVT::f64, Legal);
457457
458458 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal);
459 setOperationAction(ISD::FMAXNAN, MVT::v2f64, Legal);
459 setOperationAction(ISD::FMAXIMUM, MVT::v2f64, Legal);
460460 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
461 setOperationAction(ISD::FMINNAN, MVT::v2f64, Legal);
461 setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal);
462462
463463 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
464 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
464 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
465465 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
466 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
466 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
467467
468468 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
470470 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
471 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
471 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
472472
473473 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal);
474 setOperationAction(ISD::FMAXNAN, MVT::f128, Legal);
474 setOperationAction(ISD::FMAXIMUM, MVT::f128, Legal);
475475 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
476 setOperationAction(ISD::FMINNAN, MVT::f128, Legal);
476 setOperationAction(ISD::FMINIMUM, MVT::f128, Legal);
477477 }
478478
479479 // We have fused multiply-addition for f32 and f64 but not f128.
10301030 // Maximum.
10311031 multiclass VectorMax {
10321032 def : FPMinMax;
1033 def : FPMinMaxnan, tr, 1>;
1033 def : FPMinMaximum, tr, 1>;
10341034 }
10351035 let Predicates = [FeatureVectorEnhancements1] in {
10361036 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>;
10541054 // Minimum.
10551055 multiclass VectorMin {
10561056 def : FPMinMax;
1057 def : FPMinMaxnan, tr, 1>;
1057 def : FPMinMaximum, tr, 1>;
10581058 }
10591059 let Predicates = [FeatureVectorEnhancements1] in {
10601060 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>;
104104 for (auto Op :
105105 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
106106 setOperationAction(Op, T, Legal);
107 // Support minnan and maxnan, which otherwise default to expand.
108 setOperationAction(ISD::FMINNAN, T, Legal);
109 setOperationAction(ISD::FMAXNAN, T, Legal);
107 // Support minimum and maximum, which otherwise default to expand.
108 setOperationAction(ISD::FMINIMUM, T, Legal);
109 setOperationAction(ISD::FMAXIMUM, T, Legal);
110110 // WebAssembly currently has no builtin f16 support.
111111 setOperationAction(ISD::FP16_TO_FP, T, Expand);
112112 setOperationAction(ISD::FP_TO_FP16, T, Expand);
5757 defm COPYSIGN : BinaryFP;
5858
5959 let isCommutable = 1 in {
60 defm MIN : BinaryFP;
61 defm MAX : BinaryFP>;
60 defm MIN : BinaryFP>;
61 defm MAX : BinaryFP;
6262 } // isCommutable = 1
6363
6464 defm CEIL : UnaryFP;
756756 }
757757
758758 // NaN-propagating minimum: min
759 defm MIN : SIMDBinaryFPnan, "min", 129>;
759 defm MIN : SIMDBinaryFPimum, "min", 129>;
760760
761761 // NaN-propagating maximum: max
762 defm MAX : SIMDBinaryFPnan, "max", 131>;
762 defm MAX : SIMDBinaryFPimum, "max", 131>;
763763
764764 //===----------------------------------------------------------------------===//
765765 // Floating-point arithmetic
643643 ret void
644644 }
645645
646 ; CHECK-ALL-LABEL: test_minnan:
646 ; CHECK-ALL-LABEL: test_minimum:
647647 ; CHECK-FP16: vmov.f32 s0, #1.000000e+00
648648 ; CHECK-FP16: vcvtb.f32.f16
649649 ; CHECK-LIBCALL: bl __aeabi_h2f
653653 ; CHECK-NOVFP: bl __aeabi_fcmpge
654654 ; CHECK-FP16: vcvtb.f16.f32
655655 ; CHECK-LIBCALL: bl __aeabi_f2h
656 define void @test_minnan(half* %p) #0 {
656 define void @test_minimum(half* %p) #0 {
657657 %a = load half, half* %p, align 2
658658 %c = fcmp ult half %a, 1.0
659659 %r = select i1 %c, half %a, half 1.0
661661 ret void
662662 }
663663
664 ; CHECK-ALL-LABEL: test_maxnan:
664 ; CHECK-ALL-LABEL: test_maximum:
665665 ; CHECK-FP16: vmov.f32 s0, #1.000000e+00
666666 ; CHECK-FP16: vcvtb.f32.f16
667667 ; CHECK-LIBCALL: bl __aeabi_h2f
671671 ; CHECK-NOVFP: bl __aeabi_fcmple
672672 ; CHECK-FP16: vcvtb.f16.f32
673673 ; CHECK-LIBCALL: bl __aeabi_f2h
674 define void @test_maxnan(half* %p) #0 {
674 define void @test_maximum(half* %p) #0 {
675675 %a = load half, half* %p, align 2
676676 %c = fcmp ugt half %a, 1.0
677677 %r = select i1 %c, half %a, half 1.0
4141 ret double %ret
4242 }
4343
44 ; Test a f64 constant compare/select resulting in maxnan.
44 ; Test a f64 constant compare/select resulting in maximum.
4545 define double @f4(double %dummy, double %val) {
4646 ; CHECK-LABEL: f4:
4747 ; CHECK: lzdr [[REG:%f[0-9]+]]
9191 ret float %ret
9292 }
9393
94 ; Test a f32 constant compare/select resulting in maxnan.
94 ; Test a f32 constant compare/select resulting in maximum.
9595 define float @f14(float %dummy, float %val) {
9696 ; CHECK-LABEL: f14:
9797 ; CHECK: lzer [[REG:%f[0-9]+]]
157157 ret void
158158 }
159159
160 ; Test a f128 constant compare/select resulting in maxnan.
160 ; Test a f128 constant compare/select resulting in maximum.
161161 define void @f24(fp128 *%ptr, fp128 *%dst) {
162162 ; CHECK-LABEL: f24:
163163 ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
4141 ret double %ret
4242 }
4343
44 ; Test a f64 constant compare/select resulting in minnan.
44 ; Test a f64 constant compare/select resulting in minimum.
4545 define double @f4(double %dummy, double %val) {
4646 ; CHECK-LABEL: f4:
4747 ; CHECK: lzdr [[REG:%f[0-9]+]]
9191 ret float %ret
9292 }
9393
94 ; Test a f32 constant compare/select resulting in minnan.
94 ; Test a f32 constant compare/select resulting in minimum.
9595 define float @f14(float %dummy, float %val) {
9696 ; CHECK-LABEL: f14:
9797 ; CHECK: lzer [[REG:%f[0-9]+]]
157157 ret void
158158 }
159159
160 ; Test a f128 constant compare/select resulting in minnan.
160 ; Test a f128 constant compare/select resulting in minimum.
161161 define void @f24(fp128 *%ptr, fp128 *%dst) {
162162 ; CHECK-LABEL: f24:
163163 ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
148148 expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true});
149149 }
150150
151 TEST_F(MatchSelectPatternTest, VectorFMinNaN) {
151 TEST_F(MatchSelectPatternTest, VectorFMinimum) {
152152 parseAssembly(
153153 "define <4 x float> @test(<4 x float> %a) {\n"
154154 " %1 = fcmp ule <4 x float> %a, \n"
176176 expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true});
177177 }
178178
179 TEST_F(MatchSelectPatternTest, VectorNotFMinNaN) {
179 TEST_F(MatchSelectPatternTest, VectorNotFMinimum) {
180180 parseAssembly(
181181 "define <4 x float> @test(<4 x float> %a) {\n"
182182 " %1 = fcmp ule <4 x float> %a, \n"