llvm.org GIT mirror llvm / bb51742
Fix edge cases of ARM shift operands in arith instructions. As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 8 years ago
3 changed file(s) with 95 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
301301 O << getRegisterName(MO1.getReg());
302302
303303 // Print the shift opc.
304 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
305 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
306 if (ShOpc == ARM_AM::rrx)
307 return;
308 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
304 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
305 ARM_AM::getSORegOffset(MO2.getImm()));
309306 }
310307
311308
339336 O << "]";
340337 }
341338
342 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
343 raw_ostream &O) {
344 const MCOperand &MO1 = MI->getOperand(Op);
345 const MCOperand &MO2 = MI->getOperand(Op+1);
346 const MCOperand &MO3 = MI->getOperand(Op+2);
347
348 O << "[" << getRegisterName(MO1.getReg()) << "], ";
349
350 if (!MO2.getReg()) {
351 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
352 O << '#'
353 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
354 << ImmOffs;
355 return;
356 }
357
358 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
359 << getRegisterName(MO2.getReg());
360
361 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
362 O << ", "
363 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
364 << " #" << ShImm;
365 }
366
367339 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
368340 raw_ostream &O) {
369341 const MCOperand &MO1 = MI->getOperand(Op);
391363
392364 const MCOperand &MO3 = MI->getOperand(Op+2);
393365 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
394
395 if (IdxMode == ARMII::IndexModePost) {
396 printAM2PostIndexOp(MI, Op, O);
397 return;
398 }
366 assert(IdxMode != ARMII::IndexModePost &&
367 "Should be pre or offset index op");
368
399369 printAM2PreOrOffsetIndexOp(MI, Op, O);
400370 }
401371
921891
922892 // Print the shift opc.
923893 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
924 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
925 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
926 if (ShOpc != ARM_AM::rrx)
927 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
894 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
895 ARM_AM::getSORegOffset(MO2.getImm()));
928896 }
929897
930898 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
7373 @ CHECK: ldr r3, [r4], r5 @ encoding: [0x05,0x30,0x94,0xe6]
7474 @ CHECK: str r6, [r7], r8 @ encoding: [0x08,0x60,0x87,0xe6]
7575 @ CHECK: str r9, [r10], r11 @ encoding: [0x0b,0x90,0x8a,0xe6]
76
77 @ Uses printSORegImmOperand(), used by ADCrsi ADDrsi ANDrsi BICrsi EORrsi
78 @ ORRrsi RSBrsi RSCrsi SBCrsi SUBrsi CMNzrsi CMPrsi MOVsi MVNsi TEQrsi TSTrsi
79
80 adc sp, lr, pc
81 adc r1, r8, r9, lsr #32
82 adc r2, r7, pc, lsr #16
83 adc r3, r6, r10, lsl #0
84 adc r4, r5, lr, lsl #16
85 adc r5, r4, r11, asr #32
86 adc r6, r3, sp, asr #16
87 adc r7, r2, r12, rrx
88 adc r8, r1, r0, ror #16
89
90 @ CHECK: adc sp, lr, pc @ encoding: [0x0f,0xd0,0xae,0xe0]
91 @ CHECK: adc r1, r8, r9, lsr #32 @ encoding: [0x29,0x10,0xa8,0xe0]
92 @ CHECK: adc r2, r7, pc, lsr #16 @ encoding: [0x2f,0x28,0xa7,0xe0]
93 @ CHECK: adc r3, r6, r10 @ encoding: [0x0a,0x30,0xa6,0xe0]
94 @ CHECK: adc r4, r5, lr, lsl #16 @ encoding: [0x0e,0x48,0xa5,0xe0]
95 @ CHECK: adc r5, r4, r11, asr #32 @ encoding: [0x4b,0x50,0xa4,0xe0]
96 @ CHECK: adc r6, r3, sp, asr #16 @ encoding: [0x4d,0x68,0xa3,0xe0]
97 @ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0]
98 @ CHECK: adc r8, r1, r0, ror #16 @ encoding: [0x60,0x88,0xa1,0xe0]
99
100 cmp sp, lr
101 cmp r1, r8, lsr #32
102 cmp r2, r7, lsr #16
103 cmp r3, r6, lsl #0
104 cmp r4, r5, lsl #16
105 cmp r5, r4, asr #32
106 cmp r6, r3, asr #16
107 cmp r7, r2, rrx
108 cmp r8, r1, ror #16
109
110 @ CHECK: cmp sp, lr @ encoding: [0x0e,0x00,0x5d,0xe1]
111 @ CHECK: cmp r1, r8, lsr #32 @ encoding: [0x28,0x00,0x51,0xe1]
112 @ CHECK: cmp r2, r7, lsr #16 @ encoding: [0x27,0x08,0x52,0xe1]
113 @ CHECK: cmp r3, r6 @ encoding: [0x06,0x00,0x53,0xe1]
114 @ CHECK: cmp r4, r5, lsl #16 @ encoding: [0x05,0x08,0x54,0xe1]
115 @ CHECK: cmp r5, r4, asr #32 @ encoding: [0x44,0x00,0x55,0xe1]
116 @ CHECK: cmp r6, r3, asr #16 @ encoding: [0x43,0x08,0x56,0xe1]
117 @ CHECK: cmp r7, r2, rrx @ encoding: [0x62,0x00,0x57,0xe1]
118 @ CHECK: cmp r8, r1, ror #16 @ encoding: [0x61,0x08,0x58,0xe1]
0 @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7 -show-encoding < %s | FileCheck %s
1
2 @ Uses printT2SOOperand(), used by t2ADCrs t2ADDrs t2ANDrs t2BICrs t2EORrs
3 @ t2ORNrs t2ORRrs t2RSBrs t2SBCrs t2SUBrs t2CMNzrs t2CMPrs t2MOVSsi t2MOVsi
4 @ t2MVNs t2TEQrs t2TSTrs
5
6 sbc.w r12, lr, r0
7 sbc.w r1, r8, r9, lsr #32
8 sbc.w r2, r7, pc, lsr #16
9 sbc.w r3, r6, r10, lsl #0
10 sbc.w r4, r5, lr, lsl #16
11 sbc.w r5, r4, r11, asr #32
12 sbc.w r6, r3, sp, asr #16
13 sbc.w r7, r2, r12, rrx
14 sbc.w r8, r1, r0, ror #16
15
16 @ CHECK: sbc.w r12, lr, r0 @ encoding: [0x6e,0xeb,0x00,0x0c]
17 @ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
18 @ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42]
19 @ CHECK: sbc.w r3, r6, r10 @ encoding: [0x66,0xeb,0x0a,0x03]
20 @ CHECK: sbc.w r4, r5, lr, lsl #16 @ encoding: [0x65,0xeb,0x0e,0x44]
21 @ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05]
22 @ CHECK: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
23 @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
24 @ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48]
25
26 and.w r12, lr, r0
27 and.w r1, r8, r9, lsr #32
28 and.w r2, r7, pc, lsr #16
29 and.w r3, r6, r10, lsl #0
30 and.w r4, r5, lr, lsl #16
31 and.w r5, r4, r11, asr #32
32 and.w r6, r3, sp, asr #16
33 and.w r7, r2, r12, rrx
34 and.w r8, r1, r0, ror #16
35
36 @ CHECK: and.w r12, lr, r0 @ encoding: [0x0e,0xea,0x00,0x0c]
37 @ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
38 @ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42]
39 @ CHECK: and.w r3, r6, r10 @ encoding: [0x06,0xea,0x0a,0x03]
40 @ CHECK: and.w r4, r5, lr, lsl #16 @ encoding: [0x05,0xea,0x0e,0x44]
41 @ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05]
42 @ CHECK: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
43 @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
44 @ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48]