llvm.org GIT mirror llvm / bb32f1d
ARM: Tweak tADDrSP definition for consistent operand order. Make the operand order of the instruction match that of the asm syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
2 changed file(s) with 3 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
362362 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
363363
364364 // ADD , sp
365 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
366 "add", "\t$Rdn, $sp, $Rn", []>,
365 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
366 "add", "\t$Rdn, $sp, $Rn", []>,
367367 T1Special<{0,0,?,?}> {
368368 // A8.6.9 Encoding T1
369369 bits<4> Rdn;
32953295
32963296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
32973297 return MCDisassembler::Fail;
3298 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
32983299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
32993300 return MCDisassembler::Fail;
3300 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
33013301 } else if (Inst.getOpcode() == ARM::tADDspr) {
33023302 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
33033303