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Approved by Evan: $ svn merge -c 113297 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113297 into '.': U lib/Target/ARM/Thumb2SizeReduction.cpp $ svn merge -c 113322 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113322 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMInstrVFP.td U lib/Target/ARM/ARMInstrFormats.td $ svn merge -c 113365 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113365 into '.': U lib/Target/ARM/ARMBaseRegisterInfo.cpp $ svn merge -c 113366 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113366 into '.': G lib/Target/ARM/ARMBaseRegisterInfo.cpp $ svn merge -c 113394 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113394 into '.': G lib/Target/ARM/ARMBaseRegisterInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@113540 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 10 years ago
5 changed file(s) with 42 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
666666 }
667667
668668 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
669 const MachineFrameInfo *MFI = MF.getFrameInfo();
669670 const ARMFunctionInfo *AFI = MF.getInfo();
670 return (RealignStack && !AFI->isThumb1OnlyFunction());
671 // We can't realign the stack if:
672 // 1. Dynamic stack realignment is explicitly disabled,
673 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
674 // 3. There are VLAs in the function and the base pointer is disabled.
675 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
676 (!MFI->hasVarSizedObjects() || EnableBasePointer));
671677 }
672678
673679 bool ARMBaseRegisterInfo::
10561062 if (isFixed) {
10571063 FrameReg = getFrameRegister(MF);
10581064 Offset = FPOffset;
1059 } else if (MFI->hasVarSizedObjects())
1065 } else if (MFI->hasVarSizedObjects()) {
1066 assert(hasBasePointer(MF) &&
1067 "VLAs and dynamic stack alignment, but missing base pointer!");
10601068 FrameReg = BasePtr;
1069 }
10611070 return Offset;
10621071 }
10631072
10671076 // there are VLAs (and thus the SP isn't reliable as a base).
10681077 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
10691078 FrameReg = getFrameRegister(MF);
1070 Offset = FPOffset;
1079 return FPOffset;
10711080 } else if (MFI->hasVarSizedObjects()) {
10721081 assert(hasBasePointer(MF) && "missing base pointer!");
10731082 // Use the base register since we have it.
10771086 // out of range references.
10781087 if (FPOffset >= -255 && FPOffset < 0) {
10791088 FrameReg = getFrameRegister(MF);
1080 Offset = FPOffset;
1089 return FPOffset;
10811090 }
10821091 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
10831092 // Otherwise, use SP or FP, whichever is closer to the stack slot.
10841093 FrameReg = getFrameRegister(MF);
1085 Offset = FPOffset;
1094 return FPOffset;
10861095 }
10871096 }
10881097 // Use the base pointer if we have one.
18861895 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
18871896 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
18881897
1889 // If we need dynamic stack realignment, do it here.
1898 // If we need dynamic stack realignment, do it here. Be paranoid and make
1899 // sure if we also have VLAs, we have a base pointer for frame access.
18901900 if (needsStackRealignment(MF)) {
18911901 unsigned MaxAlign = MFI->getMaxAlignment();
18921902 assert (!AFI->isThumb1OnlyFunction());
13311331 }
13321332
13331333 // Load / store multiple
1334 class AXDI5
1334 class AXDI4
13351335 string asm, string cstr, list pattern>
1336 : VFPXI5, Size4Bytes, im,
1336 : VFPXI4, Size4Bytes, im,
13371337 VFPLdStMulFrm, itin, asm, cstr, pattern> {
13381338 // TODO: Mark the instructions with the appropriate subtarget info.
13391339 let Inst{27-25} = 0b110;
13431343 let D = VFPNeonDomain;
13441344 }
13451345
1346 class AXSI5
1346 class AXSI4
13471347 string asm, string cstr, list pattern>
1348 : VFPXI5, Size4Bytes, im,
1348 : VFPXI4, Size4Bytes, im,
13491349 VFPLdStMulFrm, itin, asm, cstr, pattern> {
13501350 // TODO: Mark the instructions with the appropriate subtarget info.
13511351 let Inst{27-25} = 0b110;
132132 // This is equivalent to VLDMD except that it has a Q register operand
133133 // instead of a pair of D registers.
134134 def VLDMQ
135 : AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
135 : AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
136136 IndexModeNone, IIC_fpLoadm,
137137 "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
138138 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
150150 // This is equivalent to VSTMD except that it has a Q register operand
151151 // instead of a pair of D registers.
152152 def VSTMQ
153 : AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
153 : AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
154154 IndexModeNone, IIC_fpStorem,
155155 "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
156156 [(store (v2f64 QPR:$src), addrmode4:$addr)]>;
7676 //
7777
7878 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
79 def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
79 def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
8080 variable_ops), IndexModeNone, IIC_fpLoadm,
8181 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
8282 let Inst{20} = 1;
8383 }
8484
85 def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
85 def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
8686 variable_ops), IndexModeNone, IIC_fpLoadm,
8787 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
8888 let Inst{20} = 1;
8989 }
9090
91 def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
91 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
9292 reglist:$dsts, variable_ops),
9393 IndexModeUpd, IIC_fpLoadm,
9494 "vldm${addr:submode}${p}\t$addr!, $dsts",
9696 let Inst{20} = 1;
9797 }
9898
99 def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
99 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
100100 reglist:$dsts, variable_ops),
101101 IndexModeUpd, IIC_fpLoadm,
102102 "vldm${addr:submode}${p}\t$addr!, $dsts",
106106 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
107107
108108 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
109 def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
109 def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
110110 variable_ops), IndexModeNone, IIC_fpStorem,
111111 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
112112 let Inst{20} = 0;
113113 }
114114
115 def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
115 def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
116116 variable_ops), IndexModeNone, IIC_fpStorem,
117117 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
118118 let Inst{20} = 0;
119119 }
120120
121 def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
121 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
122122 reglist:$srcs, variable_ops),
123123 IndexModeUpd, IIC_fpStorem,
124124 "vstm${addr:submode}${p}\t$addr!, $srcs",
126126 let Inst{20} = 0;
127127 }
128128
129 def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
129 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
130130 reglist:$srcs, variable_ops),
131131 IndexModeUpd, IIC_fpStorem,
132132 "vstm${addr:submode}${p}\t$addr!, $srcs",
314314 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
315315 if (!isARMLowRegister(BaseReg) || Mode != ARM_AM::ia)
316316 return false;
317 // For the non-writeback version (this one), the base register must be
318 // one of the registers being loaded.
319 bool isOK = false;
320 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
321 if (MI->getOperand(i).getReg() == BaseReg) {
322 isOK = true;
323 break;
324 }
325 }
326 if (!isOK)
327 return false;
328
317329 OpNum = 0;
318330 isLdStMul = true;
319331 break;