llvm.org GIT mirror llvm / bab812b
Revert r78852 for now. I want to do this differently, but I don't have time to fix it tonight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78896 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
3 changed file(s) with 23 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
486486 case ARMISD::VREV64: return "ARMISD::VREV64";
487487 case ARMISD::VREV32: return "ARMISD::VREV32";
488488 case ARMISD::VREV16: return "ARMISD::VREV16";
489 case ARMISD::VSPLAT0: return "ARMISD::VSPLAT0";
490489 }
491490 }
492491
24422441 // DAG nodes, instead of keeping them as shuffles and matching them again
24432442 // during code selection. This is more efficient and avoids the possibility
24442443 // of inconsistencies between legalization and selection.
2445 if (SVN->isSplat() && SVN->getSplatIndex() == 0)
2446 return DAG.getNode(ARMISD::VSPLAT0, dl, VT, SVN->getOperand(0));
24472444 if (isVREVMask(SVN, 64))
24482445 return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
24492446 if (isVREVMask(SVN, 32))
128128 // Vector shuffles:
129129 VREV64, // reverse elements within 64-bit doublewords
130130 VREV32, // reverse elements within 32-bit words
131 VREV16, // reverse elements within 16-bit halfwords
132 VSPLAT0 // duplicate element 0 into all elements
131 VREV16 // reverse elements within 16-bit halfwords
133132 };
134133 }
135134
9898 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
9999 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
100100 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
101 def NEONvsplat0 : SDNode<"ARMISD::VSPLAT0", SDTARMVSHUF>;
102101
103102 //===----------------------------------------------------------------------===//
104103 // NEON operand definitions
17441743
17451744 // VDUP : Vector Duplicate (from ARM core register to all elements)
17461745
1746 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1747 (vector_shuffle node:$lhs, node:$rhs), [{
1748 ShuffleVectorSDNode *SVOp = cast(N);
1749 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1750 }]>;
1751
17471752 class VDUPD opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
17481753 : NVDup
17491754 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1750 [(set DPR:$dst, (Ty (NEONvsplat0 (scalar_to_vector GPR:$src))))]>;
1755 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
17511756 class VDUPQ opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
17521757 : NVDup
17531758 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1754 [(set QPR:$dst, (Ty (NEONvsplat0 (scalar_to_vector GPR:$src))))]>;
1759 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
17551760
17561761 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
17571762 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
17621767
17631768 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
17641769 NoItinerary, "vdup", ".32\t$dst, $src",
1765 [(set DPR:$dst,
1766 (v2f32 (NEONvsplat0 (scalar_to_vector
1767 (f32 (bitconvert GPR:$src))))))]>;
1770 [(set DPR:$dst, (v2f32 (splat_lo
1771 (scalar_to_vector
1772 (f32 (bitconvert GPR:$src))),
1773 undef)))]>;
17681774 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
17691775 NoItinerary, "vdup", ".32\t$dst, $src",
1770 [(set QPR:$dst,
1771 (v4f32 (NEONvsplat0 (scalar_to_vector
1772 (f32 (bitconvert GPR:$src))))))]>;
1776 [(set QPR:$dst, (v4f32 (splat_lo
1777 (scalar_to_vector
1778 (f32 (bitconvert GPR:$src))),
1779 undef)))]>;
17731780
17741781 // VDUP : Vector Duplicate Lane (from scalar to all elements)
17751782
18111818 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
18121819 (outs DPR:$dst), (ins SPR:$src),
18131820 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1814 [(set DPR:$dst, (v2f32 (NEONvsplat0
1815 (scalar_to_vector SPR:$src))))]>;
1821 [(set DPR:$dst, (v2f32 (splat_lo
1822 (scalar_to_vector SPR:$src),
1823 undef)))]>;
18161824
18171825 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
18181826 (outs QPR:$dst), (ins SPR:$src),
18191827 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1820 [(set QPR:$dst, (v4f32 (NEONvsplat0
1821 (scalar_to_vector SPR:$src))))]>;
1828 [(set QPR:$dst, (v4f32 (splat_lo
1829 (scalar_to_vector SPR:$src),
1830 undef)))]>;
18221831
18231832 // VMOVN : Vector Narrowing Move
18241833 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",