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Merging r142550: ------------------------------------------------------------------------ r142550 | evancheng | 2011-10-19 15:22:54 -0700 (Wed, 19 Oct 2011) | 1 line Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142555 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
2 changed file(s) with 19 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
75257525 // And our return value (tls address) is in the standard call return value
75267526 // location.
75277527 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7528 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7528 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7529 Chain.getValue(1));
75297530 }
75307531
75317532 assert(false &&
44 @c = external thread_local global %struct.A, align 4
55
66 define void @main() nounwind ssp {
7 ; CHECK: main:
78 entry:
89 call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
910 unreachable
1112 ; CHECK-NEXT: callq *(%rdi)
1213 ; CHECK-NEXT: movl $0, 56(%rax)
1314 ; CHECK-NEXT: movq $0, 48(%rax)
15 }
16
17 ; rdar://10291355
18 define i32 @test() nounwind readonly ssp {
19 entry:
20 ; CHECK: test:
21 ; CHECK: movq _a@TLVP(%rip),
22 ; CHECK: callq *
23 ; CHECK: movl (%rax), [[REGISTER:%[a-z]+]]
24 ; CHECK: movq _b@TLVP(%rip),
25 ; CHECK: callq *
26 ; CHECK: subl (%rax), [[REGISTER]]
27 %0 = load i32* @a, align 4
28 %1 = load i32* @b, align 4
29 %sub = sub nsw i32 %0, %1
30 ret i32 %sub
1431 }
1532
1633 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind