llvm.org GIT mirror llvm / bab2474
Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40521 91177308-0d34-0410-b5e6-96231b3b80d8 Christopher Lamb 12 years ago
3 changed file(s) with 236 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
8787 /// and eliminates abstract frame references.
8888 ///
8989 FunctionPass *createPrologEpilogCodeInserter();
90
91 /// LowerSubregs Pass - This pass lowers subregs to register-register copies
92 /// which yields suboptimial, but correct code if the register allocator
93 /// cannot coalesce all subreg operations during allocation.
94 ///
95 FunctionPass *createLowerSubregsPass();
9096
9197 /// createPostRAScheduler - under development.
9298 FunctionPass *createPostRAScheduler();
9595
9696 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
9797 PM.add(createMachineFunctionPrinterPass(cerr));
98
99 PM.add(createLowerSubregsPass());
98100
99101 switch (FileType) {
100102 default:
196198
197199 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
198200 PM.add(createMachineFunctionPrinterPass(cerr));
201
202 PM.add(createLowerSubregsPass());
199203
200204 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
201205
0 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Christopher Lamb and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #define DEBUG_TYPE "lowersubregs"
10 #include "llvm/CodeGen/Passes.h"
11 #include "llvm/Function.h"
12 #include "llvm/CodeGen/MachineFunctionPass.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/SSARegMap.h"
15 #include "llvm/Target/MRegisterInfo.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/Compiler.h"
20 using namespace llvm;
21
22 namespace {
23 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
24 : public MachineFunctionPass {
25 static char ID; // Pass identification, replacement for typeid
26 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
27
28 const char *getPassName() const {
29 return "Subregister lowering instruction pass";
30 }
31
32 /// runOnMachineFunction - pass entry point
33 bool runOnMachineFunction(MachineFunction&);
34 };
35
36 char LowerSubregsInstructionPass::ID = 0;
37 }
38
39 FunctionPass *llvm::createLowerSubregsPass() {
40 return new LowerSubregsInstructionPass();
41 }
42
43 // Returns the Register Class of a physical register
44 static const TargetRegisterClass *getPhysicalRegisterRegClass(
45 const MRegisterInfo &MRI,
46 unsigned reg) {
47 assert(MRegisterInfo::isPhysicalRegister(reg) &&
48 "reg must be a physical register");
49 // Pick the register class of the right type that contains this physreg.
50 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
51 E = MRI.regclass_end(); I != E; ++I)
52 if ((*I)->contains(reg))
53 return *I;
54 assert(false && "Couldn't find the register class");
55 return 0;
56 }
57
58 static bool isSubRegOf(const MRegisterInfo &MRI,
59 unsigned SubReg,
60 unsigned SupReg) {
61 const TargetRegisterDesc &RD = MRI[SubReg];
62 for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
63 if (*reg == SupReg)
64 return true;
65
66 return false;
67 }
68
69
70 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
71 /// copies.
72 ///
73 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
74 DOUT << "Machine Function\n";
75 const TargetMachine &TM = MF.getTarget();
76 const MRegisterInfo &MRI = *TM.getRegisterInfo();
77
78 bool MadeChange = false;
79
80 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
81 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
82
83 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
84 mbbi != mbbe; ++mbbi) {
85 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
86 mi != me; ++mi) {
87
88 if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
89 assert(mi->getOperand(0).isRegister() && mi->getOperand(0).isDef() &&
90 mi->getOperand(1).isRegister() && mi->getOperand(1).isUse() &&
91 mi->getOperand(2).isImm() && "Malformed extract_subreg");
92
93 unsigned SuperReg = mi->getOperand(1).getReg();
94 unsigned SubIdx = mi->getOperand(2).getImm();
95
96 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
97 "Extract supperg source must be a physical register");
98 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
99 unsigned DstReg = mi->getOperand(0).getReg();
100
101 DOUT << "subreg: CONVERTING: " << *mi;
102
103 if (SrcReg != DstReg) {
104 const TargetRegisterClass *TRC = 0;
105 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
106 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
107 } else {
108 TRC = MF.getSSARegMap()->getRegClass(DstReg);
109 }
110 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
111 "Extract subreg and Dst must be of same register class");
112
113 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC);
114 MachineBasicBlock::iterator dmi = mi;
115 DOUT << "subreg: " << *(--dmi);
116 }
117
118 DOUT << "\n";
119 mbbi->erase(mi);
120 MadeChange = true;
121
122 } else if (mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
123
124 unsigned DstReg = 0;
125 unsigned SrcReg = 0;
126 unsigned InsReg = 0;
127 unsigned SubIdx = 0;
128
129 // If only have 3 operands, then the source superreg is undef
130 // and we can supress the copy from the undef value
131 if (mi->getNumOperands() == 3) {
132 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
133 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
134 mi->getOperand(2).isImm() && "Invalid extract_subreg");
135 DstReg = mi->getOperand(0).getReg();
136 SrcReg = DstReg;
137 InsReg = mi->getOperand(1).getReg();
138 SubIdx = mi->getOperand(2).getImm();
139 } else if (mi->getNumOperands() == 4) {
140 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
141 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
142 (mi->getOperand(2).isRegister() && mi->getOperand(2).isUse()) &&
143 mi->getOperand(3).isImm() && "Invalid extract_subreg");
144 DstReg = mi->getOperand(0).getReg();
145 SrcReg = mi->getOperand(1).getReg();
146 InsReg = mi->getOperand(2).getReg();
147 SubIdx = mi->getOperand(3).getImm();
148 } else
149 assert(0 && "Malformed extract_subreg");
150
151 assert(SubIdx != 0 && "Invalid index for extract_subreg");
152 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
153
154 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
155 "Insert superreg source must be in a physical register");
156 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
157 "Insert destination must be in a physical register");
158 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
159 "Inserted value must be in a physical register");
160
161 DOUT << "subreg: CONVERTING: " << *mi;
162
163 // If the inserted register is already allocated into a subregister
164 // of the destination, we copy the subreg into the source
165 // However, this is only safe if the insert instruction is the kill
166 // of the source register
167 bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
168 if (revCopyOrder) {
169 if (mi->getOperand(1).isKill()) {
170 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
171 // Insert sub-register copy
172 const TargetRegisterClass *TRC1 = 0;
173 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
174 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
175 } else {
176 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
177 }
178
179 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
180 MachineBasicBlock::iterator dmi = mi;
181 DOUT << "subreg: " << *(--dmi);
182 } else {
183 assert(0 && "Don't know how to convert this insert");
184 }
185 }
186
187 if (SrcReg != DstReg) {
188 // Insert super-register copy
189 const TargetRegisterClass *TRC0 = 0;
190 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
191 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
192 } else {
193 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
194 }
195 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
196 "Insert superreg and Dst must be of same register class");
197
198 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC0);
199 MachineBasicBlock::iterator dmi = mi;
200 DOUT << "subreg: " << *(--dmi);
201 }
202
203 if (!revCopyOrder && InsReg != DstSubReg) {
204 // Insert sub-register copy
205 const TargetRegisterClass *TRC1 = 0;
206 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
207 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
208 } else {
209 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
210 }
211
212 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
213 MachineBasicBlock::iterator dmi = mi;
214 DOUT << "subreg: " << *(--dmi);
215 }
216
217 DOUT << "\n";
218 mbbi->erase(mi);
219 MadeChange = true;
220 }
221 }
222 }
223
224 return MadeChange;
225 }