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TableGen'ing instruction encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
1 changed file(s) with 2 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
1414 BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
1515 ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
1616 ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
17 ARMGenDAGISel.inc ARMGenSubtarget.inc
17 ARMGenDAGISel.inc ARMGenSubtarget.inc \
18 ARMGenCodeEmitter.inc
1819
1920 DIRS = AsmPrinter
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