llvm.org GIT mirror llvm / ba61446
AArch64/ARM64: enable various AArch64 tests on ARM64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206877 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 5 years ago
13 changed file(s) with 34 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
44 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
55 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
66
7 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
8 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
9 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
10 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
11
712 ; CHECK-NOT: {{.*}} is not a recognized processor for this target
813 ; INVALID: {{.*}} is not a recognized processor for this target
914
0 ; REQUIRES: asserts
11 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
2 ; arm64 now has a separate copy of this test.
23 ;
34 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
45 ; much higher than the ADD instructions in order to hide latency. When not
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; arm64 has tests for i64 versions, uses different approach for others.
12
23 define i64 @test_vabsd_s64(i64 %a) {
34 ; CHECK: test_vabsd_s64
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; arm64 has a copy of the key parts in AdvSIMD-Scalar.ll
12
23 define <1 x i64> @add1xi64(<1 x i64> %A, <1 x i64> %B) {
34 ;CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
12
23 declare float @llvm.fma.f32(float, float, float)
34 declare double @llvm.fma.f64(double, double, double)
45
56 define float @test_fmla_ss4S(float %a, float %b, <4 x float> %v) {
6 ; CHECK: test_fmla_ss4S
7 ; CHECK-LABEL: test_fmla_ss4S
78 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
89 %tmp1 = extractelement <4 x float> %v, i32 3
910 %tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
1112 }
1213
1314 define float @test_fmla_ss4S_swap(float %a, float %b, <4 x float> %v) {
14 ; CHECK: test_fmla_ss4S_swap
15 ; CHECK-LABEL: test_fmla_ss4S_swap
1516 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
1617 %tmp1 = extractelement <4 x float> %v, i32 3
1718 %tmp2 = call float @llvm.fma.f32(float %tmp1, float %a, float %a)
1920 }
2021
2122 define float @test_fmla_ss2S(float %a, float %b, <2 x float> %v) {
22 ; CHECK: test_fmla_ss2S
23 ; CHECK-LABEL: test_fmla_ss2S
2324 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
2425 %tmp1 = extractelement <2 x float> %v, i32 1
2526 %tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
2728 }
2829
2930 define double @test_fmla_ddD(double %a, double %b, <1 x double> %v) {
30 ; CHECK: test_fmla_ddD
31 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
31 ; CHECK-LABEL: test_fmla_ddD
32 ; CHECK: {{fmla d[0-9]+, d[0-9]+, v[0-9]+.d\[0]|fmadd d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}}
3233 %tmp1 = extractelement <1 x double> %v, i32 0
3334 %tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
3435 ret double %tmp2
3536 }
3637
3738 define double @test_fmla_dd2D(double %a, double %b, <2 x double> %v) {
38 ; CHECK: test_fmla_dd2D
39 ; CHECK-LABEL: test_fmla_dd2D
3940 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
4041 %tmp1 = extractelement <2 x double> %v, i32 1
4142 %tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
4344 }
4445
4546 define double @test_fmla_dd2D_swap(double %a, double %b, <2 x double> %v) {
46 ; CHECK: test_fmla_dd2D_swap
47 ; CHECK-LABEL: test_fmla_dd2D_swap
4748 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
4849 %tmp1 = extractelement <2 x double> %v, i32 1
4950 %tmp2 = call double @llvm.fma.f64(double %tmp1, double %b, double %a)
5152 }
5253
5354 define float @test_fmls_ss4S(float %a, float %b, <4 x float> %v) {
54 ; CHECK: test_fmls_ss4S
55 ; CHECK-LABEL: test_fmls_ss4S
5556 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
5657 %tmp1 = extractelement <4 x float> %v, i32 3
5758 %tmp2 = fsub float -0.0, %tmp1
6061 }
6162
6263 define float @test_fmls_ss4S_swap(float %a, float %b, <4 x float> %v) {
63 ; CHECK: test_fmls_ss4S_swap
64 ; CHECK-LABEL: test_fmls_ss4S_swap
6465 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
6566 %tmp1 = extractelement <4 x float> %v, i32 3
6667 %tmp2 = fsub float -0.0, %tmp1
7071
7172
7273 define float @test_fmls_ss2S(float %a, float %b, <2 x float> %v) {
73 ; CHECK: test_fmls_ss2S
74 ; CHECK-LABEL: test_fmls_ss2S
7475 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
7576 %tmp1 = extractelement <2 x float> %v, i32 1
7677 %tmp2 = fsub float -0.0, %tmp1
7980 }
8081
8182 define double @test_fmls_ddD(double %a, double %b, <1 x double> %v) {
82 ; CHECK: test_fmls_ddD
83 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
83 ; CHECK-LABEL: test_fmls_ddD
84 ; CHECK: {{fmls d[0-9]+, d[0-9]+, v[0-9]+.d\[0]|fmsub d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}}
8485 %tmp1 = extractelement <1 x double> %v, i32 0
8586 %tmp2 = fsub double -0.0, %tmp1
8687 %tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
8889 }
8990
9091 define double @test_fmls_dd2D(double %a, double %b, <2 x double> %v) {
91 ; CHECK: test_fmls_dd2D
92 ; CHECK-LABEL: test_fmls_dd2D
9293 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
9394 %tmp1 = extractelement <2 x double> %v, i32 1
9495 %tmp2 = fsub double -0.0, %tmp1
9798 }
9899
99100 define double @test_fmls_dd2D_swap(double %a, double %b, <2 x double> %v) {
100 ; CHECK: test_fmls_dd2D_swap
101 ; CHECK-LABEL: test_fmls_dd2D_swap
101102 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
102103 %tmp1 = extractelement <2 x double> %v, i32 1
103104 %tmp2 = fsub double -0.0, %tmp1
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
1 ; arm64 has (the non-trivial parts of) this test covered by vcmp.ll
12
23 ;; Scalar Integer Compare
34
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
1 ; arm64 has a different approach to scalars. Discarding.
12
23 define float @test_vcvts_f32_s32(i32 %a) {
34 ; CHECK: test_vcvts_f32_s32
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
1 ; arm64 doesn't use <1 x iN> types, for N < 64.
12
23 define <1 x i64> @test_zext_v1i32_v1i64(<2 x i32> %v) nounwind readnone {
34 ; CHECK-LABEL: test_zext_v1i32_v1i64:
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; arm64 has separate copy of parts that aren't pure intrinsic wrangling.
12
23 define <8 x i8> @test_vshr_n_s8(<8 x i8> %a) {
34 ; CHECK: test_vshr_n_s8
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; This test is just intrinsic pumping. arm64 has its own tbl/tbx tests.
12
23 declare <16 x i8> @llvm.aarch64.neon.vtbx4.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
34
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; arm64 has its own copy: aarch64-neon-simd-vget.ll
12
23 define <8 x i8> @test_vget_high_s8(<16 x i8> %a) {
34 ; CHECK-LABEL: test_vget_high_s8:
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
12
23 ; A vector TruncStore can not be selected.
34 ; Test a trunc IR and a vector store IR can be selected correctly.
45 define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
56 ; CHECK-LABEL: truncStore.v2i64:
67 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
7 ; CHECK: st1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}]
8 ; CHECK: {{st1 {v[0-9]+.2s}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
89 %b = trunc <2 x i64> %a to <2 x i32>
910 store <2 x i32> %b, <2 x i32>* %result
1011 ret void
1314 define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
1415 ; CHECK-LABEL: truncStore.v4i32:
1516 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
16 ; CHECK: st1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}]
17 ; CHECK: {{st1 {v[0-9]+.4h}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
1718 %b = trunc <4 x i32> %a to <4 x i16>
1819 store <4 x i16> %b, <4 x i16>* %result
1920 ret void
2223 define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
2324 ; CHECK-LABEL: truncStore.v8i16:
2425 ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
25 ; CHECK: st1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}]
26 ; CHECK: {{st1 {v[0-9]+.8b}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
2627 %b = trunc <8 x i16> %a to <8 x i8>
2728 store <8 x i8> %b, <8 x i8>* %result
2829 ret void
0 ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
1 ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 < %s | FileCheck --check-prefix=CHECK-NOFP %s
1 ; arm64 has its own copy of this file, ported during implementation (variadic-aapcs.ll)
22
33 %va_list = type {i8*, i8*, i8*, i32, i32}
44