llvm.org GIT mirror llvm / ba2fa17
Canonicalize a large number of mir tests using update_mir_test_checks This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316137 91177308-0d34-0410-b5e6-96231b3b80d8 Justin Bogner 2 years ago
52 changed file(s) with 2065 addition(s) and 2201 deletion(s). Raw diff Collapse all Expand all
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
3132 body: |
3233 bb.0.entry:
3334 liveins: %x0, %x1, %x2, %x3
35
3436 ; CHECK-LABEL: name: test_scalar_add_big
35 ; CHECK-NOT: G_MERGE_VALUES
36 ; CHECK-NOT: G_UNMERGE_VALUES
37 ; CHECK-DAG: [[CARRY0_32:%.*]](s32) = G_CONSTANT i32 0
38 ; CHECK-DAG: [[CARRY0:%[0-9]+]](s1) = G_TRUNC [[CARRY0_32]]
39 ; CHECK: [[RES_LO:%.*]](s64), [[CARRY:%.*]](s1) = G_UADDE %0, %2, [[CARRY0]]
40 ; CHECK: [[RES_HI:%.*]](s64), {{%.*}}(s1) = G_UADDE %1, %3, [[CARRY]]
41 ; CHECK-NOT: G_MERGE_VALUES
42 ; CHECK-NOT: G_UNMERGE_VALUES
43 ; CHECK: %x0 = COPY [[RES_LO]]
44 ; CHECK: %x1 = COPY [[RES_HI]]
45
37 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
38 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
39 ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY %x2
40 ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY %x3
41 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
42 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
43 ; CHECK: [[UADDE:%[0-9]+]](s64), [[UADDE1:%[0-9]+]](s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
44 ; CHECK: [[UADDE2:%[0-9]+]](s64), [[UADDE3:%[0-9]+]](s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
45 ; CHECK: %x0 = COPY [[UADDE]](s64)
46 ; CHECK: %x1 = COPY [[UADDE2]](s64)
4647 %0(s64) = COPY %x0
4748 %1(s64) = COPY %x1
4849 %2(s64) = COPY %x2
6768 body: |
6869 bb.0.entry:
6970 liveins: %x0, %x1, %x2, %x3
71
7072 ; CHECK-LABEL: name: test_scalar_add_small
71 ; CHECK: [[A:%.*]](s64) = COPY %x0
72 ; CHECK: [[B:%.*]](s64) = COPY %x1
73 ; CHECK: [[OP0:%.*]](s32) = G_TRUNC [[A]]
74 ; CHECK: [[OP1:%.*]](s32) = G_TRUNC [[B]]
75 ; CHECK: [[RES32:%.*]](s32) = G_ADD [[OP0]], [[OP1]]
76 ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
77
73 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
74 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
75 ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
76 ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
77 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[TRUNC]], [[TRUNC1]]
78 ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[ADD]](s32)
79 ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
80 ; CHECK: %x0 = COPY [[ANYEXT]](s64)
7881 %0(s64) = COPY %x0
7982 %1(s64) = COPY %x1
8083 %2(s8) = G_TRUNC %0
99102 body: |
100103 bb.0.entry:
101104 liveins: %q0, %q1, %q2, %q3
105
102106 ; CHECK-LABEL: name: test_vector_add
103 ; CHECK-NOT: G_EXTRACT
104 ; CHECK-NOT: G_SEQUENCE
105 ; CHECK: [[RES_LO:%.*]](<2 x s64>) = G_ADD %0, %2
106 ; CHECK: [[RES_HI:%.*]](<2 x s64>) = G_ADD %1, %3
107 ; CHECK-NOT: G_EXTRACT
108 ; CHECK-NOT: G_SEQUENCE
109 ; CHECK: %q0 = COPY [[RES_LO]]
110 ; CHECK: %q1 = COPY [[RES_HI]]
111
107 ; CHECK: [[COPY:%[0-9]+]](<2 x s64>) = COPY %q0
108 ; CHECK: [[COPY1:%[0-9]+]](<2 x s64>) = COPY %q1
109 ; CHECK: [[COPY2:%[0-9]+]](<2 x s64>) = COPY %q2
110 ; CHECK: [[COPY3:%[0-9]+]](<2 x s64>) = COPY %q3
111 ; CHECK: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
112 ; CHECK: [[ADD1:%[0-9]+]](<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
113 ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
114 ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
112115 %0(<2 x s64>) = COPY %q0
113116 %1(<2 x s64>) = COPY %q1
114117 %2(<2 x s64>) = COPY %q2
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2021 body: |
2122 bb.0.entry:
2223 liveins: %x0, %x1, %x2, %x3
24
2325 ; CHECK-LABEL: name: test_scalar_and_small
24 ; CHECK: [[A:%.*]](s64) = COPY %x0
25 ; CHECK: [[B:%.*]](s64) = COPY %x1
26 ; CHECK: [[OP0:%.*]](s32) = G_TRUNC [[A]]
27 ; CHECK: [[OP1:%.*]](s32) = G_TRUNC [[B]]
28 ; CHECK: [[RES32:%.*]](s32) = G_AND [[OP0]], [[OP1]]
29 ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
30
26 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
27 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
28 ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s64)
29 ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
30 ; CHECK: [[TRUNC2:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
31 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[TRUNC1]], [[TRUNC2]]
32 ; CHECK: [[TRUNC3:%[0-9]+]](s8) = G_TRUNC [[AND]](s32)
33 ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s8)
34 ; CHECK: %x0 = COPY [[ANYEXT]](s64)
3135 %0(s64) = COPY %x0
3236 %1(s64) = COPY %x1
3337 %2(s8) = G_TRUNC %0
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1516 bb.0:
1617 liveins: %w0
1718
19 ; Here the types don't match.
20 ; CHECK-LABEL: name: test_combines_2
21 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
22 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
23 ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
24 ; CHECK: [[EXTRACT:%[0-9]+]](s1) = G_EXTRACT [[MV]](s64), 0
25 ; CHECK: [[EXTRACT1:%[0-9]+]](s64) = G_EXTRACT [[MV]](s64), 0
1826 %0:_(s32) = COPY %w0
1927
20 ; Similarly, here the types don't match.
21 ; CHECK-LABEL: name: test_combines_2
22 ; CHECK: %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
23 ; CHECK: %3(s1) = G_EXTRACT %2(s64), 0
24 ; CHECK: %4(s64) = G_EXTRACT %2(s64), 0
2528 %1:_(s32) = G_ADD %0, %0
2629 %2:_(s64) = G_MERGE_VALUES %0, %1
2730 %3:_(s1) = G_EXTRACT %2, 0
3437 bb.0:
3538 liveins: %w0
3639
40 ; CHECK-LABEL: name: test_combines_3
41 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
42 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
43 ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
3744 %0:_(s32) = COPY %w0
3845
39 ; CHECK-LABEL: name: test_combines_3
40 ; CHECK: %1(s32) = G_ADD %0, %0
41 ; CHECK-NOT: G_SEQUENCE
42 ; CHECK-NOT: G_EXTRACT
43 ; CHECK: %5(s32) = G_ADD %0, %1
4446 %1:_(s32) = G_ADD %0, %0
4547 %2:_(s64) = G_MERGE_VALUES %0, %1
4648 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
5355 bb.0:
5456 liveins: %x0
5557
58 ; CHECK-LABEL: name: test_combines_4
59 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
60 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY [[COPY]](s64)
61 ; CHECK: [[ADD:%[0-9]+]](s64) = G_ADD [[COPY1]], [[COPY1]]
5662 %0:_(s64) = COPY %x0
5763
58 ; CHECK-LABEL: name: test_combines_4
59 ; CHECK: %2(s64) = COPY %0(s64)
60 ; CHECK: %3(s64) = G_ADD %2, %2
6164 %1:_(s128) = G_MERGE_VALUES %0, %0
6265 %2:_(s64) = G_EXTRACT %1, 0
6366 %3:_(s64) = G_ADD %2, %2
6972 bb.0:
7073 liveins: %w0
7174
75 ; CHECK-LABEL: name: test_combines_5
76 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
77 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
78 ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
7279 %0:_(s32) = COPY %w0
7380
74 ; CHECK-LABEL: name: test_combines_5
75 ; CHECK-NOT: G_MERGE_VALUES
76 ; CHECK-NOT: G_EXTRACT
77 ; CHECK: %5(s32) = G_ADD %0, %1
7881 %1:_(s32) = G_ADD %0, %0
7982 %2:_(s64) = G_MERGE_VALUES %0, %1
8083 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
8790 bb.0:
8891 liveins: %w0
8992
93 ; Check that we replace all the uses of a G_EXTRACT.
9094 ; CHECK-LABEL: name: test_combines_6
91 ; CHECK: %0(s32) = COPY %w0
95 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
96 ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]]
97 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[MUL]]
9298 %0:_(s32) = COPY %w0
9399
94 ; Check that we replace all the uses of a G_EXTRACT.
95 ; CHECK-NOT: G_MERGE_VALUES
96 ; CHECK-NOT: G_EXTRACT
97 ; CHECK: %3(s32) = G_MUL %0, %0
98 ; CHECK: %4(s32) = G_ADD %0, %3
99100 %1:_(s32) = G_MERGE_VALUES %0
100101 %2:_(s32) = G_UNMERGE_VALUES %1
101102 %3:_(s32) = G_MUL %2, %2
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2526 - { id: 5, class: _ }
2627 body: |
2728 bb.0.entry:
29
2830 ; CHECK-LABEL: name: test_constant
29 ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 0
30 ; CHECK: %0(s1) = G_TRUNC [[TMP]]
31 ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 42
32 ; CHECK: %1(s8) = G_TRUNC [[TMP]]
33 ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 -1
34 ; CHECK: %2(s16) = G_TRUNC [[TMP]]
35 ; CHECK: %3(s32) = G_CONSTANT i32 -1
36 ; CHECK: %4(s64) = G_CONSTANT i64 1
37 ; CHECK: %5(s64) = G_CONSTANT i64 0
38
31 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
32 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
33 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 42
34 ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[C1]](s32)
35 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 -1
36 ; CHECK: [[TRUNC2:%[0-9]+]](s16) = G_TRUNC [[C2]](s32)
37 ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 -1
38 ; CHECK: [[C4:%[0-9]+]](s64) = G_CONSTANT i64 1
39 ; CHECK: [[C5:%[0-9]+]](s64) = G_CONSTANT i64 0
3940 %0(s1) = G_CONSTANT i1 0
4041 %1(s8) = G_CONSTANT i8 42
4142 %2(s16) = G_CONSTANT i16 65535
5253 - { id: 2, class: _ }
5354 body: |
5455 bb.0.entry:
56
5557 ; CHECK-LABEL: name: test_fconstant
56 ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
57 ; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00
58 ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
59 ; CHECK: %2(s16) = G_FPTRUNC [[TMP]]
60
58 ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
59 ; CHECK: [[C1:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
60 ; CHECK: [[C2:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
61 ; CHECK: [[FPTRUNC:%[0-9]+]](s16) = G_FPTRUNC [[C2]](s32)
6162 %0(s32) = G_FCONSTANT float 1.0
6263 %1(s64) = G_FCONSTANT double 2.0
6364 %2(s16) = G_FCONSTANT half 0.0
6970 - { id: 0, class: _ }
7071 body: |
7172 bb.0:
73
7274 ; CHECK-LABEL: name: test_global
73 ; CHECK: %0(p0) = G_GLOBAL_VALUE @var
74
75 ; CHECK: [[GV:%[0-9]+]](p0) = G_GLOBAL_VALUE @var
7576 %0(p0) = G_GLOBAL_VALUE @var
7677 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 ---
910 ; value stored is forwarded directly from first load.
1011
1112 ; CHECK-LABEL: name: test_extracts_1
12 ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
13 ; CHECK: {{%[0-9]+}}(s64) = G_LOAD
14 ; CHECK: [[VAL:%[0-9]+]](s64) = COPY [[LO]]
15 ; CHECK: G_STORE [[VAL]]
13 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
14 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
15 ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
16 ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
17 ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
18 ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
19 ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
20 ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
21 ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
22 ; CHECK: RET_ReallyLR
1623 %0:_(s64) = COPY %x0
1724 %1:_(s32) = COPY %w1
1825 %2:_(p0) = COPY %x2
3037
3138 ; Low extraction wipes takes whole low register. High extraction is real.
3239 ; CHECK-LABEL: name: test_extracts_2
33 ; CHECK: [[LO_TMP:%[0-9]+]](s64) = G_LOAD
34 ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
35 ; CHECK: [[LO:%[0-9]+]](s64) = COPY [[LO_TMP]]
36 ; CHECK: [[NEWHI_TMP:%[0-9]+]](s32) = G_EXTRACT [[HI]](s64), 0
37 ; CHECK: [[NEWHI:%[0-9]+]](s32) = COPY [[NEWHI_TMP]]
38 ; CHECK: G_STORE [[LO]]
39 ; CHECK: G_STORE [[NEWHI]]
40 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
41 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
42 ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
43 ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
44 ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
45 ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
46 ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
47 ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
48 ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[LOAD1]](s64), 0
49 ; CHECK: [[COPY4:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
50 ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
51 ; CHECK: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store 4)
52 ; CHECK: RET_ReallyLR
4053 %0:_(s64) = COPY %x0
4154 %1:_(s32) = COPY %w1
4255 %2:_(p0) = COPY %x2
5669
5770
5871 ; CHECK-LABEL: name: test_extracts_3
59 ; CHECK: [[LO:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
60 ; CHECK: [[HI:%[0-9]+]](s32) = G_EXTRACT %1(s64), 0
61 ; CHECK: %3(s64) = G_MERGE_VALUES [[LO]](s32), [[HI]](s32)
72 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
73 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
74 ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
75 ; CHECK: [[EXTRACT1:%[0-9]+]](s32) = G_EXTRACT [[COPY1]](s64), 0
76 ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
77 ; CHECK: RET_ReallyLR
6278 %0:_(s64) = COPY %x0
6379 %1:_(s64) = COPY %x1
6480 %2:_(s128) = G_MERGE_VALUES %0, %1
7490
7591
7692 ; CHECK-LABEL: name: test_extracts_4
77 ; CHECK: [[LO_TMP:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
78 ; CHECK: %3(s32) = COPY [[LO_TMP]]
93 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
94 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
95 ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
96 ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
97 ; CHECK: RET_ReallyLR
7998 %0:_(s64) = COPY %x0
8099 %1:_(s64) = COPY %x1
81100 %2:_(s128) = G_MERGE_VALUES %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2021 bb.1:
2122 liveins: %s0
2223 ; CHECK-LABEL: name: test_fneg_f32
23 ; CHECK: [[VAR:%[0-9]+]](s32) = COPY %s0
24 ; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
25 ; CHECK: [[RES:%[0-9]+]](s32) = G_FSUB [[ZERO]], [[VAR]]
26 ; CHECK: %s0 = COPY [[RES]](s32)
24 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
25 ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
26 ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[C]], [[COPY]]
27 ; CHECK: %s0 = COPY [[FSUB]](s32)
2728 %0(s32) = COPY %s0
2829 %1(s32) = G_FNEG %0
2930 %s0 = COPY %1(s32)
3738 bb.1:
3839 liveins: %d0
3940 ; CHECK-LABEL: name: test_fneg_f64
40 ; CHECK: [[VAR:%[0-9]+]](s64) = COPY %d0
41 ; CHECK: [[ZERO:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
42 ; CHECK: [[RES:%[0-9]+]](s64) = G_FSUB [[ZERO]], [[VAR]]
43 ; CHECK: %d0 = COPY [[RES]](s64)
41 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0
42 ; CHECK: [[C:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
43 ; CHECK: [[FSUB:%[0-9]+]](s64) = G_FSUB [[C]], [[COPY]]
44 ; CHECK: %d0 = COPY [[FSUB]](s64)
4445 %0(s64) = COPY %d0
4546 %1(s64) = G_FNEG %0
4647 %d0 = COPY %1(s64)
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2829 body: |
2930 bb.0:
3031 liveins: %w0
31 %0:_(s32) = COPY %w0
32
3332 ; CHECK-LABEL: name: test_fptosi_s32_s32
34 ; CHECK: %1(s32) = G_FPTOSI %0
33 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
34 ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
35 %0:_(s32) = COPY %w0
3536 %1:_(s32) = G_FPTOSI %0
3637 ...
3738
4041 body: |
4142 bb.0:
4243 liveins: %w0
43 %0:_(s32) = COPY %w0
44
4544 ; CHECK-LABEL: name: test_fptoui_s32_s32
46 ; CHECK: %1(s32) = G_FPTOUI %0
45 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
46 ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
47 %0:_(s32) = COPY %w0
4748 %1:_(s32) = G_FPTOUI %0
4849 ...
4950
5253 body: |
5354 bb.0:
5455 liveins: %x0
55 %0:_(s64) = COPY %x0
56
5756 ; CHECK-LABEL: name: test_fptosi_s32_s64
58 ; CHECK: %1(s32) = G_FPTOSI %0
57 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
58 ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
59 %0:_(s64) = COPY %x0
5960 %1:_(s32) = G_FPTOSI %0
6061 ...
6162
6465 body: |
6566 bb.0:
6667 liveins: %x0
67 %0:_(s64) = COPY %x0
68
6968 ; CHECK-LABEL: name: test_fptoui_s32_s64
70 ; CHECK: %1(s32) = G_FPTOUI %0
69 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
70 ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
71 %0:_(s64) = COPY %x0
7172 %1:_(s32) = G_FPTOUI %0
7273 ...
7374
7677 body: |
7778 bb.0:
7879 liveins: %w0
79 %0:_(s32) = COPY %w0
80
8180 ; CHECK-LABEL: name: test_fptosi_s64_s32
82 ; CHECK: %1(s64) = G_FPTOSI %0
81 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
82 ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s32)
83 %0:_(s32) = COPY %w0
8384 %1:_(s64) = G_FPTOSI %0
8485 ...
8586
8889 body: |
8990 bb.0:
9091 liveins: %w0
91 %0:_(s32) = COPY %w0
92
9392 ; CHECK-LABEL: name: test_fptoui_s64_s32
94 ; CHECK: %1(s64) = G_FPTOUI %0
93 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
94 ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s32)
95 %0:_(s32) = COPY %w0
9596 %1:_(s64) = G_FPTOUI %0
9697 ...
9798
100101 body: |
101102 bb.0:
102103 liveins: %x0
103 %0:_(s64) = COPY %x0
104
105104 ; CHECK-LABEL: name: test_fptosi_s64_s64
106 ; CHECK: %1(s64) = G_FPTOSI %0
105 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
106 ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s64)
107 %0:_(s64) = COPY %x0
107108 %1:_(s64) = G_FPTOSI %0
108109 ...
109110
112113 body: |
113114 bb.0:
114115 liveins: %x0
115 %0:_(s64) = COPY %x0
116
117116 ; CHECK-LABEL: name: test_fptoui_s64_s64
118 ; CHECK: %1(s64) = G_FPTOUI %0
117 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
118 ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s64)
119 %0:_(s64) = COPY %x0
119120 %1:_(s64) = G_FPTOUI %0
120121 ...
121122
126127 body: |
127128 bb.0:
128129 liveins: %w0
129 %0:_(s32) = COPY %w0
130
131130 ; CHECK-LABEL: name: test_fptosi_s1_s32
132 ; CHECK: %2(s32) = G_FPTOSI %0
133 ; CHECK: %1(s1) = G_TRUNC %2
131 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
132 ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
133 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOSI]](s32)
134 %0:_(s32) = COPY %w0
134135 %1:_(s1) = G_FPTOSI %0
135136 ...
136137
139140 body: |
140141 bb.0:
141142 liveins: %w0
142 %0:_(s32) = COPY %w0
143
144143 ; CHECK-LABEL: name: test_fptoui_s1_s32
145 ; CHECK: %2(s32) = G_FPTOUI %0
146 ; CHECK: %1(s1) = G_TRUNC %2
144 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
145 ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
146 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOUI]](s32)
147 %0:_(s32) = COPY %w0
147148 %1:_(s1) = G_FPTOUI %0
148149 ...
149150
152153 body: |
153154 bb.0:
154155 liveins: %x0
155 %0:_(s64) = COPY %x0
156
157156 ; CHECK-LABEL: name: test_fptosi_s8_s64
158 ; CHECK: %2(s32) = G_FPTOSI %0
159 ; CHECK: %1(s8) = G_TRUNC %2
157 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
158 ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
159 ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOSI]](s32)
160 %0:_(s64) = COPY %x0
160161 %1:_(s8) = G_FPTOSI %0
161162 ...
162163
165166 body: |
166167 bb.0:
167168 liveins: %x0
168 %0:_(s64) = COPY %x0
169
170169 ; CHECK-LABEL: name: test_fptoui_s8_s64
171 ; CHECK: %2(s32) = G_FPTOUI %0
172 ; CHECK: %1(s8) = G_TRUNC %2
170 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
171 ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
172 ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOUI]](s32)
173 %0:_(s64) = COPY %x0
173174 %1:_(s8) = G_FPTOUI %0
174175 ...
175176
178179 body: |
179180 bb.0:
180181 liveins: %w0
181 %0:_(s32) = COPY %w0
182
183182 ; CHECK-LABEL: name: test_fptosi_s16_s32
184 ; CHECK: %2(s32) = G_FPTOSI %0
185 ; CHECK: %1(s16) = G_TRUNC %2
183 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
184 ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
185 ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOSI]](s32)
186 %0:_(s32) = COPY %w0
186187 %1:_(s16) = G_FPTOSI %0
187188 ...
188189
191192 body: |
192193 bb.0:
193194 liveins: %w0
194 %0:_(s32) = COPY %w0
195
196195 ; CHECK-LABEL: name: test_fptoui_s16_s32
197 ; CHECK: %2(s32) = G_FPTOUI %0
198 ; CHECK: %1(s16) = G_TRUNC %2
196 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
197 ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
198 ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOUI]](s32)
199 %0:_(s32) = COPY %w0
199200 %1:_(s16) = G_FPTOUI %0
200201 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1819 body: |
1920 bb.0.entry:
2021 liveins: %x0, %x1, %x2, %x3
22
2123 ; CHECK-LABEL: name: test_gep_small
22 ; CHECK: [[A:%.*]](p0) = COPY %x0
23 ; CHECK: [[B:%.*]](s64) = COPY %x1
24 ; CHECK: [[C:%.*]](s64) = G_CONSTANT i64 56
25 ; CHECK: [[SRC:%.*]](s64) = COPY [[B]](s64)
26 ; CHECK: [[SHL:%.*]](s64) = G_SHL [[SRC]], [[C]]
27 ; CHECK: [[SEXT:%.*]](s64) = G_ASHR [[SHL]], [[C]]
28 ; CHECK: G_GEP [[A]], [[SEXT]]
29
30
24 ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
25 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
26 ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 56
27 ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY [[COPY1]](s64)
28 ; CHECK: [[SHL:%[0-9]+]](s64) = G_SHL [[COPY2]], [[C]]
29 ; CHECK: [[ASHR:%[0-9]+]](s64) = G_ASHR [[SHL]], [[C]]
30 ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY]], [[ASHR]](s64)
31 ; CHECK: %x0 = COPY [[GEP]](p0)
3132 %0(p0) = COPY %x0
3233 %1(s64) = COPY %x1
3334 %2(s8) = G_TRUNC %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1314 body: |
1415 bb.0:
1516 liveins: %x0
17
1618 ; CHECK-LABEL: name: test_copy
17 ; CHECK: %0(s64) = COPY %x0
18 ; CHECK-NEXT: %x0 = COPY %0
19
19 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
20 ; CHECK: %x0 = COPY [[COPY]](s64)
2021 %0(s64) = COPY %x0
2122 %x0 = COPY %0
2223 ...
2526 name: test_targetspecific
2627 body: |
2728 bb.0:
29
2830 ; CHECK-LABEL: name: test_targetspecific
2931 ; CHECK: RET_ReallyLR
30
3132 RET_ReallyLR
3233 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2829 body: |
2930 bb.0:
3031 liveins: %w0
31 %0:_(s32) = COPY %w0
32
3332 ; CHECK-LABEL: name: test_sitofp_s32_s32
34 ; CHECK: %1(s32) = G_SITOFP %0
33 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
34 ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s32)
35 %0:_(s32) = COPY %w0
3536 %1:_(s32) = G_SITOFP %0
3637 ...
3738
4041 body: |
4142 bb.0:
4243 liveins: %w0
43 %0:_(s32) = COPY %w0
44
4544 ; CHECK-LABEL: name: test_uitofp_s32_s32
46 ; CHECK: %1(s32) = G_UITOFP %0
45 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
46 ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s32)
47 %0:_(s32) = COPY %w0
4748 %1:_(s32) = G_UITOFP %0
4849 ...
4950
5253 body: |
5354 bb.0:
5455 liveins: %x0
55 %0:_(s64) = COPY %x0
56
5756 ; CHECK-LABEL: name: test_sitofp_s32_s64
58 ; CHECK: %1(s32) = G_SITOFP %0
57 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
58 ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s64)
59 %0:_(s64) = COPY %x0
5960 %1:_(s32) = G_SITOFP %0
6061 ...
6162
6465 body: |
6566 bb.0:
6667 liveins: %x0
67 %0:_(s64) = COPY %x0
68
6968 ; CHECK-LABEL: name: test_uitofp_s32_s64
70 ; CHECK: %1(s32) = G_UITOFP %0
69 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
70 ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s64)
71 %0:_(s64) = COPY %x0
7172 %1:_(s32) = G_UITOFP %0
7273 ...
7374
7677 body: |
7778 bb.0:
7879 liveins: %w0
79 %0:_(s32) = COPY %w0
80
8180 ; CHECK-LABEL: name: test_sitofp_s64_s32
82 ; CHECK: %1(s64) = G_SITOFP %0
81 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
82 ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s32)
83 %0:_(s32) = COPY %w0
8384 %1:_(s64) = G_SITOFP %0
8485 ...
8586
8889 body: |
8990 bb.0:
9091 liveins: %w0
91 %0:_(s32) = COPY %w0
92
9392 ; CHECK-LABEL: name: test_uitofp_s64_s32
94 ; CHECK: %1(s64) = G_UITOFP %0
93 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
94 ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s32)
95 %0:_(s32) = COPY %w0
9596 %1:_(s64) = G_UITOFP %0
9697 ...
9798
100101 body: |
101102 bb.0:
102103 liveins: %x0
103 %0:_(s64) = COPY %x0
104
105104 ; CHECK-LABEL: name: test_sitofp_s64_s64
106 ; CHECK: %1(s64) = G_SITOFP %0
105 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
106 ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s64)
107 %0:_(s64) = COPY %x0
107108 %1:_(s64) = G_SITOFP %0
108109 ...
109110
112113 body: |
113114 bb.0:
114115 liveins: %x0
115 %0:_(s64) = COPY %x0
116
117116 ; CHECK-LABEL: name: test_uitofp_s64_s64
118 ; CHECK: %1(s64) = G_UITOFP %0
117 ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
118 ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s64)
119 %0:_(s64) = COPY %x0
119120 %1:_(s64) = G_UITOFP %0
120121 ...
121122
125126 body: |
126127 bb.0:
127128 liveins: %w0
129 ; CHECK-LABEL: name: test_sitofp_s32_s1
130 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
131 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 31
132 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
133 ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
134 ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
135 ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
128136 %0:_(s32) = COPY %w0
129137 %1:_(s1) = G_TRUNC %0
130
131 ; CHECK-LABEL: name: test_sitofp_s32_s1
132 ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 31
133 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
134 ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
135 ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
136 ; CHECK: %2(s32) = G_SITOFP [[SEXT]]
137138 %2:_(s32) = G_SITOFP %1
138139 ...
139140
142143 body: |
143144 bb.0:
144145 liveins: %w0
146 ; CHECK-LABEL: name: test_uitofp_s32_s1
147 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
148 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 1
149 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
150 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
151 ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
145152 %0:_(s32) = COPY %w0
146153 %1:_(s1) = G_TRUNC %0
147
148 ; CHECK-LABEL: name: test_uitofp_s32_s1
149 ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 1
150 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
151 ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
152 ; CHECK: [[RES:%.*]](s32) = G_UITOFP [[ZEXT]]
153154 %2:_(s32) = G_UITOFP %1
154155 ...
155156
158159 body: |
159160 bb.0:
160161 liveins: %w0
162 ; CHECK-LABEL: name: test_sitofp_s64_s8
163 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
164 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 24
165 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
166 ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
167 ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
168 ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[ASHR]](s32)
161169 %0:_(s32) = COPY %w0
162170 %1:_(s8) = G_TRUNC %0
163
164 ; CHECK-LABEL: name: test_sitofp_s64_s8
165 ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
166 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
167 ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
168 ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
169 ; CHECK: %2(s64) = G_SITOFP [[SEXT]]
170171 %2:_(s64) = G_SITOFP %1
171172 ...
172173
175176 body: |
176177 bb.0:
177178 liveins: %w0
179 ; CHECK-LABEL: name: test_uitofp_s64_s8
180 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
181 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 255
182 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
183 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
184 ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[AND]](s32)
178185 %0:_(s32) = COPY %w0
179186 %1:_(s8) = G_TRUNC %0
180
181 ; CHECK-LABEL: name: test_uitofp_s64_s8
182 ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 255
183 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
184 ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
185 ; CHECK: %2(s64) = G_UITOFP [[ZEXT]]
186187 %2:_(s64) = G_UITOFP %1
187188 ...
188189
191192 body: |
192193 bb.0:
193194 liveins: %w0
195 ; CHECK-LABEL: name: test_sitofp_s32_s16
196 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
197 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 16
198 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
199 ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
200 ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
201 ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
194202 %0:_(s32) = COPY %w0
195203 %1:_(s16) = G_TRUNC %0
196
197 ; CHECK-LABEL: name: test_sitofp_s32_s16
198 ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 16
199 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
200 ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
201 ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
202 ; CHECK: %2(s32) = G_SITOFP [[SEXT]]
203204 %2:_(s32) = G_SITOFP %1
204205 ...
205206
208209 body: |
209210 bb.0:
210211 liveins: %w0
212 ; CHECK-LABEL: name: test_uitofp_s32_s16
213 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
214 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 65535
215 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
216 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
217 ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
211218 %0:_(s32) = COPY %w0
212219 %1:_(s16) = G_TRUNC %0
213
214 ; CHECK-LABEL: name: test_uitofp_s32_s16
215 ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 65535
216 ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
217 ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
218 ; CHECK: [[RES:%.*]](s32) = G_UITOFP [[ZEXT]]
219220 %2:_(s32) = G_UITOFP %1
220221 ...
5353 ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
5454 ; CHECK: [[MUL:%[0-9]+]](s64) = G_MUL [[COPY]], [[COPY1]]
5555 ; CHECK: [[SMULH:%[0-9]+]](s64) = G_SMULH [[COPY]], [[COPY1]]
56 ; CHECK: [[C2:%[0-9]+]](s64) = G_CONSTANT i64 0
57 ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C2]]
56 ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 0
57 ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
5858 ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32)
5959 %0:_(s64) = COPY %x0
6060 %1:_(s64) = COPY %x1
61
6261 %2:_(s64), %3:_(s1) = G_SMULO %0, %1
6362
6463 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1718 bb.0:
1819 liveins: %w0, %w1, %w2
1920 ; CHECK-LABEL: name: test_legalize_merge_v3s32
20 ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
21 ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1
22 ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2
23 ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32)
21 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
22 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
23 ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY %w2
24 ; CHECK: [[MV:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
2425 %0(s32) = COPY %w0
2526 %1(s32) = COPY %w1
2627 %2(s32) = COPY %w2
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 ---
67 bb.0.entry:
78 liveins:
89 ; CHECK-LABEL: name: test_implicit_def
9 ; CHECK: [[LO:%[0-9]+]](s64) = G_IMPLICIT_DEF
10 ; CHECK: [[HI:%[0-9]+]](s64) = G_IMPLICIT_DEF
11 ; CHECK: %0(s128) = G_MERGE_VALUES [[LO]](s64), [[HI]](s64)
10 ; CHECK: [[DEF:%[0-9]+]](s64) = G_IMPLICIT_DEF
11 ; CHECK: [[DEF1:%[0-9]+]](s64) = G_IMPLICIT_DEF
12 ; CHECK: [[MV:%[0-9]+]](s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
1213
1314 %0:_(s128) = G_IMPLICIT_DEF
1415 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s
12
23 # We run the legalizer to combine the trivial EXTRACT_SEQ pair, leaving %1 and
910 define void @unused_reg() { ret void }
1011
1112 ---
12 # CHECK-LABEL: name: unused_reg
1313 name: unused_reg
1414 legalized: true
1515 regBankSelected: true
1616 tracksRegLiveness: true
1717
18 # CHECK: body:
19 # CHECK: %0 = COPY %w0
20 # CHECK: %w0 = COPY %0
2118
2219 body: |
2320 bb.0:
2421 liveins: %w0
22 ; CHECK-LABEL: name: unused_reg
23 ; CHECK: liveins: %w0
24 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
25 ; CHECK: %w0 = COPY [[COPY]]
2526 %0:gpr(s32) = COPY %w0
2627 %1:gpr(s32) = G_MERGE_VALUES %0(s32)
2728 %2:gpr(s32) = G_UNMERGE_VALUES %1(s32)
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
12
23 --- |
1213 ...
1314
1415 ---
15 # CHECK-LABEL: name: const_s32
1616 name: const_s32
1717 legalized: true
1818 regBankSelected: true
1919 registers:
2020 - { id: 0, class: gpr }
2121
22 # CHECK: body:
23 # CHECK: %0 = MOVi32imm 42
2422 body: |
2523 bb.0:
24 ; CHECK-LABEL: name: const_s32
25 ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 42
26 ; CHECK: %w0 = COPY [[MOVi32imm]]
2627 %0(s32) = G_CONSTANT i32 42
2728 %w0 = COPY %0(s32)
2829 ...
2930
3031 ---
31 # CHECK-LABEL: name: const_s64
3232 name: const_s64
3333 legalized: true
3434 regBankSelected: true
3535 registers:
3636 - { id: 0, class: gpr }
3737
38 # CHECK: body:
39 # CHECK: %0 = MOVi64imm 1234567890123
4038 body: |
4139 bb.0:
40 ; CHECK-LABEL: name: const_s64
41 ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234567890123
42 ; CHECK: %x0 = COPY [[MOVi64imm]]
4243 %0(s64) = G_CONSTANT i64 1234567890123
4344 %x0 = COPY %0(s64)
4445 ...
4546
4647 ---
47 # CHECK-LABEL: name: fconst_s32
4848 name: fconst_s32
4949 legalized: true
5050 regBankSelected: true
5151 registers:
5252 - { id: 0, class: fpr }
5353
54 # CHECK: body:
55 # CHECK: [[TMP:%[0-9]+]] = MOVi32imm 1080033280
56 # CHECK: %0 = COPY [[TMP]]
5754 body: |
5855 bb.0:
56 ; CHECK-LABEL: name: fconst_s32
57 ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1080033280
58 ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi32imm]]
59 ; CHECK: %s0 = COPY [[COPY]]
5960 %0(s32) = G_FCONSTANT float 3.5
6061 %s0 = COPY %0(s32)
6162 ...
6263
6364 ---
64 # CHECK-LABEL: name: fconst_s64
6565 name: fconst_s64
6666 legalized: true
6767 regBankSelected: true
6868 registers:
6969 - { id: 0, class: fpr }
7070
71 # CHECK: body:
72 # CHECK: [[TMP:%[0-9]+]] = MOVi64imm 4607182418800017408
73 # CHECK: %0 = COPY [[TMP]]
7471 body: |
7572 bb.0:
73 ; CHECK-LABEL: name: fconst_s64
74 ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 4607182418800017408
75 ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi64imm]]
76 ; CHECK: %d0 = COPY [[COPY]]
7677 %0(s64) = G_FCONSTANT double 1.0
7778 %d0 = COPY %0(s64)
7879 ...
7980
8081 ---
81 # CHECK-LABEL: name: fconst_s32_0
8282 name: fconst_s32_0
8383 legalized: true
8484 regBankSelected: true
8585 registers:
8686 - { id: 0, class: fpr }
8787
88 # CHECK: body:
89 # CHECK: [[TMP:%[0-9]+]] = FMOVS0
90 # CHECK: %s0 = COPY [[TMP]]
9188 body: |
9289 bb.0:
90 ; CHECK-LABEL: name: fconst_s32_0
91 ; CHECK: [[FMOVS0_:%[0-9]+]] = FMOVS0
92 ; CHECK: %s0 = COPY [[FMOVS0_]]
9393 %0(s32) = G_FCONSTANT float 0.0
9494 %s0 = COPY %0(s32)
9595 ...
9696
9797 ---
98 # CHECK-LABEL: name: fconst_s64_0
9998 name: fconst_s64_0
10099 legalized: true
101100 regBankSelected: true
102101 registers:
103102 - { id: 0, class: fpr }
104103
105 # CHECK: body:
106 # CHECK: [[TMP:%[0-9]+]] = FMOVD0
107 # CHECK: %s0 = COPY [[TMP]]
108104 body: |
109105 bb.0:
106 ; CHECK-LABEL: name: fconst_s64_0
107 ; CHECK: [[FMOVD0_:%[0-9]+]] = FMOVD0
108 ; CHECK: %s0 = COPY [[FMOVD0_]]
110109 %0(s64) = G_FCONSTANT double 0.0
111110 %s0 = COPY %0(s64)
112111 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple arm64-- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
12
23 --- |
3435 ...
3536
3637 ---
37 # CHECK-LABEL: name: test_dbg_value
3838 name: test_dbg_value
3939 legalized: true
4040 regBankSelected: true
4141 body: |
4242 bb.0:
4343 liveins: %w0
44 ; CHECK-LABEL: name: test_dbg_value
45 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
46 ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[COPY]], [[COPY]]
47 ; CHECK: %w0 = COPY [[ADDWrr]]
48 ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9
4449 %0:gpr(s32) = COPY %w0
4550 %1:gpr(s32) = G_ADD %0, %0
4651 %w0 = COPY %1(s32)
47
48 ; CHECK: %0 = COPY %w0
49 ; CHECK-NEXT: %1 = ADDWrr %0, %0
50 ; CHECK-NEXT: %w0 = COPY %1
51 ; CHECK-NEXT: DBG_VALUE debug-use %1, debug-use _, !7, !DIExpression(), debug-location !9
52
5352 DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9
5453 ...
5554
5655 ---
57 # CHECK-LABEL: name: test_dbg_value_dead
5856 name: test_dbg_value_dead
5957 legalized: true
6058 regBankSelected: true
6159 body: |
6260 bb.0:
6361 liveins: %w0
64 %0:gpr(s32) = COPY %w0
65
62 ; CHECK-LABEL: name: test_dbg_value_dead
6663 ; CHECK-NOT: COPY
6764 ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9
68
65 %0:gpr(s32) = COPY %w0
6966 DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
7067 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
12
23 --- |
45 entry:
56 ret i32 0
67 }
7
8
89 declare i32 @printf(i8*, ...)
910 ...
1011 ---
11 # CHECK-LABEL: name: main
1212 name: main
1313 alignment: 2
1414 exposesReturnsTwice: false
1616 regBankSelected: true
1717 selected: false
1818 tracksRegLiveness: true
19 registers:
19 registers:
2020 - { id: 0, class: gpr }
2121 - { id: 1, class: gpr }
2222 - { id: 2, class: gpr }
3333 - { id: 13, class: gpr }
3434 - { id: 14, class: gpr }
3535 - { id: 15, class: gpr }
36 frameInfo:
36 frameInfo:
3737 isFrameAddressTaken: false
3838 isReturnAddressTaken: false
3939 hasStackMap: false
4747 hasOpaqueSPAdjustment: false
4848 hasVAStart: false
4949 hasMustTailInVarArgFunc: false
50 # CHECK: body:
51 # CHECK: %1 = COPY %w0
52 # CHECK-NOT: %2 = ORNWrr %wzr, %1
53 # CHECK: %4 = EONWrr %1, %3
5450 body: |
5551 bb.1.entry:
5652 liveins: %w0
53 ; CHECK-LABEL: name: main
54 ; CHECK: liveins: %w0
55 ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1
56 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
57 ; CHECK: [[EONWrr:%[0-9]+]] = EONWrr [[COPY]], [[MOVi32imm]]
58 ; CHECK: %w0 = COPY [[EONWrr]]
5759 %0(s32) = G_CONSTANT i32 -1
5860 %3(s32) = G_CONSTANT i32 1
5961 %1(s32) = COPY %w0
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1213 body: |
1314 bb.0:
1415 liveins: %vgpr0, %vgpr1
16
1517 ; CHECK-LABEL: name: test_add
16 ; CHECK: %2(s32) = G_ADD %0, %1
17
18 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
19 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
20 ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY1]]
1821 %0(s32) = COPY %vgpr0
1922 %1(s32) = COPY %vgpr1
2023 %2(s32) = G_ADD %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1213 body: |
1314 bb.0:
1415 liveins: %vgpr0, %vgpr1
16
1517 ; CHECK-LABEL: name: test_and
16 ; CHECK: %2(s32) = G_AND %0, %1
17
18 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
19 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
20 ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY]], [[COPY1]]
1821 %0(s32) = COPY %vgpr0
1922 %1(s32) = COPY %vgpr1
2023 %2(s32) = G_AND %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1213 body: |
1314 bb.0:
1415 liveins: %vgpr0
16
1517 ; CHECK-LABEL: name: test_bitcast
16 ; CHECK: %1(<2 x s16>) = G_BITCAST %0
17 ; CHECK: %2(s32) = G_BITCAST %1
18
18 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
19 ; CHECK: [[BITCAST:%[0-9]+]](<2 x s16>) = G_BITCAST [[COPY]](s32)
20 ; CHECK: [[BITCAST1:%[0-9]+]](s32) = G_BITCAST [[BITCAST]](<2 x s16>)
1921 %0(s32) = COPY %vgpr0
2022 %1(<2 x s16>) = G_BITCAST %0
2123 %2(s32) = G_BITCAST %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
2324 - { id: 1, class: _ }
2425 body: |
2526 bb.0.entry:
27
2628 ; CHECK-LABEL: name: test_constant
27 ; CHECK: %0(s32) = G_CONSTANT i32 5
28 ; CHECK: %1(s1) = G_CONSTANT i1 false
29
29 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 5
30 ; CHECK: [[C1:%[0-9]+]](s1) = G_CONSTANT i1 false
3031 %0(s32) = G_CONSTANT i32 5
3132 %1(s1) = G_CONSTANT i1 0
3233 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
3940 - { id: 1, class: _ }
4041 body: |
4142 bb.0.entry:
43
4244 ; CHECK-LABEL: name: test_fconstant
43 ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
44 ; CHECK: %1(s32) = G_FCONSTANT float 7.5
45
45 ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
46 ; CHECK: [[C1:%[0-9]+]](s32) = G_FCONSTANT float 7.500000e+00
4647 %0(s32) = G_FCONSTANT float 1.0
4748 %1(s32) = G_FCONSTANT float 7.5
4849 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1213 body: |
1314 bb.0:
1415 liveins: %vgpr0, %vgpr1
16
1517 ; CHECK-LABEL: name: test_fmul
16 ; CHECK: %2(s32) = G_FMUL %0, %1
17
18 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
19 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
20 ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY1]]
1821 %0(s32) = COPY %vgpr0
1922 %1(s32) = COPY %vgpr1
2023 %2(s32) = G_FMUL %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1516 body: |
1617 bb.0.entry:
1718 liveins: %vgpr0
19 ; CHECK-LABEL: name: test_icmp
20 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
21 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
22 ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
1823 %0(s32) = G_CONSTANT i32 0
1924 %1(s32) = COPY %vgpr0
20
21 ; CHECK: %2(s1) = G_ICMP intpred(ne), %0(s32), %1
2225 %2(s1) = G_ICMP intpred(ne), %0, %1
2326 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1112 body: |
1213 bb.0:
1314 liveins: %vgpr0, %vgpr1
15
1416 ; CHECK-LABEL: name: test_or
15 ; CHECK: %2(s32) = G_OR %0, %1
16
17 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
18 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
19 ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[COPY]], [[COPY1]]
1720 %0(s32) = COPY %vgpr0
1821 %1(s32) = COPY %vgpr1
1922 %2(s32) = G_OR %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 --- |
1516 body: |
1617 bb.0:
1718 liveins: %vgpr0
19 ; CHECK-LABEL: name: test_select
20 ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
21 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
22 ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
23 ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
24 ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
25 ; CHECK: [[SELECT:%[0-9]+]](s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
1826 %0(s32) = G_CONSTANT i32 0
1927 %1(s32) = COPY %vgpr0
2028
2129 %2(s1) = G_ICMP intpred(ne), %0, %1
2230 %3(s32) = G_CONSTANT i32 1
2331 %4(s32) = G_CONSTANT i32 2
24 ; CHECK: %5(s32) = G_SELECT %2(s1), %3, %4
2532 %5(s32) = G_SELECT %2, %3, %4
2633
2734 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
12
23 ---
89 body: |
910 bb.0.entry:
1011 liveins: %vgpr0, %vgpr1
12
1113 ; CHECK-LABEL: name: test_shl
12 ; CHECK: %2(s32) = G_SHL %0, %1
13
14 ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
15 ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
16 ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY]], [[COPY1]]
1417 %0(s32) = COPY %vgpr0
1518 %1(s32) = COPY %vgpr1
1619 %2(s32) = G_SHL %0, %1
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
12 --- |
23 define void @test_icmp_eq_s32() { ret void }
5253 ...
5354 ---
5455 name: test_icmp_eq_s32
55 # CHECK-LABEL: name: test_icmp_eq_s32
56 legalized: true
57 regBankSelected: true
58 selected: false
59 # CHECK: selected: true
56 legalized: true
57 regBankSelected: true
58 selected: false
6059 registers:
6160 - { id: 0, class: gprb }
6261 - { id: 1, class: gprb }
6665 bb.0:
6766 liveins: %r0, %r1
6867
68 ; CHECK-LABEL: name: test_icmp_eq_s32
69 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
70 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
71 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
72 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
73 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
74 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
75 ; CHECK: %r0 = COPY [[ANDri]]
76 ; CHECK: BX_RET 14, _, implicit %r0
6977 %0(s32) = COPY %r0
70 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
71
7278 %1(s32) = COPY %r1
73 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
74
7579 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
76 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
77 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
78 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
79
80 %3(s32) = G_ZEXT %2(s1)
81 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
82
83 %r0 = COPY %3(s32)
84 ; CHECK: %r0 = COPY [[RET]]
85
86 BX_RET 14, _, implicit %r0
87 ; CHECK: BX_RET 14, _, implicit %r0
80 %3(s32) = G_ZEXT %2(s1)
81 %r0 = COPY %3(s32)
82 BX_RET 14, _, implicit %r0
8883 ...
8984 ---
9085 name: test_icmp_ne_s32
91 # CHECK-LABEL: name: test_icmp_ne_s32
92 legalized: true
93 regBankSelected: true
94 selected: false
95 # CHECK: selected: true
86 legalized: true
87 regBankSelected: true
88 selected: false
9689 registers:
9790 - { id: 0, class: gprb }
9891 - { id: 1, class: gprb }
10295 bb.0:
10396 liveins: %r0, %r1
10497
98 ; CHECK-LABEL: name: test_icmp_ne_s32
99 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
100 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
101 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
102 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
103 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
104 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
105 ; CHECK: %r0 = COPY [[ANDri]]
106 ; CHECK: BX_RET 14, _, implicit %r0
105107 %0(s32) = COPY %r0
106 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
107
108108 %1(s32) = COPY %r1
109 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
110
111109 %2(s1) = G_ICMP intpred(ne), %0(s32), %1
112 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
113 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
114 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
115
116 %3(s32) = G_ZEXT %2(s1)
117 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
118
119 %r0 = COPY %3(s32)
120 ; CHECK: %r0 = COPY [[RET]]
121
122 BX_RET 14, _, implicit %r0
123 ; CHECK: BX_RET 14, _, implicit %r0
110 %3(s32) = G_ZEXT %2(s1)
111 %r0 = COPY %3(s32)
112 BX_RET 14, _, implicit %r0
124113 ...
125114 ---
126115 name: test_icmp_ugt_s32
127 # CHECK-LABEL: name: test_icmp_ugt_s32
128 legalized: true
129 regBankSelected: true
130 selected: false
131 # CHECK: selected: true
116 legalized: true
117 regBankSelected: true
118 selected: false
132119 registers:
133120 - { id: 0, class: gprb }
134121 - { id: 1, class: gprb }
138125 bb.0:
139126 liveins: %r0, %r1
140127
128 ; CHECK-LABEL: name: test_icmp_ugt_s32
129 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
130 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
131 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
132 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
133 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
134 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
135 ; CHECK: %r0 = COPY [[ANDri]]
136 ; CHECK: BX_RET 14, _, implicit %r0
141137 %0(s32) = COPY %r0
142 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
143
144138 %1(s32) = COPY %r1
145 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
146
147139 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
148 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
149 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
150 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
151
152 %3(s32) = G_ZEXT %2(s1)
153 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
154
155 %r0 = COPY %3(s32)
156 ; CHECK: %r0 = COPY [[RET]]
157
158 BX_RET 14, _, implicit %r0
159 ; CHECK: BX_RET 14, _, implicit %r0
140 %3(s32) = G_ZEXT %2(s1)
141 %r0 = COPY %3(s32)
142 BX_RET 14, _, implicit %r0
160143 ...
161144 ---
162145 name: test_icmp_uge_s32
163 # CHECK-LABEL: name: test_icmp_uge_s32
164 legalized: true
165 regBankSelected: true
166 selected: false
167 # CHECK: selected: true
146 legalized: true
147 regBankSelected: true
148 selected: false
168149 registers:
169150 - { id: 0, class: gprb }
170151 - { id: 1, class: gprb }
174155 bb.0:
175156 liveins: %r0, %r1
176157
158 ; CHECK-LABEL: name: test_icmp_uge_s32
159 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
160 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
161 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
162 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
163 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 2, %cpsr
164 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
165 ; CHECK: %r0 = COPY [[ANDri]]
166 ; CHECK: BX_RET 14, _, implicit %r0
177167 %0(s32) = COPY %r0
178 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
179
180168 %1(s32) = COPY %r1
181 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
182
183169 %2(s1) = G_ICMP intpred(uge), %0(s32), %1
184 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
185 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
186 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr
187
188 %3(s32) = G_ZEXT %2(s1)
189 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
190
191 %r0 = COPY %3(s32)
192 ; CHECK: %r0 = COPY [[RET]]
193
194 BX_RET 14, _, implicit %r0
195 ; CHECK: BX_RET 14, _, implicit %r0
170 %3(s32) = G_ZEXT %2(s1)
171 %r0 = COPY %3(s32)
172 BX_RET 14, _, implicit %r0
196173 ...
197174 ---
198175 name: test_icmp_ult_s32
199 # CHECK-LABEL: name: test_icmp_ult_s32
200 legalized: true
201 regBankSelected: true
202 selected: false
203 # CHECK: selected: true
176 legalized: true
177 regBankSelected: true
178 selected: false
204179 registers:
205180 - { id: 0, class: gprb }
206181 - { id: 1, class: gprb }
210185 bb.0:
211186 liveins: %r0, %r1
212187
188 ; CHECK-LABEL: name: test_icmp_ult_s32
189 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
190 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
191 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
192 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
193 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 3, %cpsr
194 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
195 ; CHECK: %r0 = COPY [[ANDri]]
196 ; CHECK: BX_RET 14, _, implicit %r0
213197 %0(s32) = COPY %r0
214 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
215
216198 %1(s32) = COPY %r1
217 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
218
219199 %2(s1) = G_ICMP intpred(ult), %0(s32), %1
220 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
221 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
222 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr
223
224 %3(s32) = G_ZEXT %2(s1)
225 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
226
227 %r0 = COPY %3(s32)
228 ; CHECK: %r0 = COPY [[RET]]
229
230 BX_RET 14, _, implicit %r0
231 ; CHECK: BX_RET 14, _, implicit %r0
200 %3(s32) = G_ZEXT %2(s1)
201 %r0 = COPY %3(s32)
202 BX_RET 14, _, implicit %r0
232203 ...
233204 ---
234205 name: test_icmp_ule_s32
235 # CHECK-LABEL: name: test_icmp_ule_s32
236 legalized: true
237 regBankSelected: true
238 selected: false
239 # CHECK: selected: true
206 legalized: true
207 regBankSelected: true
208 selected: false
240209 registers:
241210 - { id: 0, class: gprb }
242211 - { id: 1, class: gprb }
246215 bb.0:
247216 liveins: %r0, %r1
248217
218 ; CHECK-LABEL: name: test_icmp_ule_s32
219 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
220 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
221 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
222 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
223 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
224 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
225 ; CHECK: %r0 = COPY [[ANDri]]
226 ; CHECK: BX_RET 14, _, implicit %r0
249227 %0(s32) = COPY %r0
250 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
251
252228 %1(s32) = COPY %r1
253 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
254
255229 %2(s1) = G_ICMP intpred(ule), %0(s32), %1
256 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
257 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
258 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
259
260 %3(s32) = G_ZEXT %2(s1)
261 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
262
263 %r0 = COPY %3(s32)
264 ; CHECK: %r0 = COPY [[RET]]
265
266 BX_RET 14, _, implicit %r0
267 ; CHECK: BX_RET 14, _, implicit %r0
230 %3(s32) = G_ZEXT %2(s1)
231 %r0 = COPY %3(s32)
232 BX_RET 14, _, implicit %r0
268233 ...
269234 ---
270235 name: test_icmp_sgt_s32
271 # CHECK-LABEL: name: test_icmp_sgt_s32
272 legalized: true
273 regBankSelected: true
274 selected: false
275 # CHECK: selected: true
236 legalized: true
237 regBankSelected: true
238 selected: false
276239 registers:
277240 - { id: 0, class: gprb }
278241 - { id: 1, class: gprb }
282245 bb.0:
283246 liveins: %r0, %r1
284247
248 ; CHECK-LABEL: name: test_icmp_sgt_s32
249 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
250 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
251 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
252 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
253 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
254 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
255 ; CHECK: %r0 = COPY [[ANDri]]
256 ; CHECK: BX_RET 14, _, implicit %r0
285257 %0(s32) = COPY %r0
286 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
287
288258 %1(s32) = COPY %r1
289 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
290
291259 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
292 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
293 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
294 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
295
296 %3(s32) = G_ZEXT %2(s1)
297 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
298
299 %r0 = COPY %3(s32)
300 ; CHECK: %r0 = COPY [[RET]]
301
302 BX_RET 14, _, implicit %r0
303 ; CHECK: BX_RET 14, _, implicit %r0
260 %3(s32) = G_ZEXT %2(s1)
261 %r0 = COPY %3(s32)
262 BX_RET 14, _, implicit %r0
304263 ...
305264 ---
306265 name: test_icmp_sge_s32
307 # CHECK-LABEL: name: test_icmp_sge_s32
308 legalized: true
309 regBankSelected: true
310 selected: false
311 # CHECK: selected: true
266 legalized: true
267 regBankSelected: true
268 selected: false
312269 registers:
313270 - { id: 0, class: gprb }
314271 - { id: 1, class: gprb }
318275 bb.0:
319276 liveins: %r0, %r1
320277
278 ; CHECK-LABEL: name: test_icmp_sge_s32
279 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
280 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
281 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
282 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
283 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
284 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
285 ; CHECK: %r0 = COPY [[ANDri]]
286 ; CHECK: BX_RET 14, _, implicit %r0
321287 %0(s32) = COPY %r0
322 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
323
324288 %1(s32) = COPY %r1
325 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
326
327289 %2(s1) = G_ICMP intpred(sge), %0(s32), %1
328 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
329 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
330 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
331
332 %3(s32) = G_ZEXT %2(s1)
333 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
334
335 %r0 = COPY %3(s32)
336 ; CHECK: %r0 = COPY [[RET]]
337
338 BX_RET 14, _, implicit %r0
339 ; CHECK: BX_RET 14, _, implicit %r0
290 %3(s32) = G_ZEXT %2(s1)
291 %r0 = COPY %3(s32)
292 BX_RET 14, _, implicit %r0
340293 ...
341294 ---
342295 name: test_icmp_slt_s32
343 # CHECK-LABEL: name: test_icmp_slt_s32
344 legalized: true
345 regBankSelected: true
346 selected: false
347 # CHECK: selected: true
296 legalized: true
297 regBankSelected: true
298 selected: false
348299 registers:
349300 - { id: 0, class: gprb }
350301 - { id: 1, class: gprb }
354305 bb.0:
355306 liveins: %r0, %r1
356307
308 ; CHECK-LABEL: name: test_icmp_slt_s32
309 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
310 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
311 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
312 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
313 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
314 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
315 ; CHECK: %r0 = COPY [[ANDri]]
316 ; CHECK: BX_RET 14, _, implicit %r0
357317 %0(s32) = COPY %r0
358 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
359
360318 %1(s32) = COPY %r1
361 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
362
363319 %2(s1) = G_ICMP intpred(slt), %0(s32), %1
364 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
365 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
366 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
367
368 %3(s32) = G_ZEXT %2(s1)
369 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
370
371 %r0 = COPY %3(s32)
372 ; CHECK: %r0 = COPY [[RET]]
373
374 BX_RET 14, _, implicit %r0
375 ; CHECK: BX_RET 14, _, implicit %r0
320 %3(s32) = G_ZEXT %2(s1)
321 %r0 = COPY %3(s32)
322 BX_RET 14, _, implicit %r0
376323 ...
377324 ---
378325 name: test_icmp_sle_s32
379 # CHECK-LABEL: name: test_icmp_sle_s32
380 legalized: true
381 regBankSelected: true
382 selected: false
383 # CHECK: selected: true
326 legalized: true
327 regBankSelected: true
328 selected: false
384329 registers:
385330 - { id: 0, class: gprb }
386331 - { id: 1, class: gprb }
390335 bb.0:
391336 liveins: %r0, %r1
392337
338 ; CHECK-LABEL: name: test_icmp_sle_s32
339 ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
340 ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
341 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
342 ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
343 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
344 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
345 ; CHECK: %r0 = COPY [[ANDri]]
346 ; CHECK: BX_RET 14, _, implicit %r0
393347 %0(s32) = COPY %r0
394 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
395
396348 %1(s32) = COPY %r1
397 ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
398
399349 %2(s1) = G_ICMP intpred(sle), %0(s32), %1
400 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
401 ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
402 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
403
404 %3(s32) = G_ZEXT %2(s1)
405 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
406
407 %r0 = COPY %3(s32)
408 ; CHECK: %r0 = COPY [[RET]]
409
410 BX_RET 14, _, implicit %r0
411 ; CHECK: BX_RET 14, _, implicit %r0
350 %3(s32) = G_ZEXT %2(s1)
351 %r0 = COPY %3(s32)
352 BX_RET 14, _, implicit %r0
412353 ...
413354 ---
414355 name: test_fcmp_true_s32
415 # CHECK-LABEL: name: test_fcmp_true_s32
416 legalized: true
417 regBankSelected: true
418 selected: false
419 # CHECK: selected: true
420 registers:
421 - { id: 0, class: fprb }
422 - { id: 1, class: fprb }
423 - { id: 2, class: gprb }
424 - { id: 3, class: gprb }
425 body: |
426 bb.0:
427 liveins: %s0, %s1
428
429 %0(s32) = COPY %s0
430 %1(s32) = COPY %s1
431
356 legalized: true
357 regBankSelected: true
358 selected: false
359 registers:
360 - { id: 0, class: fprb }
361 - { id: 1, class: fprb }
362 - { id: 2, class: gprb }
363 - { id: 3, class: gprb }
364 body: |
365 bb.0:
366 liveins: %s0, %s1
367
368 ; CHECK-LABEL: name: test_fcmp_true_s32
369 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
370 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
371 ; CHECK: %r0 = COPY [[ANDri]]
372 ; CHECK: BX_RET 14, _, implicit %r0
373 %0(s32) = COPY %s0
374 %1(s32) = COPY %s1
432375 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
433 ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
434
435 %3(s32) = G_ZEXT %2(s1)
436 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
437
438 %r0 = COPY %3(s32)
439 ; CHECK: %r0 = COPY [[RET]]
440
441 BX_RET 14, _, implicit %r0
442 ; CHECK: BX_RET 14, _, implicit %r0
376 %3(s32) = G_ZEXT %2(s1)
377 %r0 = COPY %3(s32)
378 BX_RET 14, _, implicit %r0
443379 ...
444380 ---
445381 name: test_fcmp_false_s32
446 # CHECK-LABEL: name: test_fcmp_false_s32
447 legalized: true
448 regBankSelected: true
449 selected: false
450 # CHECK: selected: true
451 registers:
452 - { id: 0, class: fprb }
453 - { id: 1, class: fprb }
454 - { id: 2, class: gprb }
455 - { id: 3, class: gprb }
456 body: |
457 bb.0:
458 liveins: %s0, %s1
459
460 %0(s32) = COPY %s0
461 %1(s32) = COPY %s1
462
382 legalized: true
383 regBankSelected: true
384 selected: false
385 registers:
386 - { id: 0, class: fprb }
387 - { id: 1, class: fprb }
388 - { id: 2, class: gprb }
389 - { id: 3, class: gprb }
390 body: |
391 bb.0:
392 liveins: %s0, %s1
393
394 ; CHECK-LABEL: name: test_fcmp_false_s32
395 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
396 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
397 ; CHECK: %r0 = COPY [[ANDri]]
398 ; CHECK: BX_RET 14, _, implicit %r0
399 %0(s32) = COPY %s0
400 %1(s32) = COPY %s1
463401 %2(s1) = G_FCMP floatpred(false), %0(s32), %1
464 ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
465
466 %3(s32) = G_ZEXT %2(s1)
467 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
468
469 %r0 = COPY %3(s32)
470 ; CHECK: %r0 = COPY [[RET]]
471
472 BX_RET 14, _, implicit %r0
473 ; CHECK: BX_RET 14, _, implicit %r0
402 %3(s32) = G_ZEXT %2(s1)
403 %r0 = COPY %3(s32)
404 BX_RET 14, _, implicit %r0
474405 ...
475406 ---
476407 name: test_fcmp_oeq_s32
477 # CHECK-LABEL: name: test_fcmp_oeq_s32
478 legalized: true
479 regBankSelected: true
480 selected: false
481 # CHECK: selected: true
482 registers:
483 - { id: 0, class: fprb }
484 - { id: 1, class: fprb }
485 - { id: 2, class: gprb }
486 - { id: 3, class: gprb }
487 body: |
488 bb.0:
489 liveins: %s0, %s1
490
491 %0(s32) = COPY %s0
492 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
493
494 %1(s32) = COPY %s1
495 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
496
408 legalized: true
409 regBankSelected: true
410 selected: false
411 registers:
412 - { id: 0, class: fprb }
413 - { id: 1, class: fprb }
414 - { id: 2, class: gprb }
415 - { id: 3, class: gprb }
416 body: |
417 bb.0:
418 liveins: %s0, %s1
419
420 ; CHECK-LABEL: name: test_fcmp_oeq_s32
421 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
422 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
423 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
424 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
425 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
426 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
427 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
428 ; CHECK: %r0 = COPY [[ANDri]]
429 ; CHECK: BX_RET 14, _, implicit %r0
430 %0(s32) = COPY %s0
431 %1(s32) = COPY %s1
497432 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
498 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
499 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
500 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
501 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
502
503 %3(s32) = G_ZEXT %2(s1)
504 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
505
506 %r0 = COPY %3(s32)
507 ; CHECK: %r0 = COPY [[RET]]
508
509 BX_RET 14, _, implicit %r0
510 ; CHECK: BX_RET 14, _, implicit %r0
433 %3(s32) = G_ZEXT %2(s1)
434 %r0 = COPY %3(s32)
435 BX_RET 14, _, implicit %r0
511436 ...
512437 ---
513438 name: test_fcmp_ogt_s32
514 # CHECK-LABEL: name: test_fcmp_ogt_s32
515 legalized: true
516 regBankSelected: true
517 selected: false
518 # CHECK: selected: true
519 registers:
520 - { id: 0, class: fprb }
521 - { id: 1, class: fprb }
522 - { id: 2, class: gprb }
523 - { id: 3, class: gprb }
524 body: |
525 bb.0:
526 liveins: %s0, %s1
527
528 %0(s32) = COPY %s0
529 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
530
531 %1(s32) = COPY %s1
532 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
533
439 legalized: true
440 regBankSelected: true
441 selected: false
442 registers:
443 - { id: 0, class: fprb }
444 - { id: 1, class: fprb }
445 - { id: 2, class: gprb }
446 - { id: 3, class: gprb }
447 body: |
448 bb.0:
449 liveins: %s0, %s1
450
451 ; CHECK-LABEL: name: test_fcmp_ogt_s32
452 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
453 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
454 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
455 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
456 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
457 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
458 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
459 ; CHECK: %r0 = COPY [[ANDri]]
460 ; CHECK: BX_RET 14, _, implicit %r0
461 %0(s32) = COPY %s0
462 %1(s32) = COPY %s1
534463 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
535 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
536 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
537 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
538 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
539
540 %3(s32) = G_ZEXT %2(s1)
541 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
542
543 %r0 = COPY %3(s32)
544 ; CHECK: %r0 = COPY [[RET]]
545
546 BX_RET 14, _, implicit %r0
547 ; CHECK: BX_RET 14, _, implicit %r0
464 %3(s32) = G_ZEXT %2(s1)
465 %r0 = COPY %3(s32)
466 BX_RET 14, _, implicit %r0
548467 ...
549468 ---
550469 name: test_fcmp_oge_s32
551 # CHECK-LABEL: name: test_fcmp_oge_s32
552 legalized: true
553 regBankSelected: true
554 selected: false
555 # CHECK: selected: true
556 registers:
557 - { id: 0, class: fprb }
558 - { id: 1, class: fprb }
559 - { id: 2, class: gprb }
560 - { id: 3, class: gprb }
561 body: |
562 bb.0:
563 liveins: %s0, %s1
564
565 %0(s32) = COPY %s0
566 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
567
568 %1(s32) = COPY %s1
569 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
570
470 legalized: true
471 regBankSelected: true
472 selected: false
473 registers:
474 - { id: 0, class: fprb }
475 - { id: 1, class: fprb }
476 - { id: 2, class: gprb }
477 - { id: 3, class: gprb }
478 body: |
479 bb.0:
480 liveins: %s0, %s1
481
482 ; CHECK-LABEL: name: test_fcmp_oge_s32
483 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
484 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
485 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
486 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
487 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
488 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
489 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
490 ; CHECK: %r0 = COPY [[ANDri]]
491 ; CHECK: BX_RET 14, _, implicit %r0
492 %0(s32) = COPY %s0
493 %1(s32) = COPY %s1
571494 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
572 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
573 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
574 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
575 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
576
577 %3(s32) = G_ZEXT %2(s1)
578 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
579
580 %r0 = COPY %3(s32)
581 ; CHECK: %r0 = COPY [[RET]]
582
583 BX_RET 14, _, implicit %r0
584 ; CHECK: BX_RET 14, _, implicit %r0
495 %3(s32) = G_ZEXT %2(s1)
496 %r0 = COPY %3(s32)
497 BX_RET 14, _, implicit %r0
585498 ...
586499 ---
587500 name: test_fcmp_olt_s32
588 # CHECK-LABEL: name: test_fcmp_olt_s32
589 legalized: true
590 regBankSelected: true
591 selected: false
592 # CHECK: selected: true
593 registers:
594 - { id: 0, class: fprb }
595 - { id: 1, class: fprb }
596 - { id: 2, class: gprb }
597 - { id: 3, class: gprb }
598 body: |
599 bb.0:
600 liveins: %s0, %s1
601
602 %0(s32) = COPY %s0
603 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
604
605 %1(s32) = COPY %s1
606 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
607
501 legalized: true
502 regBankSelected: true
503 selected: false
504 registers:
505 - { id: 0, class: fprb }
506 - { id: 1, class: fprb }
507 - { id: 2, class: gprb }
508 - { id: 3, class: gprb }
509 body: |
510 bb.0:
511 liveins: %s0, %s1
512
513 ; CHECK-LABEL: name: test_fcmp_olt_s32
514 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
515 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
516 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
517 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
518 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
519 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
520 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
521 ; CHECK: %r0 = COPY [[ANDri]]
522 ; CHECK: BX_RET 14, _, implicit %r0
523 %0(s32) = COPY %s0
524 %1(s32) = COPY %s1
608525 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
609 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
610 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
611 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
612 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
613
614 %3(s32) = G_ZEXT %2(s1)
615 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
616
617 %r0 = COPY %3(s32)
618 ; CHECK: %r0 = COPY [[RET]]
619
620 BX_RET 14, _, implicit %r0
621 ; CHECK: BX_RET 14, _, implicit %r0
526 %3(s32) = G_ZEXT %2(s1)
527 %r0 = COPY %3(s32)
528 BX_RET 14, _, implicit %r0
622529 ...
623530 ---
624531 name: test_fcmp_ole_s32
625 # CHECK-LABEL: name: test_fcmp_ole_s32
626 legalized: true
627 regBankSelected: true
628 selected: false
629 # CHECK: selected: true
630 registers:
631 - { id: 0, class: fprb }
632 - { id: 1, class: fprb }
633 - { id: 2, class: gprb }
634 - { id: 3, class: gprb }
635 body: |
636 bb.0:
637 liveins: %s0, %s1
638
639 %0(s32) = COPY %s0
640 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
641
642 %1(s32) = COPY %s1
643 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
644
532 legalized: true
533 regBankSelected: true
534 selected: false
535 registers:
536 - { id: 0, class: fprb }
537 - { id: 1, class: fprb }
538 - { id: 2, class: gprb }
539 - { id: 3, class: gprb }
540 body: |
541 bb.0:
542 liveins: %s0, %s1
543
544 ; CHECK-LABEL: name: test_fcmp_ole_s32
545 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
546 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
547 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
548 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
549 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
550 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
551 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
552 ; CHECK: %r0 = COPY [[ANDri]]
553 ; CHECK: BX_RET 14, _, implicit %r0
554 %0(s32) = COPY %s0
555 %1(s32) = COPY %s1
645556 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
646 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
647 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
648 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
649 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
650
651 %3(s32) = G_ZEXT %2(s1)
652 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
653
654 %r0 = COPY %3(s32)
655 ; CHECK: %r0 = COPY [[RET]]
656
657 BX_RET 14, _, implicit %r0
658 ; CHECK: BX_RET 14, _, implicit %r0
557 %3(s32) = G_ZEXT %2(s1)
558 %r0 = COPY %3(s32)
559 BX_RET 14, _, implicit %r0
659560 ...
660561 ---
661562 name: test_fcmp_ord_s32
662 # CHECK-LABEL: name: test_fcmp_ord_s32
663 legalized: true
664 regBankSelected: true
665 selected: false
666 # CHECK: selected: true
667 registers:
668 - { id: 0, class: fprb }
669 - { id: 1, class: fprb }
670 - { id: 2, class: gprb }
671 - { id: 3, class: gprb }
672 body: |
673 bb.0:
674 liveins: %s0, %s1
675
676 %0(s32) = COPY %s0
677 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
678
679 %1(s32) = COPY %s1
680 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
681
563 legalized: true
564 regBankSelected: true
565 selected: false
566 registers:
567 - { id: 0, class: fprb }
568 - { id: 1, class: fprb }
569 - { id: 2, class: gprb }
570 - { id: 3, class: gprb }
571 body: |
572 bb.0:
573 liveins: %s0, %s1
574
575 ; CHECK-LABEL: name: test_fcmp_ord_s32
576 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
577 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
578 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
579 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
580 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
581 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
582 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
583 ; CHECK: %r0 = COPY [[ANDri]]
584 ; CHECK: BX_RET 14, _, implicit %r0
585 %0(s32) = COPY %s0
586 %1(s32) = COPY %s1
682587 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
683 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
684 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
685 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
686 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
687
688 %3(s32) = G_ZEXT %2(s1)
689 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
690
691 %r0 = COPY %3(s32)
692 ; CHECK: %r0 = COPY [[RET]]
693
694 BX_RET 14, _, implicit %r0
695 ; CHECK: BX_RET 14, _, implicit %r0
588 %3(s32) = G_ZEXT %2(s1)
589 %r0 = COPY %3(s32)
590 BX_RET 14, _, implicit %r0
696591 ...
697592 ---
698593 name: test_fcmp_ugt_s32
699 # CHECK-LABEL: name: test_fcmp_ugt_s32
700 legalized: true
701 regBankSelected: true
702 selected: false
703 # CHECK: selected: true
704 registers:
705 - { id: 0, class: fprb }
706 - { id: 1, class: fprb }
707 - { id: 2, class: gprb }
708 - { id: 3, class: gprb }
709 body: |
710 bb.0:
711 liveins: %s0, %s1
712
713 %0(s32) = COPY %s0
714 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
715
716 %1(s32) = COPY %s1
717 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
718
594 legalized: true
595 regBankSelected: true
596 selected: false
597 registers:
598 - { id: 0, class: fprb }
599 - { id: 1, class: fprb }
600 - { id: 2, class: gprb }
601 - { id: 3, class: gprb }
602 body: |
603 bb.0:
604 liveins: %s0, %s1
605
606 ; CHECK-LABEL: name: test_fcmp_ugt_s32
607 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
608 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
609 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
610 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
611 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
612 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
613 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
614 ; CHECK: %r0 = COPY [[ANDri]]
615 ; CHECK: BX_RET 14, _, implicit %r0
616 %0(s32) = COPY %s0
617 %1(s32) = COPY %s1
719618 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
720 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
721 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
722 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
723 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
724
725 %3(s32) = G_ZEXT %2(s1)
726 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
727
728 %r0 = COPY %3(s32)
729 ; CHECK: %r0 = COPY [[RET]]
730
731 BX_RET 14, _, implicit %r0
732 ; CHECK: BX_RET 14, _, implicit %r0
619 %3(s32) = G_ZEXT %2(s1)
620 %r0 = COPY %3(s32)
621 BX_RET 14, _, implicit %r0
733622 ...
734623 ---
735624 name: test_fcmp_uge_s32
736 # CHECK-LABEL: name: test_fcmp_uge_s32
737 legalized: true
738 regBankSelected: true
739 selected: false
740 # CHECK: selected: true
741 registers:
742 - { id: 0, class: fprb }
743 - { id: 1, class: fprb }
744 - { id: 2, class: gprb }
745 - { id: 3, class: gprb }
746 body: |
747 bb.0:
748 liveins: %s0, %s1
749
750 %0(s32) = COPY %s0
751 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
752
753 %1(s32) = COPY %s1
754 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
755
625 legalized: true
626 regBankSelected: true
627 selected: false
628 registers:
629 - { id: 0, class: fprb }
630 - { id: 1, class: fprb }
631 - { id: 2, class: gprb }
632 - { id: 3, class: gprb }
633 body: |
634 bb.0:
635 liveins: %s0, %s1
636
637 ; CHECK-LABEL: name: test_fcmp_uge_s32
638 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
639 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
640 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
641 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
642 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
643 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
644 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
645 ; CHECK: %r0 = COPY [[ANDri]]
646 ; CHECK: BX_RET 14, _, implicit %r0
647 %0(s32) = COPY %s0
648 %1(s32) = COPY %s1
756649 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
757 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
758 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
759 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
760 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
761
762 %3(s32) = G_ZEXT %2(s1)
763 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
764
765 %r0 = COPY %3(s32)
766 ; CHECK: %r0 = COPY [[RET]]
767
768 BX_RET 14, _, implicit %r0
769 ; CHECK: BX_RET 14, _, implicit %r0
650 %3(s32) = G_ZEXT %2(s1)
651 %r0 = COPY %3(s32)
652 BX_RET 14, _, implicit %r0
770653 ...
771654 ---
772655 name: test_fcmp_ult_s32
773 # CHECK-LABEL: name: test_fcmp_ult_s32
774 legalized: true
775 regBankSelected: true
776 selected: false
777 # CHECK: selected: true
778 registers:
779 - { id: 0, class: fprb }
780 - { id: 1, class: fprb }
781 - { id: 2, class: gprb }
782 - { id: 3, class: gprb }
783 body: |
784 bb.0:
785 liveins: %s0, %s1
786
787 %0(s32) = COPY %s0
788 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
789
790 %1(s32) = COPY %s1
791 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
792
656 legalized: true
657 regBankSelected: true
658 selected: false
659 registers:
660 - { id: 0, class: fprb }
661 - { id: 1, class: fprb }
662 - { id: 2, class: gprb }
663 - { id: 3, class: gprb }
664 body: |
665 bb.0:
666 liveins: %s0, %s1
667
668 ; CHECK-LABEL: name: test_fcmp_ult_s32
669 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
670 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
671 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
672 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
673 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
674 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
675 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
676 ; CHECK: %r0 = COPY [[ANDri]]
677 ; CHECK: BX_RET 14, _, implicit %r0
678 %0(s32) = COPY %s0
679 %1(s32) = COPY %s1
793680 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
794 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
795 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
796 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
797 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
798
799 %3(s32) = G_ZEXT %2(s1)
800 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
801
802 %r0 = COPY %3(s32)
803 ; CHECK: %r0 = COPY [[RET]]
804
805 BX_RET 14, _, implicit %r0
806 ; CHECK: BX_RET 14, _, implicit %r0
681 %3(s32) = G_ZEXT %2(s1)
682 %r0 = COPY %3(s32)
683 BX_RET 14, _, implicit %r0
807684 ...
808685 ---
809686 name: test_fcmp_ule_s32
810 # CHECK-LABEL: name: test_fcmp_ule_s32
811 legalized: true
812 regBankSelected: true
813 selected: false
814 # CHECK: selected: true
815 registers:
816 - { id: 0, class: fprb }
817 - { id: 1, class: fprb }
818 - { id: 2, class: gprb }
819 - { id: 3, class: gprb }
820 body: |
821 bb.0:
822 liveins: %s0, %s1
823
824 %0(s32) = COPY %s0
825 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
826
827 %1(s32) = COPY %s1
828 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
829
687 legalized: true
688 regBankSelected: true
689 selected: false
690 registers:
691 - { id: 0, class: fprb }
692 - { id: 1, class: fprb }
693 - { id: 2, class: gprb }
694 - { id: 3, class: gprb }
695 body: |
696 bb.0:
697 liveins: %s0, %s1
698
699 ; CHECK-LABEL: name: test_fcmp_ule_s32
700 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
701 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
702 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
703 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
704 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
705 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
706 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
707 ; CHECK: %r0 = COPY [[ANDri]]
708 ; CHECK: BX_RET 14, _, implicit %r0
709 %0(s32) = COPY %s0
710 %1(s32) = COPY %s1
830711 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
831 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
832 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
833 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
834 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
835
836 %3(s32) = G_ZEXT %2(s1)
837 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
838
839 %r0 = COPY %3(s32)
840 ; CHECK: %r0 = COPY [[RET]]
841
842 BX_RET 14, _, implicit %r0
843 ; CHECK: BX_RET 14, _, implicit %r0
712 %3(s32) = G_ZEXT %2(s1)
713 %r0 = COPY %3(s32)
714 BX_RET 14, _, implicit %r0
844715 ...
845716 ---
846717 name: test_fcmp_une_s32
847 # CHECK-LABEL: name: test_fcmp_une_s32
848 legalized: true
849 regBankSelected: true
850 selected: false
851 # CHECK: selected: true
852 registers:
853 - { id: 0, class: fprb }
854 - { id: 1, class: fprb }
855 - { id: 2, class: gprb }
856 - { id: 3, class: gprb }
857 body: |
858 bb.0:
859 liveins: %s0, %s1
860
861 %0(s32) = COPY %s0
862 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
863
864 %1(s32) = COPY %s1
865 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
866
718 legalized: true
719 regBankSelected: true
720 selected: false
721 registers:
722 - { id: 0, class: fprb }
723 - { id: 1, class: fprb }
724 - { id: 2, class: gprb }
725 - { id: 3, class: gprb }
726 body: |
727 bb.0:
728 liveins: %s0, %s1
729
730 ; CHECK-LABEL: name: test_fcmp_une_s32
731 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
732 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
733 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
734 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
735 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
736 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
737 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
738 ; CHECK: %r0 = COPY [[ANDri]]
739 ; CHECK: BX_RET 14, _, implicit %r0
740 %0(s32) = COPY %s0
741 %1(s32) = COPY %s1
867742 %2(s1) = G_FCMP floatpred(une), %0(s32), %1
868 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
869 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
870 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
871 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
872
873 %3(s32) = G_ZEXT %2(s1)
874 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
875
876 %r0 = COPY %3(s32)
877 ; CHECK: %r0 = COPY [[RET]]
878
879 BX_RET 14, _, implicit %r0
880 ; CHECK: BX_RET 14, _, implicit %r0
743 %3(s32) = G_ZEXT %2(s1)
744 %r0 = COPY %3(s32)
745 BX_RET 14, _, implicit %r0
881746 ...
882747 ---
883748 name: test_fcmp_uno_s32
884 # CHECK-LABEL: name: test_fcmp_uno_s32
885 legalized: true
886 regBankSelected: true
887 selected: false
888 # CHECK: selected: true
889 registers:
890 - { id: 0, class: fprb }
891 - { id: 1, class: fprb }
892 - { id: 2, class: gprb }
893 - { id: 3, class: gprb }
894 body: |
895 bb.0:
896 liveins: %s0, %s1
897
898 %0(s32) = COPY %s0
899 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
900
901 %1(s32) = COPY %s1
902 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
903
749 legalized: true
750 regBankSelected: true
751 selected: false
752 registers:
753 - { id: 0, class: fprb }
754 - { id: 1, class: fprb }
755 - { id: 2, class: gprb }
756 - { id: 3, class: gprb }
757 body: |
758 bb.0:
759 liveins: %s0, %s1
760
761 ; CHECK-LABEL: name: test_fcmp_uno_s32
762 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
763 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
764 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
765 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
766 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
767 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
768 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
769 ; CHECK: %r0 = COPY [[ANDri]]
770 ; CHECK: BX_RET 14, _, implicit %r0
771 %0(s32) = COPY %s0
772 %1(s32) = COPY %s1
904773 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
905 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
906 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
907 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
908 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
909
910 %3(s32) = G_ZEXT %2(s1)
911 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
912
913 %r0 = COPY %3(s32)
914 ; CHECK: %r0 = COPY [[RET]]
915
916 BX_RET 14, _, implicit %r0
917 ; CHECK: BX_RET 14, _, implicit %r0
774 %3(s32) = G_ZEXT %2(s1)
775 %r0 = COPY %3(s32)
776 BX_RET 14, _, implicit %r0
918777 ...
919778 ---
920779 name: test_fcmp_one_s32
921 # CHECK-LABEL: name: test_fcmp_one_s32
922 legalized: true
923 regBankSelected: true
924 selected: false
925 # CHECK: selected: true
926 registers:
927 - { id: 0, class: fprb }
928 - { id: 1, class: fprb }
929 - { id: 2, class: gprb }
930 - { id: 3, class: gprb }
931 body: |
932 bb.0:
933 liveins: %s0, %s1
934
935 %0(s32) = COPY %s0
936 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
937
938 %1(s32) = COPY %s1
939 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
940
780 legalized: true
781 regBankSelected: true
782 selected: false
783 registers:
784 - { id: 0, class: fprb }
785 - { id: 1, class: fprb }
786 - { id: 2, class: gprb }
787 - { id: 3, class: gprb }
788 body: |
789 bb.0:
790 liveins: %s0, %s1
791
792 ; CHECK-LABEL: name: test_fcmp_one_s32
793 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
794 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
795 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
796 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
797 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
798 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
799 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
800 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
801 ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
802 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
803 ; CHECK: %r0 = COPY [[ANDri]]
804 ; CHECK: BX_RET 14, _, implicit %r0
805 %0(s32) = COPY %s0
806 %1(s32) = COPY %s1
941807 %2(s1) = G_FCMP floatpred(one), %0(s32), %1
942 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
943 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
944 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
945 ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
946 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
947 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
948 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
949
950 %3(s32) = G_ZEXT %2(s1)
951 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
952
953 %r0 = COPY %3(s32)
954 ; CHECK: %r0 = COPY [[RET]]
955
956 BX_RET 14, _, implicit %r0
957 ; CHECK: BX_RET 14, _, implicit %r0
808 %3(s32) = G_ZEXT %2(s1)
809 %r0 = COPY %3(s32)
810 BX_RET 14, _, implicit %r0
958811 ...
959812 ---
960813 name: test_fcmp_ueq_s32
961 # CHECK-LABEL: name: test_fcmp_ueq_s32
962 legalized: true
963 regBankSelected: true
964 selected: false
965 # CHECK: selected: true
966 registers:
967 - { id: 0, class: fprb }
968 - { id: 1, class: fprb }
969 - { id: 2, class: gprb }
970 - { id: 3, class: gprb }
971 body: |
972 bb.0:
973 liveins: %s0, %s1
974
975 %0(s32) = COPY %s0
976 ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
977
978 %1(s32) = COPY %s1
979 ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
980
814 legalized: true
815 regBankSelected: true
816 selected: false
817 registers:
818 - { id: 0, class: fprb }
819 - { id: 1, class: fprb }
820 - { id: 2, class: gprb }
821 - { id: 3, class: gprb }
822 body: |
823 bb.0:
824 liveins: %s0, %s1
825
826 ; CHECK-LABEL: name: test_fcmp_ueq_s32
827 ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
828 ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
829 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
830 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
831 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
832 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
833 ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
834 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
835 ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
836 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
837 ; CHECK: %r0 = COPY [[ANDri]]
838 ; CHECK: BX_RET 14, _, implicit %r0
839 %0(s32) = COPY %s0
840 %1(s32) = COPY %s1
981841 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
982 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
983 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
984 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
985 ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
986 ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
987 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
988 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
989
990 %3(s32) = G_ZEXT %2(s1)
991 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
992
993 %r0 = COPY %3(s32)
994 ; CHECK: %r0 = COPY [[RET]]
995
996 BX_RET 14, _, implicit %r0
997 ; CHECK: BX_RET 14, _, implicit %r0
842 %3(s32) = G_ZEXT %2(s1)
843 %r0 = COPY %3(s32)
844 BX_RET 14, _, implicit %r0
998845 ...
999846 ---
1000847 name: test_fcmp_true_s64
1001 # CHECK-LABEL: name: test_fcmp_true_s64
1002 legalized: true
1003 regBankSelected: true
1004 selected: false
1005 # CHECK: selected: true
1006 registers:
1007 - { id: 0, class: fprb }
1008 - { id: 1, class: fprb }
1009 - { id: 2, class: gprb }
1010 - { id: 3, class: gprb }
1011 body: |
1012 bb.0:
1013 liveins: %d0, %d1
1014
1015 %0(s64) = COPY %d0
1016 %1(s64) = COPY %d1
1017
848 legalized: true
849 regBankSelected: true
850 selected: false
851 registers:
852 - { id: 0, class: fprb }
853 - { id: 1, class: fprb }
854 - { id: 2, class: gprb }
855 - { id: 3, class: gprb }
856 body: |
857 bb.0:
858 liveins: %d0, %d1
859
860 ; CHECK-LABEL: name: test_fcmp_true_s64
861 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
862 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
863 ; CHECK: %r0 = COPY [[ANDri]]
864 ; CHECK: BX_RET 14, _, implicit %r0
865 %0(s64) = COPY %d0
866 %1(s64) = COPY %d1
1018867 %2(s1) = G_FCMP floatpred(true), %0(s64), %1
1019 ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
1020
1021 %3(s32) = G_ZEXT %2(s1)
1022 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1023
1024 %r0 = COPY %3(s32)
1025 ; CHECK: %r0 = COPY [[RET]]
1026
1027 BX_RET 14, _, implicit %r0
1028 ; CHECK: BX_RET 14, _, implicit %r0
868 %3(s32) = G_ZEXT %2(s1)
869 %r0 = COPY %3(s32)
870 BX_RET 14, _, implicit %r0
1029871 ...
1030872 ---
1031873 name: test_fcmp_false_s64
1032 # CHECK-LABEL: name: test_fcmp_false_s64
1033 legalized: true
1034 regBankSelected: true
1035 selected: false
1036 # CHECK: selected: true
1037 registers:
1038 - { id: 0, class: fprb }
1039 - { id: 1, class: fprb }
1040 - { id: 2, class: gprb }
1041 - { id: 3, class: gprb }
1042 body: |
1043 bb.0:
1044 liveins: %d0, %d1
1045
1046 %0(s64) = COPY %d0
1047 %1(s64) = COPY %d1
1048
874 legalized: true
875 regBankSelected: true
876 selected: false
877 registers:
878 - { id: 0, class: fprb }
879 - { id: 1, class: fprb }
880 - { id: 2, class: gprb }
881 - { id: 3, class: gprb }
882 body: |
883 bb.0:
884 liveins: %d0, %d1
885
886 ; CHECK-LABEL: name: test_fcmp_false_s64
887 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
888 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
889 ; CHECK: %r0 = COPY [[ANDri]]
890 ; CHECK: BX_RET 14, _, implicit %r0
891 %0(s64) = COPY %d0
892 %1(s64) = COPY %d1
1049893 %2(s1) = G_FCMP floatpred(false), %0(s64), %1
1050 ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
1051
1052 %3(s32) = G_ZEXT %2(s1)
1053 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1054
1055 %r0 = COPY %3(s32)
1056 ; CHECK: %r0 = COPY [[RET]]
1057
1058 BX_RET 14, _, implicit %r0
1059 ; CHECK: BX_RET 14, _, implicit %r0
894 %3(s32) = G_ZEXT %2(s1)
895 %r0 = COPY %3(s32)
896 BX_RET 14, _, implicit %r0
1060897 ...
1061898 ---
1062899 name: test_fcmp_oeq_s64
1063 # CHECK-LABEL: name: test_fcmp_oeq_s64
1064 legalized: true
1065 regBankSelected: true
1066 selected: false
1067 # CHECK: selected: true
1068 registers:
1069 - { id: 0, class: fprb }
1070 - { id: 1, class: fprb }
1071 - { id: 2, class: gprb }
1072 - { id: 3, class: gprb }
1073 body: |
1074 bb.0:
1075 liveins: %d0, %d1
1076
1077 %0(s64) = COPY %d0
1078 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1079
1080 %1(s64) = COPY %d1
1081 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1082
900 legalized: true
901 regBankSelected: true
902 selected: false
903 registers:
904 - { id: 0, class: fprb }
905 - { id: 1, class: fprb }
906 - { id: 2, class: gprb }
907 - { id: 3, class: gprb }
908 body: |
909 bb.0:
910 liveins: %d0, %d1
911
912 ; CHECK-LABEL: name: test_fcmp_oeq_s64
913 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
914 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
915 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
916 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
917 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
918 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
919 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
920 ; CHECK: %r0 = COPY [[ANDri]]
921 ; CHECK: BX_RET 14, _, implicit %r0
922 %0(s64) = COPY %d0
923 %1(s64) = COPY %d1
1083924 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
1084 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1085 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1086 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1087 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
1088
1089 %3(s32) = G_ZEXT %2(s1)
1090 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1091
1092 %r0 = COPY %3(s32)
1093 ; CHECK: %r0 = COPY [[RET]]
1094
1095 BX_RET 14, _, implicit %r0
1096 ; CHECK: BX_RET 14, _, implicit %r0
925 %3(s32) = G_ZEXT %2(s1)
926 %r0 = COPY %3(s32)
927 BX_RET 14, _, implicit %r0
1097928 ...
1098929 ---
1099930 name: test_fcmp_ogt_s64
1100 # CHECK-LABEL: name: test_fcmp_ogt_s64
1101 legalized: true
1102 regBankSelected: true
1103 selected: false
1104 # CHECK: selected: true
1105 registers:
1106 - { id: 0, class: fprb }
1107 - { id: 1, class: fprb }
1108 - { id: 2, class: gprb }
1109 - { id: 3, class: gprb }
1110 body: |
1111 bb.0:
1112 liveins: %d0, %d1
1113
1114 %0(s64) = COPY %d0
1115 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1116
1117 %1(s64) = COPY %d1
1118 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1119
931 legalized: true
932 regBankSelected: true
933 selected: false
934 registers:
935 - { id: 0, class: fprb }
936 - { id: 1, class: fprb }
937 - { id: 2, class: gprb }
938 - { id: 3, class: gprb }
939 body: |
940 bb.0:
941 liveins: %d0, %d1
942
943 ; CHECK-LABEL: name: test_fcmp_ogt_s64
944 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
945 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
946 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
947 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
948 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
949 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
950 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
951 ; CHECK: %r0 = COPY [[ANDri]]
952 ; CHECK: BX_RET 14, _, implicit %r0
953 %0(s64) = COPY %d0
954 %1(s64) = COPY %d1
1120955 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
1121 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1122 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1123 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1124 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
1125
1126 %3(s32) = G_ZEXT %2(s1)
1127 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1128
1129 %r0 = COPY %3(s32)
1130 ; CHECK: %r0 = COPY [[RET]]
1131
1132 BX_RET 14, _, implicit %r0
1133 ; CHECK: BX_RET 14, _, implicit %r0
956 %3(s32) = G_ZEXT %2(s1)
957 %r0 = COPY %3(s32)
958 BX_RET 14, _, implicit %r0
1134959 ...
1135960 ---
1136961 name: test_fcmp_oge_s64
1137 # CHECK-LABEL: name: test_fcmp_oge_s64
1138 legalized: true
1139 regBankSelected: true
1140 selected: false
1141 # CHECK: selected: true
1142 registers:
1143 - { id: 0, class: fprb }
1144 - { id: 1, class: fprb }
1145 - { id: 2, class: gprb }
1146 - { id: 3, class: gprb }
1147 body: |
1148 bb.0:
1149 liveins: %d0, %d1
1150
1151 %0(s64) = COPY %d0
1152 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1153
1154 %1(s64) = COPY %d1
1155 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1156
962 legalized: true
963 regBankSelected: true
964 selected: false
965 registers:
966 - { id: 0, class: fprb }
967 - { id: 1, class: fprb }
968 - { id: 2, class: gprb }
969 - { id: 3, class: gprb }
970 body: |
971 bb.0:
972 liveins: %d0, %d1
973
974 ; CHECK-LABEL: name: test_fcmp_oge_s64
975 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
976 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
977 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
978 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
979 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
980 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
981 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
982 ; CHECK: %r0 = COPY [[ANDri]]
983 ; CHECK: BX_RET 14, _, implicit %r0
984 %0(s64) = COPY %d0
985 %1(s64) = COPY %d1
1157986 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1
1158 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1159 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1160 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1161 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
1162
1163 %3(s32) = G_ZEXT %2(s1)
1164 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1165
1166 %r0 = COPY %3(s32)
1167 ; CHECK: %r0 = COPY [[RET]]
1168
1169 BX_RET 14, _, implicit %r0
1170 ; CHECK: BX_RET 14, _, implicit %r0
987 %3(s32) = G_ZEXT %2(s1)
988 %r0 = COPY %3(s32)
989 BX_RET 14, _, implicit %r0
1171990 ...
1172991 ---
1173992 name: test_fcmp_olt_s64
1174 # CHECK-LABEL: name: test_fcmp_olt_s64
1175 legalized: true
1176 regBankSelected: true
1177 selected: false
1178 # CHECK: selected: true
1179 registers:
1180 - { id: 0, class: fprb }
1181 - { id: 1, class: fprb }
1182 - { id: 2, class: gprb }
1183 - { id: 3, class: gprb }
1184 body: |
1185 bb.0:
1186 liveins: %d0, %d1
1187
1188 %0(s64) = COPY %d0
1189 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1190
1191 %1(s64) = COPY %d1
1192 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1193
993 legalized: true
994 regBankSelected: true
995 selected: false
996 registers:
997 - { id: 0, class: fprb }
998 - { id: 1, class: fprb }
999 - { id: 2, class: gprb }
1000 - { id: 3, class: gprb }
1001 body: |
1002 bb.0:
1003 liveins: %d0, %d1
1004
1005 ; CHECK-LABEL: name: test_fcmp_olt_s64
1006 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
1007 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
1008 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
1009 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1010 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1011 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
1012 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
1013 ; CHECK: %r0 = COPY [[ANDri]]
1014 ; CHECK: BX_RET 14, _, implicit %r0
1015 %0(s64) = COPY %d0
1016 %1(s64) = COPY %d1
11941017 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1
1195 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1196 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1197 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1198 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
1199
1200 %3(s32) = G_ZEXT %2(s1)
1201 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1202
1203 %r0 = COPY %3(s32)
1204 ; CHECK: %r0 = COPY [[RET]]
1205
1206 BX_RET 14, _, implicit %r0
1207 ; CHECK: BX_RET 14, _, implicit %r0
1018 %3(s32) = G_ZEXT %2(s1)
1019 %r0 = COPY %3(s32)
1020 BX_RET 14, _, implicit %r0
12081021 ...
12091022 ---
12101023 name: test_fcmp_ole_s64
1211 # CHECK-LABEL: name: test_fcmp_ole_s64
1212 legalized: true
1213 regBankSelected: true
1214 selected: false
1215 # CHECK: selected: true
1216 registers:
1217 - { id: 0, class: fprb }
1218 - { id: 1, class: fprb }
1219 - { id: 2, class: gprb }
1220 - { id: 3, class: gprb }
1221 body: |
1222 bb.0:
1223 liveins: %d0, %d1
1224
1225 %0(s64) = COPY %d0
1226 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1227
1228 %1(s64) = COPY %d1
1229 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1230
1024 legalized: true
1025 regBankSelected: true
1026 selected: false
1027 registers:
1028 - { id: 0, class: fprb }
1029 - { id: 1, class: fprb }
1030 - { id: 2, class: gprb }
1031 - { id: 3, class: gprb }
1032 body: |
1033 bb.0:
1034 liveins: %d0, %d1
1035
1036 ; CHECK-LABEL: name: test_fcmp_ole_s64
1037 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
1038 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
1039 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
1040 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1041 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1042 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
1043 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
1044 ; CHECK: %r0 = COPY [[ANDri]]
1045 ; CHECK: BX_RET 14, _, implicit %r0
1046 %0(s64) = COPY %d0
1047 %1(s64) = COPY %d1
12311048 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1
1232 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1233 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1234 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1235 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
1236
1237 %3(s32) = G_ZEXT %2(s1)
1238 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1239
1240 %r0 = COPY %3(s32)
1241 ; CHECK: %r0 = COPY [[RET]]
1242
1243 BX_RET 14, _, implicit %r0
1244 ; CHECK: BX_RET 14, _, implicit %r0
1049 %3(s32) = G_ZEXT %2(s1)
1050 %r0 = COPY %3(s32)
1051 BX_RET 14, _, implicit %r0
12451052 ...
12461053 ---
12471054 name: test_fcmp_ord_s64
1248 # CHECK-LABEL: name: test_fcmp_ord_s64
1249 legalized: true
1250 regBankSelected: true
1251 selected: false
1252 # CHECK: selected: true
1253 registers:
1254 - { id: 0, class: fprb }
1255 - { id: 1, class: fprb }
1256 - { id: 2, class: gprb }
1257 - { id: 3, class: gprb }
1258 body: |
1259 bb.0:
1260 liveins: %d0, %d1
1261
1262 %0(s64) = COPY %d0
1263 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1264
1265 %1(s64) = COPY %d1
1266 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1267
1055 legalized: true
1056 regBankSelected: true
1057 selected: false
1058 registers:
1059 - { id: 0, class: fprb }
1060 - { id: 1, class: fprb }
1061 - { id: 2, class: gprb }
1062 - { id: 3, class: gprb }
1063 body: |
1064 bb.0:
1065 liveins: %d0, %d1
1066
1067 ; CHECK-LABEL: name: test_fcmp_ord_s64
1068 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
1069 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
1070 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
1071 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1072 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1073 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
1074 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
1075 ; CHECK: %r0 = COPY [[ANDri]]
1076 ; CHECK: BX_RET 14, _, implicit %r0
1077 %0(s64) = COPY %d0
1078 %1(s64) = COPY %d1
12681079 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1
1269 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1270 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1271 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1272 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
1273
1274 %3(s32) = G_ZEXT %2(s1)
1275 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1276
1277 %r0 = COPY %3(s32)
1278 ; CHECK: %r0 = COPY [[RET]]
1279
1280 BX_RET 14, _, implicit %r0
1281 ; CHECK: BX_RET 14, _, implicit %r0
1080 %3(s32) = G_ZEXT %2(s1)
1081 %r0 = COPY %3(s32)
1082 BX_RET 14, _, implicit %r0
12821083 ...
12831084 ---
12841085 name: test_fcmp_ugt_s64
1285 # CHECK-LABEL: name: test_fcmp_ugt_s64
1286 legalized: true
1287 regBankSelected: true
1288 selected: false
1289 # CHECK: selected: true
1290 registers:
1291 - { id: 0, class: fprb }
1292 - { id: 1, class: fprb }
1293 - { id: 2, class: gprb }
1294 - { id: 3, class: gprb }
1295 body: |
1296 bb.0:
1297 liveins: %d0, %d1
1298
1299 %0(s64) = COPY %d0
1300 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1301
1302 %1(s64) = COPY %d1
1303 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1304
1086 legalized: true
1087 regBankSelected: true
1088 selected: false
1089 registers:
1090 - { id: 0, class: fprb }
1091 - { id: 1, class: fprb }
1092 - { id: 2, class: gprb }
1093 - { id: 3, class: gprb }
1094 body: |
1095 bb.0:
1096 liveins: %d0, %d1
1097
1098 ; CHECK-LABEL: name: test_fcmp_ugt_s64
1099 ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
1100 ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
1101 ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
1102 ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
1103 ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1104 ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
1105 ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
1106 ; CHECK: %r0 = COPY [[ANDri]]
1107 ; CHECK: BX_RET 14, _, implicit %r0
1108 %0(s64) = COPY %d0
1109 %1(s64) = COPY %d1
13051110 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
1306 ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
1307 ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
1308 ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
1309 ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
1310
1311 %3(s32) = G_ZEXT %2(s1)
1312 ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
1313
1314 %r0 = COPY %3(s32)
1315 ; CHECK: %r0 = COPY [[RET]]
1316
1317 BX_RET 14, _, implicit %r0
1318 ; CHECK: BX_RET 14, _, implicit %r0
1111 %3(s32) = G_ZEXT %2(s1)
1112 %r0 = COPY %3(s32)
1113 BX_RET 14, _, implicit %r0
13191114 ...
13201115 ---
13211116 name: test_fcmp_uge_s64
1322 # CHECK-LABEL: name: test_fcmp_uge_s64
1323 legalized: true
1324 regBankSelected: true
1325 selected: false
1326 # CHECK: selected: true
1327 registers:
1328 - { id: 0, class: fprb }
1329 - { id: 1, class: fprb }
1330 - { id: 2, class: gprb }
1331 - { id: 3, class: gprb }
1332 body: |
1333 bb.0:
1334 liveins: %d0, %d1
1335
1336 %0(s64) = COPY %d0
1337 ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
1338
1339 %1(s64) = COPY %d1
1340 ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
1341
1117 legalized: true
1118 regBankSelected: true
1119 selected: false
1120 registers:
1121 - { id: 0, class: fprb }
1122 - { id: 1, class: fprb }
1123 - { id: 2, class: gprb }
1124 - { id: 3, class: gprb }
1125 body: |
1126 bb.0:
1127<