llvm.org GIT mirror llvm / b8e9ac8
Emit cross regclass register moves for thumb2. Minor code duplication cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 11 years ago
7 changed file(s) with 75 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
2828 static cl::opt
2929 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
3030 cl::desc("Enable ARM 2-addr to 3-addr conv"));
31
32 static inline
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
35 }
36
37 static inline
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
39 return MIB.addReg(0);
40 }
4131
4232 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
4333 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
1313 #ifndef ARMBASEINSTRUCTIONINFO_H
1414 #define ARMBASEINSTRUCTIONINFO_H
1515
16 #include "ARM.h"
17 #include "ARMRegisterInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
1619 #include "llvm/Target/TargetInstrInfo.h"
17 #include "ARMRegisterInfo.h"
18 #include "ARM.h"
1920
2021 namespace llvm {
2122 class ARMSubtarget;
186187 };
187188 }
188189
190 static inline
191 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
192 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
193 }
194
195 static inline
196 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
197 return MIB.addReg(0);
198 }
199
189200 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
190201 protected:
191202 // Can be only subclassed.
2020 #include "Thumb1InstrInfo.h"
2121
2222 using namespace llvm;
23
24 static inline
25 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
26 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
27 }
2823
2924 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
3025 : ARMBaseInstrInfo(STI), RI(*this, STI) {
4444 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
4545 const ARMSubtarget &sti)
4646 : ARMBaseRegisterInfo(tii, sti) {
47 }
48
49 static inline
50 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
51 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
52 }
53
54 static inline
55 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
56 return MIB.addReg(ARM::CPSR);
5747 }
5848
5949 /// emitLoadConstPool - Emits a load from constpool to materialize the
8686
8787 return false;
8888 }
89
90 bool
91 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I,
93 unsigned DestReg, unsigned SrcReg,
94 const TargetRegisterClass *DestRC,
95 const TargetRegisterClass *SrcRC) const {
96 DebugLoc DL = DebugLoc::getUnknownLoc();
97 if (I != MBB.end()) DL = I->getDebugLoc();
98
99 if ((DestRC == ARM::GPRRegisterClass &&
100 SrcRC == ARM::tGPRRegisterClass) ||
101 (DestRC == ARM::tGPRRegisterClass &&
102 SrcRC == ARM::GPRRegisterClass)) {
103 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
104 DestReg).addReg(SrcReg)));
105 return true;
106 }
107
108 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
109 }
3636 // Return true if the block does not fall through.
3737 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
3838
39 bool copyRegToReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator I,
41 unsigned DestReg, unsigned SrcReg,
42 const TargetRegisterClass *DestRC,
43 const TargetRegisterClass *SrcRC) const;
44
3945 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
4046 /// such, whenever a client has an instance of instruction info, it should
4147 /// always be able to get register info as well (through this method).
0 ; RUN: llvm-as < %s | llc
1
2 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
3 target triple = "thumbv6t2-elf"
4 %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }>
5
6 declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind
7
8 define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind {
9 entry:
10 br i1 undef, label %bb1, label %bb13
11
12 bb1: ; preds = %entry
13 %tmp38 = add i32 undef, 10 ; [#uses=1]
14 br label %bb.i
15
16 bb.i: ; preds = %bb.i, %bb1
17 %indvar.i = phi i32 [ 0, %bb1 ], [ %2, %bb.i ] ; [#uses=3]
18 %tmp39 = add i32 %indvar.i, %tmp38 ; [#uses=1]
19 %p_addr.0.i = getelementptr i8* undef, i32 %tmp39 ; [#uses=1]
20 %0 = load i8* %p_addr.0.i, align 1 ; [#uses=1]
21 %1 = icmp slt i8 %0, 0 ; [#uses=1]
22 %2 = add i32 %indvar.i, 1 ; [#uses=1]
23 br i1 %1, label %bb.i, label %read_uleb128.exit
24
25 read_uleb128.exit: ; preds = %bb.i
26 %.sum40 = add i32 %indvar.i, undef ; [#uses=1]
27 %.sum31 = add i32 %.sum40, 2 ; [#uses=1]
28 %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31 ; [#uses=1]
29 %3 = call arm_apcscc i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; [#uses=0]
30 unreachable
31
32 bb13: ; preds = %entry
33 ret i32 0
34 }