llvm.org GIT mirror llvm / b8cab92
Fix command-line option printing to print two spaces where needed, instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
26 changed file(s) with 43 addition(s) and 43 deletion(s). Raw diff Collapse all Expand all
5252 STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
5353
5454 static RegisterRegAlloc
55 bigBlockRegAlloc("bigblock", " Big-block register allocator",
55 bigBlockRegAlloc("bigblock", "Big-block register allocator",
5656 createBigBlockRegisterAllocator);
5757
5858 namespace {
4949 cl::init(false), cl::Hidden);
5050
5151 static RegisterRegAlloc
52 linearscanRegAlloc("linearscan", " linear scan register allocator",
52 linearscanRegAlloc("linearscan", "linear scan register allocator",
5353 createLinearScanRegisterAllocator);
5454
5555 namespace {
3636 STATISTIC(NumLoads , "Number of loads added");
3737
3838 static RegisterRegAlloc
39 localRegAlloc("local", " local register allocator",
39 localRegAlloc("local", "local register allocator",
4040 createLocalRegisterAllocator);
4141
4242 namespace {
5959 using namespace llvm;
6060
6161 static RegisterRegAlloc
62 registerPBQPRepAlloc("pbqp", " PBQP register allocator",
62 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
6363 createPBQPRegisterAllocator);
6464
6565
3434
3535 namespace {
3636 static RegisterRegAlloc
37 simpleRegAlloc("simple", " simple register allocator",
37 simpleRegAlloc("simple", "simple register allocator",
3838 createSimpleRegisterAllocator);
3939
4040 class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
3030 STATISTIC(NumCCCopies, "Number of cross class copies");
3131
3232 static RegisterScheduler
33 fastDAGScheduler("fast", " Fast suboptimal list scheduling",
33 fastDAGScheduler("fast", "Fast suboptimal list scheduling",
3434 createFastDAGScheduler);
3535
3636 namespace {
3636 STATISTIC(NumStalls, "Number of pipeline stalls");
3737
3838 static RegisterScheduler
39 tdListDAGScheduler("list-td", " Top-down list scheduler",
39 tdListDAGScheduler("list-td", "Top-down list scheduler",
4040 createTDListDAGScheduler);
4141
4242 namespace {
4040
4141 static RegisterScheduler
4242 burrListDAGScheduler("list-burr",
43 " Bottom-up register reduction list scheduling",
43 "Bottom-up register reduction list scheduling",
4444 createBURRListDAGScheduler);
4545 static RegisterScheduler
4646 tdrListrDAGScheduler("list-tdrr",
47 " Top-down register reduction list scheduling",
47 "Top-down register reduction list scheduling",
4848 createTDRRListDAGScheduler);
4949
5050 namespace {
118118 " allocation):"));
119119
120120 static RegisterScheduler
121 defaultListDAGScheduler("default", " Best scheduler for the target",
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122122 createDefaultScheduler);
123123
124124 namespace llvm {
5555 SpillerOpt("spiller",
5656 cl::desc("Spiller to use: (default: local)"),
5757 cl::Prefix,
58 cl::values(clEnumVal(simple, " simple spiller"),
59 clEnumVal(local, " local spiller"),
58 cl::values(clEnumVal(simple, "simple spiller"),
59 clEnumVal(local, "local spiller"),
6060 clEnumValEnd),
6161 cl::init(local));
6262
952952 for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
953953 size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8;
954954 cout << " =" << getOption(i) << std::string(NumSpaces, ' ')
955 << " - " << getDescription(i) << "\n";
955 << " - " << getDescription(i) << "\n";
956956 }
957957 } else {
958958 if (O.HelpStr[0])
2828 cl::desc("Disable if-conversion pass"));
2929
3030 // Register the target.
31 static RegisterTarget X("arm", " ARM");
32 static RegisterTarget<ThumbTargetMachine> Y("thumb", " Thumb");
31 static RegisterTarget<ARMTargetMachine> X("arm", "ARM");
32 static RegisterTarget Y("thumb", "Thumb");
3333
3434 // No assembler printer by default
3535 ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;
2121 using namespace llvm;
2222
2323 // Register the targets
24 static RegisterTarget X("alpha", " Alpha (incomplete)");
24 static RegisterTarget X("alpha", "Alpha (incomplete)");
2525
2626 const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
2727 return new AlphaTargetAsmInfo(*this);
4848 using namespace llvm;
4949
5050 // Register the target.
51 static RegisterTarget X("c", " C backend");
51 static RegisterTarget X("c", "C backend");
5252
5353 namespace {
5454 /// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for
2323 namespace {
2424 // Register the targets
2525 RegisterTarget
26 CELLSPU("cellspu", " STI CBEA Cell SPU");
26 CELLSPU("cellspu", "STI CBEA Cell SPU");
2727 }
2828
2929 const std::pair *
7171 cl::init("!bad!"));
7272
7373 // Register the target.
74 static RegisterTarget X("cpp", " C++ backend");
74 static RegisterTarget X("cpp", "C++ backend");
7575
7676 namespace {
7777 typedef std::vector TypeList;
2525 extern "C" int IA64TargetMachineModule;
2626 int IA64TargetMachineModule = 0;
2727
28 static RegisterTarget X("ia64", " IA-64 (Itanium)");
28 static RegisterTarget X("ia64", "IA-64 (Itanium)");
2929
3030 const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
3131 return new IA64TargetAsmInfo(*this);
4444 }
4545
4646
47 static RegisterTarget X("msil", " MSIL backend");
47 static RegisterTarget X("msil", "MSIL backend");
4848
4949 bool MSILModule::runOnModule(Module &M) {
5050 ModulePtr = &M;
1919 using namespace llvm;
2020
2121 // Register the target.
22 static RegisterTarget X("mips", " Mips");
23 static RegisterTargetelTargetMachine> Y("mipsel", " Mipsel");
22 static RegisterTargetTargetMachine> X("mips", "Mips");
23 static RegisterTarget Y("mipsel", "Mipsel");
2424
2525 const TargetAsmInfo *MipsTargetMachine::
2626 createTargetAsmInfo() const
2222
2323 namespace {
2424 // Register the targets
25 RegisterTarget X("pic16", " PIC16 14-bit");
25 RegisterTarget X("pic16", "PIC16 14-bit");
2626 }
2727
2828 PIC16TargetMachine::
2222
2323 // Register the targets
2424 static RegisterTarget
25 X("ppc32", " PowerPC 32");
25 X("ppc32", "PowerPC 32");
2626 static RegisterTarget
27 Y("ppc64", " PowerPC 64");
27 Y("ppc64", "PowerPC 64");
2828
2929 // No assembler printer by default
3030 PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
1818 using namespace llvm;
1919
2020 // Register the target.
21 static RegisterTarget X("sparc", " SPARC");
21 static RegisterTarget X("sparc", "SPARC");
2222
2323 const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
2424 // FIXME: Handle Solaris subtarget someday :)
101101 cl::init(Reloc::Default),
102102 cl::values(
103103 clEnumValN(Reloc::Default, "default",
104 " Target default relocation model"),
104 "Target default relocation model"),
105105 clEnumValN(Reloc::Static, "static",
106 " Non-relocatable code"),
106 "Non-relocatable code"),
107107 clEnumValN(Reloc::PIC_, "pic",
108 " Fully relocatable, position independent code"),
108 "Fully relocatable, position independent code"),
109109 clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
110 " Relocatable external references, non-relocatable code"),
110 "Relocatable external references, non-relocatable code"),
111111 clEnumValEnd));
112112 static cl::opt
113113 DefCodeModel(
117117 cl::init(CodeModel::Default),
118118 cl::values(
119119 clEnumValN(CodeModel::Default, "default",
120 " Target default code model"),
120 "Target default code model"),
121121 clEnumValN(CodeModel::Small, "small",
122 " Small code model"),
122 "Small code model"),
123123 clEnumValN(CodeModel::Kernel, "kernel",
124 " Kernel code model"),
124 "Kernel code model"),
125125 clEnumValN(CodeModel::Medium, "medium",
126 " Medium code model"),
126 "Medium code model"),
127127 clEnumValN(CodeModel::Large, "large",
128 " Large code model"),
128 "Large code model"),
129129 clEnumValEnd));
130130
131131 static cl::opt
2222 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
2323 cl::desc("Choose style of code to emit from X86 backend:"),
2424 cl::values(
25 clEnumValN(X86Subtarget::ATT, "att", " Emit AT&T-style assembly"),
26 clEnumValN(X86Subtarget::Intel, "intel", " Emit Intel-style assembly"),
25 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
26 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
2727 clEnumValEnd));
2828
2929
3131
3232 // Register the target.
3333 static RegisterTarget
34 X("x86", " 32-bit X86: Pentium-Pro and above");
34 X("x86", "32-bit X86: Pentium-Pro and above");
3535 static RegisterTarget
36 Y("x86-64", " 64-bit X86: EM64T and AMD64");
36 Y("x86-64", "64-bit X86: EM64T and AMD64");
3737
3838 // No assembler printer by default
3939 X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;
7979 cl::desc("Choose a file type (not all types are supported by all targets):"),
8080 cl::values(
8181 clEnumValN(TargetMachine::AssemblyFile, "asm",
82 " Emit an assembly ('.s') file"),
82 "Emit an assembly ('.s') file"),
8383 clEnumValN(TargetMachine::ObjectFile, "obj",
84 " Emit a native object ('.o') file [experimental]"),
84 "Emit a native object ('.o') file [experimental]"),
8585 clEnumValN(TargetMachine::DynamicLibrary, "dynlib",
86 " Emit a native dynamic library ('.so') file"
86 "Emit a native dynamic library ('.so') file"
8787 " [experimental]"),
8888 clEnumValEnd));
8989