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[NFC] Revisited tests for D64285 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365815 91177308-0d34-0410-b5e6-96231b3b80d8 David Bolvansky 2 months ago
2 changed file(s) with 202 addition(s) and 462 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
11 ; RUN: opt < %s -instcombine -S | FileCheck %s
22
3 define i32 @ashr_lshr(i32 %x, i32 %y) {
4 ; CHECK-LABEL: @ashr_lshr(
3 define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
4 ; CHECK-LABEL: @ashr_lshr_exact_ashr_only(
55 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
66 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
77 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
1111 %cmp = icmp sgt i32 %x, -1
1212 %l = lshr i32 %x, %y
1313 %r = ashr exact i32 %x, %y
14 %ret = select i1 %cmp, i32 %l, i32 %r
15 ret i32 %ret
16 }
17
18 define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
19 ; CHECK-LABEL: @ashr_lshr_no_exact(
20 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
21 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
22 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
23 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
24 ; CHECK-NEXT: ret i32 [[RET]]
25 ;
26 %cmp = icmp sgt i32 %x, -1
27 %l = lshr i32 %x, %y
28 %r = ashr i32 %x, %y
29 %ret = select i1 %cmp, i32 %l, i32 %r
30 ret i32 %ret
31 }
32
33 define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
34 ; CHECK-LABEL: @ashr_lshr_exact_both(
35 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
36 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
37 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
38 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
39 ; CHECK-NEXT: ret i32 [[RET]]
40 ;
41 %cmp = icmp sgt i32 %x, -1
42 %l = lshr exact i32 %x, %y
43 %r = ashr exact i32 %x, %y
44 %ret = select i1 %cmp, i32 %l, i32 %r
45 ret i32 %ret
46 }
47
48 define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
49 ; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
50 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
51 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
52 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
53 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
54 ; CHECK-NEXT: ret i32 [[RET]]
55 ;
56 %cmp = icmp sgt i32 %x, -1
57 %l = lshr exact i32 %x, %y
58 %r = ashr i32 %x, %y
1459 %ret = select i1 %cmp, i32 %l, i32 %r
1560 ret i32 %ret
1661 }
3075 ret i32 %ret
3176 }
3277
33 define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
34 ; CHECK-LABEL: @ashr_lshr_vec(
78 define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
79 ; CHECK-LABEL: @ashr_lshr_splat_vec(
3580 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
3681 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
37 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
82 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
3883 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
3984 ; CHECK-NEXT: ret <2 x i32> [[RET]]
4085 ;
4186 %cmp = icmp sgt <2 x i32> %x,
87 %l = lshr <2 x i32> %x, %y
88 %r = ashr <2 x i32> %x, %y
89 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
90 ret <2 x i32> %ret
91 }
92
93 define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
94 ; CHECK-LABEL: @ashr_lshr_splat_vec2(
95 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
96 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
97 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
98 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
99 ; CHECK-NEXT: ret <2 x i32> [[RET]]
100 ;
101 %cmp = icmp sgt <2 x i32> %x,
102 %l = lshr exact <2 x i32> %x, %y
103 %r = ashr exact <2 x i32> %x, %y
104 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
105 ret <2 x i32> %ret
106 }
107
108 define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
109 ; CHECK-LABEL: @ashr_lshr_splat_vec3(
110 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
111 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
112 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
113 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
114 ; CHECK-NEXT: ret <2 x i32> [[RET]]
115 ;
116 %cmp = icmp sgt <2 x i32> %x,
117 %l = lshr exact <2 x i32> %x, %y
118 %r = ashr <2 x i32> %x, %y
119 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
120 ret <2 x i32> %ret
121 }
122
123 define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
124 ; CHECK-LABEL: @ashr_lshr_splat_vec4(
125 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
126 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
127 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
128 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
129 ; CHECK-NEXT: ret <2 x i32> [[RET]]
130 ;
131 %cmp = icmp sgt <2 x i32> %x,
132 %l = lshr <2 x i32> %x, %y
133 %r = ashr exact <2 x i32> %x, %y
134 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
135 ret <2 x i32> %ret
136 }
137
138 define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
139 ; CHECK-LABEL: @ashr_lshr_nonsplat_vec(
140 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
141 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
142 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
143 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
144 ; CHECK-NEXT: ret <2 x i32> [[RET]]
145 ;
146 %cmp = icmp sgt <2 x i32> %x,
147 %l = lshr <2 x i32> %x, %y
148 %r = ashr <2 x i32> %x, %y
149 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
150 ret <2 x i32> %ret
151 }
152
153 define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
154 ; CHECK-LABEL: @ashr_lshr_nonsplat_vec2(
155 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
156 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
157 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
158 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
159 ; CHECK-NEXT: ret <2 x i32> [[RET]]
160 ;
161 %cmp = icmp sgt <2 x i32> %x,
162 %l = lshr exact <2 x i32> %x, %y
163 %r = ashr exact <2 x i32> %x, %y
164 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
165 ret <2 x i32> %ret
166 }
167
168 define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
169 ; CHECK-LABEL: @ashr_lshr_nonsplat_vec3(
170 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
171 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
172 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
173 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
174 ; CHECK-NEXT: ret <2 x i32> [[RET]]
175 ;
176 %cmp = icmp sgt <2 x i32> %x,
177 %l = lshr exact <2 x i32> %x, %y
178 %r = ashr <2 x i32> %x, %y
179 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
180 ret <2 x i32> %ret
181 }
182
183 define <2 x i32> @ashr_lshr_nonsplat_vec4(<2 x i32> %x, <2 x i32> %y) {
184 ; CHECK-LABEL: @ashr_lshr_nonsplat_vec4(
185 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
186 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
187 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
188 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
189 ; CHECK-NEXT: ret <2 x i32> [[RET]]
190 ;
191 %cmp = icmp sgt <2 x i32> %x,
42192 %l = lshr <2 x i32> %x, %y
43193 %r = ashr exact <2 x i32> %x, %y
44194 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
105255 ret i32 %ret
106256 }
107257
108 define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
109 ; CHECK-LABEL: @ashr_lshr_inv_vec(
258 define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
259 ; CHECK-LABEL: @ashr_lshr_inv_splat_vec(
110260 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
111261 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
112262 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
115265 ;
116266 %cmp = icmp slt <2 x i32> %x,
117267 %l = lshr <2 x i32> %x, %y
268 %r = ashr exact <2 x i32> %x, %y
269 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
270 ret <2 x i32> %ret
271 }
272
273 define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
274 ; CHECK-LABEL: @ashr_lshr_inv_nonsplat_vec(
275 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
276 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
277 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
278 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
279 ; CHECK-NEXT: ret <2 x i32> [[RET]]
280 ;
281 %cmp = icmp slt <2 x i32> %x,
282 %l = lshr <2 x i32> %x, %y
283 %r = ashr exact <2 x i32> %x, %y
284 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
285 ret <2 x i32> %ret
286 }
287
288 define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
289 ; CHECK-LABEL: @ashr_lshr_vec_undef(
290 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
291 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
292 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
293 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
294 ; CHECK-NEXT: ret <2 x i32> [[RET]]
295 ;
296 %cmp = icmp sgt <2 x i32> %x,
297 %l = lshr <2 x i32> %x, %y
298 %r = ashr exact <2 x i32> %x, %y
299 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
300 ret <2 x i32> %ret
301 }
302
303 define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
304 ; CHECK-LABEL: @ashr_lshr_vec_undef2(
305 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
306 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
307 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
308 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
309 ; CHECK-NEXT: ret <2 x i32> [[RET]]
310 ;
311 %cmp = icmp slt <2 x i32> %x,
312 %l = lshr exact <2 x i32> %x, %y
118313 %r = ashr exact <2 x i32> %x, %y
119314 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
120315 ret <2 x i32> %ret
301496 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
302497 ret <2 x i32> %ret
303498 }
304
305 define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
306 ; CHECK-LABEL: @ashr_lshr_no_exact(
307 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
308 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
309 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
310 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
311 ; CHECK-NEXT: ret i32 [[RET]]
312 ;
313 %cmp = icmp sgt i32 %x, -1
314 %l = lshr i32 %x, %y
315 %r = ashr i32 %x, %y
316 %ret = select i1 %cmp, i32 %l, i32 %r
317 ret i32 %ret
318 }
319
320
321 define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
322 ; CHECK-LABEL: @ashr_lshr_exact_both(
323 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
324 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
325 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
326 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
327 ; CHECK-NEXT: ret i32 [[RET]]
328 ;
329 %cmp = icmp sgt i32 %x, -1
330 %l = lshr exact i32 %x, %y
331 %r = ashr exact i32 %x, %y
332 %ret = select i1 %cmp, i32 %l, i32 %r
333 ret i32 %ret
334 }
335
336 define i32 @ashr_lshr_exact_mismatch2(i32 %x, i32 %y) {
337 ; CHECK-LABEL: @ashr_lshr_exact_mismatch2(
338 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
339 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
340 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
341 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
342 ; CHECK-NEXT: ret i32 [[RET]]
343 ;
344 %cmp = icmp sgt i32 %x, -1
345 %l = lshr exact i32 %x, %y
346 %r = ashr i32 %x, %y
347 %ret = select i1 %cmp, i32 %l, i32 %r
348 ret i32 %ret
349 }
350
351 define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
352 ; CHECK-LABEL: @ashr_lshr_vec_undef(
353 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
354 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
355 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
356 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
357 ; CHECK-NEXT: ret <2 x i32> [[RET]]
358 ;
359 %cmp = icmp sgt <2 x i32> %x,
360 %l = lshr <2 x i32> %x, %y
361 %r = ashr exact <2 x i32> %x, %y
362 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
363 ret <2 x i32> %ret
364 }
365
366 define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
367 ; CHECK-LABEL: @ashr_lshr_vec_undef2(
368 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
369 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
370 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
371 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
372 ; CHECK-NEXT: ret <2 x i32> [[RET]]
373 ;
374 %cmp = icmp slt <2 x i32> %x,
375 %l = lshr <2 x i32> %x, %y
376 %r = ashr exact <2 x i32> %x, %y
377 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
378 ret <2 x i32> %ret
379 }
+0
-379
test/Transforms/InstSimplify/ashr-lshr.ll less more
None ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instsimplify -S | FileCheck %s
2
3 define i32 @ashr_lshr(i32 %x, i32 %y) {
4 ; CHECK-LABEL: @ashr_lshr(
5 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
6 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
7 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
8 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
9 ; CHECK-NEXT: ret i32 [[RET]]
10 ;
11 %cmp = icmp sgt i32 %x, -1
12 %l = lshr i32 %x, %y
13 %r = ashr i32 %x, %y
14 %ret = select i1 %cmp, i32 %l, i32 %r
15 ret i32 %ret
16 }
17
18 define i32 @ashr_lshr2(i32 %x, i32 %y) {
19 ; CHECK-LABEL: @ashr_lshr2(
20 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 8
21 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
22 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
23 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
24 ; CHECK-NEXT: ret i32 [[RET]]
25 ;
26 %cmp = icmp sgt i32 %x, 8
27 %l = lshr i32 %x, %y
28 %r = ashr i32 %x, %y
29 %ret = select i1 %cmp, i32 %l, i32 %r
30 ret i32 %ret
31 }
32
33 define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
34 ; CHECK-LABEL: @ashr_lshr_exact_both(
35 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
36 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
37 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
38 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
39 ; CHECK-NEXT: ret i32 [[RET]]
40 ;
41 %cmp = icmp sgt i32 %x, -1
42 %l = lshr exact i32 %x, %y
43 %r = ashr exact i32 %x, %y
44 %ret = select i1 %cmp, i32 %l, i32 %r
45 ret i32 %ret
46 }
47
48 define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
49 ; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
50 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
51 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
52 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
53 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
54 ; CHECK-NEXT: ret i32 [[RET]]
55 ;
56 %cmp = icmp sgt i32 %x, -1
57 %l = lshr exact i32 %x, %y
58 %r = ashr i32 %x, %y
59 %ret = select i1 %cmp, i32 %l, i32 %r
60 ret i32 %ret
61 }
62
63 define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
64 ; CHECK-LABEL: @ashr_lshr_vec(
65 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
66 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
67 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
68 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
69 ; CHECK-NEXT: ret <2 x i32> [[RET]]
70 ;
71 %cmp = icmp sgt <2 x i32> %x,
72 %l = lshr <2 x i32> %x, %y
73 %r = ashr <2 x i32> %x, %y
74 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
75 ret <2 x i32> %ret
76 }
77
78 define <2 x i32> @ashr_lshr_vec2(<2 x i32> %x, <2 x i32> %y) {
79 ; CHECK-LABEL: @ashr_lshr_vec2(
80 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
81 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
82 ; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
83 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
84 ; CHECK-NEXT: ret <2 x i32> [[RET]]
85 ;
86 %cmp = icmp sgt <2 x i32> %x,
87 %l = lshr exact <2 x i32> %x, %y
88 %r = ashr exact <2 x i32> %x, %y
89 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
90 ret <2 x i32> %ret
91 }
92
93 define <2 x i32> @ashr_lshr_vec3(<2 x i32> %x, <2 x i32> %y) {
94 ; CHECK-LABEL: @ashr_lshr_vec3(
95 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
96 ; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
97 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
98 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
99 ; CHECK-NEXT: ret <2 x i32> [[RET]]
100 ;
101 %cmp = icmp sgt <2 x i32> %x,
102 %l = lshr exact <2 x i32> %x, %y
103 %r = ashr <2 x i32> %x, %y
104 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
105 ret <2 x i32> %ret
106 }
107
108 define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
109 ; CHECK-LABEL: @ashr_lshr_inv(
110 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
111 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
112 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
113 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
114 ; CHECK-NEXT: ret i32 [[RET]]
115 ;
116 %cmp = icmp slt i32 %x, 1
117 %l = lshr i32 %x, %y
118 %r = ashr i32 %x, %y
119 %ret = select i1 %cmp, i32 %r, i32 %l
120 ret i32 %ret
121 }
122
123 define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
124 ; CHECK-LABEL: @ashr_lshr_inv2(
125 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 5
126 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
127 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
128 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
129 ; CHECK-NEXT: ret i32 [[RET]]
130 ;
131 %cmp = icmp slt i32 %x, 5
132 %l = lshr i32 %x, %y
133 %r = ashr i32 %x, %y
134 %ret = select i1 %cmp, i32 %r, i32 %l
135 ret i32 %ret
136 }
137
138 define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
139 ; CHECK-LABEL: @ashr_lshr_inv_vec(
140 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
141 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
142 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
143 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
144 ; CHECK-NEXT: ret <2 x i32> [[RET]]
145 ;
146 %cmp = icmp slt <2 x i32> %x,
147 %l = lshr <2 x i32> %x, %y
148 %r = ashr <2 x i32> %x, %y
149 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
150 ret <2 x i32> %ret
151 }
152
153 ; Negative tests
154
155 define i32 @ashr_lshr_wrong_cst(i32 %x, i32 %y) {
156 ; CHECK-LABEL: @ashr_lshr_wrong_cst(
157 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -2
158 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
159 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
160 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
161 ; CHECK-NEXT: ret i32 [[RET]]
162 ;
163 %cmp = icmp sgt i32 %x, -2
164 %l = lshr i32 %x, %y
165 %r = ashr exact i32 %x, %y
166 %ret = select i1 %cmp, i32 %l, i32 %r
167 ret i32 %ret
168 }
169
170 define i32 @ashr_lshr_wrong_cst2(i32 %x, i32 %y) {
171 ; CHECK-LABEL: @ashr_lshr_wrong_cst2(
172 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], -1
173 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
174 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
175 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
176 ; CHECK-NEXT: ret i32 [[RET]]
177 ;
178 %cmp = icmp slt i32 %x, -1
179 %l = lshr exact i32 %x, %y
180 %r = ashr exact i32 %x, %y
181 %ret = select i1 %cmp, i32 %r, i32 %l
182 ret i32 %ret
183 }
184
185 define i32 @ashr_lshr_wrong(i32 %x, i32 %y) {
186 ; CHECK-LABEL: @ashr_lshr_wrong(
187 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], -1
188 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
189 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
190 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
191 ; CHECK-NEXT: ret i32 [[RET]]
192 ;
193 %cmp = icmp sge i32 %x, -1
194 %l = lshr i32 %x, %y
195 %r = ashr i32 %x, %y
196 %ret = select i1 %cmp, i32 %l, i32 %r
197 ret i32 %ret
198 }
199
200 define i32 @ashr_lshr_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
201 ; CHECK-LABEL: @ashr_lshr_shift_wrong_pred(
202 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], 0
203 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
204 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
205 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
206 ; CHECK-NEXT: ret i32 [[RET]]
207 ;
208 %cmp = icmp sle i32 %x, 0
209 %l = lshr i32 %x, %y
210 %r = ashr i32 %x, %y
211 %ret = select i1 %cmp, i32 %l, i32 %r
212 ret i32 %ret
213 }
214
215 define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
216 ; CHECK-LABEL: @ashr_lshr_shift_wrong_pred2(
217 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[Z:%.*]], 0
218 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
219 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
220 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
221 ; CHECK-NEXT: ret i32 [[RET]]
222 ;
223 %cmp = icmp sge i32 %z, 0
224 %l = lshr i32 %x, %y
225 %r = ashr i32 %x, %y
226 %ret = select i1 %cmp, i32 %l, i32 %r
227 ret i32 %ret
228 }
229
230 define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) {
231 ; CHECK-LABEL: @ashr_lshr_wrong_operands(
232 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
233 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
234 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
235 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
236 ; CHECK-NEXT: ret i32 [[RET]]
237 ;
238 %cmp = icmp sge i32 %x, 0
239 %l = lshr i32 %x, %y
240 %r = ashr i32 %x, %y
241 %ret = select i1 %cmp, i32 %r, i32 %l
242 ret i32 %ret
243 }
244
245 define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) {
246 ; CHECK-LABEL: @ashr_lshr_no_ashr(
247 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
248 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
249 ; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
250 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
251 ; CHECK-NEXT: ret i32 [[RET]]
252 ;
253 %cmp = icmp sge i32 %x, 0
254 %l = lshr i32 %x, %y
255 %r = xor i32 %x, %y
256 %ret = select i1 %cmp, i32 %l, i32 %r
257 ret i32 %ret
258 }
259
260 define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
261 ; CHECK-LABEL: @ashr_lshr_shift_amt_mismatch(
262 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
263 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
264 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
265 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
266 ; CHECK-NEXT: ret i32 [[RET]]
267 ;
268 %cmp = icmp sge i32 %x, 0
269 %l = lshr i32 %x, %y
270 %r = ashr i32 %x, %z
271 %ret = select i1 %cmp, i32 %l, i32 %r
272 ret i32 %ret
273 }
274
275 define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
276 ; CHECK-LABEL: @ashr_lshr_shift_base_mismatch(
277 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
278 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
279 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
280 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
281 ; CHECK-NEXT: ret i32 [[RET]]
282 ;
283 %cmp = icmp sge i32 %x, 0
284 %l = lshr i32 %x, %y
285 %r = ashr i32 %z, %y
286 %ret = select i1 %cmp, i32 %l, i32 %r
287 ret i32 %ret
288 }
289
290 define i32 @ashr_lshr_no_lshr(i32 %x, i32 %y) {
291 ; CHECK-LABEL: @ashr_lshr_no_lshr(
292 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
293 ; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
294 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
295 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
296 ; CHECK-NEXT: ret i32 [[RET]]
297 ;
298 %cmp = icmp sge i32 %x, 0
299 %l = add i32 %x, %y
300 %r = ashr i32 %x, %y
301 %ret = select i1 %cmp, i32 %l, i32 %r
302 ret i32 %ret
303 }
304
305 define <2 x i32> @ashr_lshr_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
306 ; CHECK-LABEL: @ashr_lshr_vec_wrong_pred(
307 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle <2 x i32> [[X:%.*]], zeroinitializer
308 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
309 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
310 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
311 ; CHECK-NEXT: ret <2 x i32> [[RET]]
312 ;
313 %cmp = icmp sle <2 x i32> %x, zeroinitializer
314 %l = lshr <2 x i32> %x, %y
315 %r = ashr <2 x i32> %x, %y
316 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
317 ret <2 x i32> %ret
318 }
319
320 define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
321 ; CHECK-LABEL: @ashr_lshr_inv_vec_wrong_pred(
322 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X:%.*]], zeroinitializer
323 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
324 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
325 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
326 ; CHECK-NEXT: ret <2 x i32> [[RET]]
327 ;
328 %cmp = icmp sge <2 x i32> %x, zeroinitializer
329 %l = lshr <2 x i32> %x, %y
330 %r = ashr <2 x i32> %x, %y
331 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
332 ret <2 x i32> %ret
333 }
334
335 define <2 x i32> @ashr_lshr_undef2(<2 x i32> %x, <2 x i32> %y) {
336 ; CHECK-LABEL: @ashr_lshr_undef2(
337 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
338 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
339 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
340 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
341 ; CHECK-NEXT: ret <2 x i32> [[RET]]
342 ;
343 %cmp = icmp sgt <2 x i32> %x,
344 %l = lshr <2 x i32> %x, %y
345 %r = ashr <2 x i32> %x, %y
346 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
347 ret <2 x i32> %ret
348 }
349
350 define <2 x i32> @ashr_lshr_undef3(<2 x i32> %x, <2 x i32> %y) {
351 ; CHECK-LABEL: @ashr_lshr_undef3(
352 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
353 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
354 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
355 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
356 ; CHECK-NEXT: ret <2 x i32> [[RET]]
357 ;
358 %cmp = icmp slt <2 x i32> %x,
359 %l = lshr <2 x i32> %x, %y
360 %r = ashr <2 x i32> %x, %y
361 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
362 ret <2 x i32> %ret
363 }
364
365 define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
366 ; CHECK-LABEL: @ashr_lshr_exact_ashr_only(
367 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
368 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
369 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
370 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
371 ; CHECK-NEXT: ret i32 [[RET]]
372 ;
373 %cmp = icmp sgt i32 %x, -1
374 %l = lshr i32 %x, %y
375 %r = ashr exact i32 %x, %y
376 %ret = select i1 %cmp, i32 %l, i32 %r
377 ret i32 %ret
378 }