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[X86Disassembler] Unify the EVEX and VEX code in emitContextTable. Merge the ATTR_VEXL/ATTR_EVEXL bits. NFCI Merging the two bits shrinks the context table from 16384 bytes to 8192 bytes. Remove the ATTRIBUTE_BITS macro and just create an enum directly. Then fix the ATTR_max define to be 8192 to reflect the table size so we stop hardcoding it separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363330 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 months ago
3 changed file(s) with 40 addition(s) and 74 deletion(s). Raw diff Collapse all Expand all
4545 // Attributes of an instruction that must be known before the opcode can be
4646 // processed correctly. Most of these indicate the presence of particular
4747 // prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
48 #define ATTRIBUTE_BITS \
49 ENUM_ENTRY(ATTR_NONE, 0x00) \
50 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
51 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
52 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
53 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
54 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
55 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
56 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
57 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
58 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
59 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
60 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
61 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
62 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
63 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
64
65 #define ENUM_ENTRY(n, v) n = v,
6648 enum attributeBits {
67 ATTRIBUTE_BITS
68 ATTR_max
69 };
70 #undef ENUM_ENTRY
49 ATTR_NONE = 0x00,
50 ATTR_64BIT = 0x1 << 0,
51 ATTR_XS = 0x1 << 1,
52 ATTR_XD = 0x1 << 2,
53 ATTR_REXW = 0x1 << 3,
54 ATTR_OPSIZE = 0x1 << 4,
55 ATTR_ADSIZE = 0x1 << 5,
56 ATTR_VEX = 0x1 << 6,
57 ATTR_VEXL = 0x1 << 7,
58 ATTR_EVEX = 0x1 << 8,
59 ATTR_EVEXL2 = 0x1 << 9,
60 ATTR_EVEXK = 0x1 << 10,
61 ATTR_EVEXKZ = 0x1 << 11,
62 ATTR_EVEXB = 0x1 << 12,
63 ATTR_max = 0x1 << 13,
64 };
7165
7266 // Combinations of the above attributes that are relevant to instruction
7367 // decode. Although other combinations are possible, they can be reduced to
881881 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
882882 attrMask |= ATTR_EVEXK;
883883 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
884 attrMask |= ATTR_EVEXL;
884 attrMask |= ATTR_VEXL;
885885 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
886886 attrMask |= ATTR_EVEXL2;
887887 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
887887 }
888888
889889 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
890 const unsigned int tableSize = 16384;
891890 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
892 "[" << tableSize << "] = {\n";
891 "[" << ATTR_max << "] = {\n";
893892 i++;
894893
895 for (unsigned index = 0; index < tableSize; ++index) {
894 for (unsigned index = 0; index < ATTR_max; ++index) {
896895 o.indent(i * 2);
897896
898 if (index & ATTR_EVEX) {
899 o << "IC_EVEX";
900 if (index & ATTR_EVEXL2)
897 if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
898 if (index & ATTR_EVEX)
899 o << "IC_EVEX";
900 else
901 o << "IC_VEX";
902
903 if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
901904 o << "_L2";
902 else if (index & ATTR_EVEXL)
905 else if (index & ATTR_VEXL)
903906 o << "_L";
907
904908 if (index & ATTR_REXW)
905909 o << "_W";
910
906911 if (index & ATTR_OPSIZE)
907912 o << "_OPSIZE";
908913 else if (index & ATTR_XD)
909914 o << "_XD";
910915 else if (index & ATTR_XS)
911916 o << "_XS";
912 if (index & ATTR_EVEXKZ)
913 o << "_KZ";
914 else if (index & ATTR_EVEXK)
915 o << "_K";
916 if (index & ATTR_EVEXB)
917 o << "_B";
917
918 if ((index & ATTR_EVEX)) {
919 if (index & ATTR_EVEXKZ)
920 o << "_KZ";
921 else if (index & ATTR_EVEXK)
922 o << "_K";
923
924 if (index & ATTR_EVEXB)
925 o << "_B";
926 }
918927 }
919 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
920 o << "IC_VEX_L_W_OPSIZE";
921 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
922 o << "IC_VEX_L_W_XD";
923 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
924 o << "IC_VEX_L_W_XS";
925 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
926 o << "IC_VEX_L_W";
927 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
928 o << "IC_VEX_L_OPSIZE";
929 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
930 o << "IC_VEX_L_XD";
931 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
932 o << "IC_VEX_L_XS";
933 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
934 o << "IC_VEX_W_OPSIZE";
935 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
936 o << "IC_VEX_W_XD";
937 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
938 o << "IC_VEX_W_XS";
939 else if (index & ATTR_VEXL)
940 o << "IC_VEX_L";
941 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
942 o << "IC_VEX_W";
943 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
944 o << "IC_VEX_OPSIZE";
945 else if ((index & ATTR_VEX) && (index & ATTR_XD))
946 o << "IC_VEX_XD";
947 else if ((index & ATTR_VEX) && (index & ATTR_XS))
948 o << "IC_VEX_XS";
949 else if (index & ATTR_VEX)
950 o << "IC_VEX";
951928 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
952929 o << "IC_64BIT_REXW_XS";
953930 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
1002979 else
1003980 o << "IC";
1004981
1005 if (index < tableSize - 1)
1006 o << ",";
1007 else
1008 o << " ";
1009
1010 o << " /* " << index << " */";
982 o << ", /* " << index << " */";
1011983
1012984 o << "\n";
1013985 }