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[llvm-objdump] Implement -Mreg-names-raw/-std options. The --disassembler-options, or -M, are used to customize the disassembler and affect its output. The two implemented options allow selecting register names on ARM: * With -Mreg-names-raw, the disassembler uses rNN for all registers. * With -Mreg-names-std it prints sp, lr and pc for r13, r14 and r15, which is the default behavior of llvm-objdump. Differential Revision: https://reviews.llvm.org/D57680 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354870 91177308-0d34-0410-b5e6-96231b3b80d8 Igor Kudrin 1 year, 5 months ago
8 changed file(s) with 86 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
6363
6464 virtual ~MCInstPrinter();
6565
66 /// Customize the printer according to a command line option.
67 /// @return true if the option is recognized and applied.
68 virtual bool applyTargetSpecificCLOption(StringRef Opt) { return false; }
69
6670 /// Specify a stream to emit comments to.
6771 void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }
6872
120120 // this register class when printing.
121121 class RegAltNameIndex {
122122 string Namespace = "";
123
124 // A set to be used if the name for a register is not defined in this set.
125 // This allows creating name sets with only a few alternative names.
126 RegAltNameIndex FallbackRegAltNameIndex = ?;
123127 }
124128 def NoRegAltName : RegAltNameIndex;
125129
1212 //===----------------------------------------------------------------------===//
1313
1414 // Registers are identified with 4-bit ID numbers.
15 class ARMReg Enc, string n, list subregs = []> : Register {
15 class ARMReg Enc, string n, list subregs = [],
16 list altNames = []> : Register {
1617 let HWEncoding = Enc;
1718 let Namespace = "ARM";
1819 let SubRegs = subregs;
2324 class ARMFReg Enc, string n> : Register {
2425 let HWEncoding = Enc;
2526 let Namespace = "ARM";
27 }
28
29 let Namespace = "ARM",
30 FallbackRegAltNameIndex = NoRegAltName in {
31 def RegNamesRaw : RegAltNameIndex;
2632 }
2733
2834 // Subregister indices.
8288 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
8389 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
8490 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
85 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
86 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
87 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
91 let RegAltNameIndices = [RegNamesRaw] in {
92 def SP : ARMReg<13, "sp", [], ["r13"]>, DwarfRegNum<[13]>;
93 def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>;
94 def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>;
95 }
8896 }
8997
9098 // Float registers
7171 const MCRegisterInfo &MRI)
7272 : MCInstPrinter(MAI, MII, MRI) {}
7373
74 bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
75 if (Opt == "reg-names-std") {
76 DefaultAltIdx = ARM::NoRegAltName;
77 return true;
78 }
79 if (Opt == "reg-names-raw") {
80 DefaultAltIdx = ARM::RegNamesRaw;
81 return true;
82 }
83 return false;
84 }
85
7486 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75 OS << markup(") << markup(">");
87 OS << markup(", DefaultAltIdx) << markup(">");
7688 }
7789
7890 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
1212 #ifndef LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H
1313 #define LLVM_LIB_TARGET_ARM_INSTPRINTER_ARMINSTPRINTER_H
1414
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
1516 #include "llvm/MC/MCInstPrinter.h"
1617
1718 namespace llvm {
2021 public:
2122 ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
2223 const MCRegisterInfo &MRI);
24
25 bool applyTargetSpecificCLOption(StringRef Opt) override;
2326
2427 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
2528 const MCSubtargetInfo &STI) override;
3437 unsigned PrintMethodIdx,
3538 const MCSubtargetInfo &STI,
3639 raw_ostream &O);
37 static const char *getRegisterName(unsigned RegNo);
40 static const char *getRegisterName(unsigned RegNo,
41 unsigned AltIdx = ARM::NoRegAltName);
3842
3943 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
4044 raw_ostream &O);
234238 template
235239 void printComplexRotationOp(const MCInst *MI, unsigned OpNum,
236240 const MCSubtargetInfo &STI, raw_ostream &O);
241
242 private:
243 unsigned DefaultAltIdx = ARM::NoRegAltName;
237244 };
238245
239246 } // end namespace llvm
0 @ RUN: llvm-mc %s -triple armv5-unknown-linux -filetype=obj -o %t
1 @ RUN: llvm-objdump -d %t | FileCheck -check-prefix=STD %s
2 @ RUN: llvm-objdump -d -Mreg-names-std %t \
3 @ RUN: | FileCheck -check-prefix=STD %s
4 @ RUN: llvm-objdump -d --disassembler-options=reg-names-raw %t \
5 @ RUN: | FileCheck -check-prefix=RAW %s
6 @ RUN: llvm-objdump -d -Mreg-names-raw,reg-names-std %t \
7 @ RUN: | FileCheck -check-prefix=STD %s
8 @ RUN: llvm-objdump -d -Mreg-names-std,reg-names-raw %t \
9 @ RUN: | FileCheck -check-prefix=RAW %s
10 @ RUN: not llvm-objdump -d -Munknown %t 2>&1 \
11 @ RUN: | FileCheck -check-prefix=ERR %s
12 @ ERR: Unrecognized disassembler option: unknown
13
14 .text
15 add r13, r14, r15
16 @ STD: add sp, lr, pc
17 @ RAW: add r13, r14, r15
291291 cl::desc("Alias for --disassemble-zeroes"),
292292 cl::NotHidden, cl::Grouping,
293293 cl::aliasopt(DisassembleZeroes));
294
295 static cl::list
296 DisassemblerOptions("disassembler-options",
297 cl::desc("Pass target specific disassembler options"),
298 cl::value_desc("options"), cl::CommaSeparated);
299 static cl::alias
300 DisassemblerOptionsShort("M", cl::desc("Alias for --disassembler-options"),
301 cl::NotHidden, cl::Prefix, cl::CommaSeparated,
302 cl::aliasopt(DisassemblerOptions));
294303
295304 static StringRef ToolName;
296305
14721481 PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName));
14731482 SourcePrinter SP(Obj, TheTarget->getName());
14741483
1484 for (StringRef Opt : DisassemblerOptions)
1485 if (!IP->applyTargetSpecificCLOption(Opt))
1486 error("Unrecognized disassembler option: " + Opt);
1487
14751488 disassembleObject(TheTarget, Obj, Ctx, DisAsm.get(), MIA.get(), IP.get(),
14761489 STI.get(), PIP, SP, InlineRelocs);
14771490 }
584584 O << " case ";
585585 if (!Namespace.empty())
586586 O << Namespace << "::";
587 O << AltName << ":\n"
588 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
589 << "[RegNo-1]) &&\n"
590 << " \"Invalid alt name index for register!\");\n"
591 << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
587 O << AltName << ":\n";
588 if (R->isValueUnset("FallbackRegAltNameIndex"))
589 O << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
590 << "[RegNo-1]) &&\n"
591 << " \"Invalid alt name index for register!\");\n";
592 else {
593 O << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
594 << "[RegNo-1]))\n"
595 << " return getRegisterName(RegNo, ";
596 if (!Namespace.empty())
597 O << Namespace << "::";
598 O << R->getValueAsDef("FallbackRegAltNameIndex")->getName() << ");\n";
599 }
600 O << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
592601 << "[RegNo-1];\n";
593602 }
594603 O << " }\n";