llvm.org GIT mirror llvm / b7d45e1
Fix clang -Wimplicit-fallthrough warnings across llvm, NFC This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345882 91177308-0d34-0410-b5e6-96231b3b80d8 Reid Kleckner 10 months ago
20 changed file(s) with 24 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
28062806 SoFar = make(SSK);
28072807 if (!SoFar)
28082808 return nullptr;
2809 break;
28092810 default:
28102811 break;
28112812 }
719719 case Instruction::FPToSI:
720720 if (TTI.getFPOpCost(I.getType()) == TargetTransformInfo::TCC_Expensive)
721721 Cost += InlineConstants::CallPenalty;
722 break;
722723 default:
723724 break;
724725 }
557557 case StorageClass::PublicStatic:
558558 case StorageClass::ProtectedStatic:
559559 OS << "static ";
560 break;
560561 default:
561562 break;
562563 }
350350 case AMDGPU::G_SHL:
351351 if (isSALUMapping(MI))
352352 return getDefaultMappingSOP(MI);
353 // Fall-through
353 LLVM_FALLTHROUGH;
354354
355355 case AMDGPU::G_FADD:
356356 case AMDGPU::G_FPTOSI:
235235 // MI will become a KILL, don't considers it in scheduling
236236 return AluDiscarded;
237237 }
238 break;
238239 default:
239240 break;
240241 }
50485048 case Intrinsic::r600_read_tgid_z:
50495049 return getPreloadedValue(DAG, *MFI, VT,
50505050 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
5051 case Intrinsic::amdgcn_workitem_id_x: {
5051 case Intrinsic::amdgcn_workitem_id_x:
50525052 case Intrinsic::r600_read_tidig_x:
50535053 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
50545054 SDLoc(DAG.getEntryNode()),
50555055 MFI->getArgInfo().WorkItemIDX);
5056 }
50575056 case Intrinsic::amdgcn_workitem_id_y:
50585057 case Intrinsic::r600_read_tidig_y:
50595058 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
356356 case AsmToken::Plus: {
357357 if (getLexer().peekTok().is(AsmToken::Integer))
358358 return MatchOperand_NoMatch;
359 }
360 // Fall through.
359 LLVM_FALLTHROUGH;
360 }
361361
362362 case AsmToken::Equal:
363363 case AsmToken::Greater:
12071207 case Hexagon::S4_subaddi: // (__: ## - Rs<<0)
12081208 ED.Expr.Rs = MI.getOperand(OpNum+1);
12091209 ED.Expr.Neg = true;
1210 break;
12101211 default: // (__: ## + __<<_)
12111212 break;
12121213 }
24622462 case Hexagon::A4_cmpheqi: // s8
24632463 case Hexagon::C4_cmpneqi: // s8
24642464 Signed = true;
2465 break;
24652466 case Hexagon::A4_cmpbeqi: // u8
24662467 break;
24672468 case Hexagon::C2_cmpgtui: // u9
104104 default:
105105 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
106106 return false;
107 break;
107108 case TargetOpcode::EXTRACT_SUBREG:
108109 case TargetOpcode::INSERT_SUBREG:
109110 case TargetOpcode::SUBREG_TO_REG:
15671567 if (GlueAllocframeStore)
15681568 continue;
15691569 }
1570 break;
15701571 default:
15711572 break;
15721573 }
766766
767767 ~MipsOperand() override {
768768 switch (Kind) {
769 case k_Immediate:
770 break;
771769 case k_Memory:
772770 delete Mem.Base;
773771 break;
774772 case k_RegList:
775773 delete RegList.List;
774 break;
775 case k_Immediate:
776776 case k_RegisterIndex:
777777 case k_Token:
778778 break;
560560 O << '$' << MipsInstPrinter::getRegisterName(Reg);
561561 return false;
562562 }
563 break;
563564 }
564565 case 'w':
565566 // Print MSA registers for the 'f' constraint
243243 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
244244 break;
245245 }
246 // fallthrough
246 LLVM_FALLTHROUGH;
247247 case Mips::BuildPairF64:
248248 case Mips::ExtractElementF64:
249249 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
902902 case MVT::i8:
903903 case MVT::i16:
904904 NeedsExt = true;
905 // Intentional fall-through.
905 LLVM_FALLTHROUGH;
906906 case MVT::i32:
907907 if (!UseImm)
908908 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
39693969
39703970 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
39713971 "Invalid QPX parameter type");
3972 /* fall through */
3972 LLVM_FALLTHROUGH;
39733973
39743974 case MVT::v4f64:
39753975 case MVT::v4i1:
61126112 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
61136113 "Invalid QPX parameter type");
61146114
6115 /* fall through */
6115 LLVM_FALLTHROUGH;
61166116 case MVT::v4f64:
61176117 case MVT::v4i1: {
61186118 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
13071307 return false;
13081308 case SystemZISD::SSUBO:
13091309 NegateOperand = true;
1310 /* fall through */
1310 LLVM_FALLTHROUGH;
13111311 case SystemZISD::SADDO:
13121312 if (MemVT == MVT::i32)
13131313 NewOpc = SystemZ::ASI;
13181318 break;
13191319 case SystemZISD::USUBO:
13201320 NegateOperand = true;
1321 /* fall through */
1321 LLVM_FALLTHROUGH;
13221322 case SystemZISD::UADDO:
13231323 if (MemVT == MVT::i32)
13241324 NewOpc = SystemZ::ALSI;
446446 (isa(V) && cast(V)->hasZExtAttr()))
447447 return copyValue(Reg);
448448 }
449 break;
449450 case MVT::i8:
450451 case MVT::i16:
451452 break;
13921392 break;
13931393 case 0x1:
13941394 insn->displacementSize = 1;
1395 /* FALLTHROUGH */
1395 LLVM_FALLTHROUGH;
13961396 case 0x2:
13971397 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
13981398 switch (rm & 7) {