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Merging r341221: ------------------------------------------------------------------------ r341221 | atanasyan | 2018-08-31 08:57:17 -0700 (Fri, 31 Aug 2018) | 12 lines [mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6 The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel, but do not have StdMMR6Rel tags. When these instructions are emitted for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor `Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the backend uses mips32 variant of the instructions encoding. The patch fixes this problem by adding the StdMMR6Rel tag and check instructions encoding in the test case. Differential revision: https://reviews.llvm.org/D51482 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346737 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 11 months ago
3 changed file(s) with 73 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
17321732 defm D_MMR6 : Cmp_Pats, ISA_MICROMIPS32R6;
17331733
17341734 def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1735 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1 ZERO))>, ISA_MICROMIPS32R6;
1735 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
17361736 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
17371737 (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
17381738
484484 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,
485485 ISA_MIPS1;
486486
487 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
488 bitconvert>, MFC1_FM<0>, ISA_MIPS1;
487 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
488 bitconvert>, MFC1_FM<0>, ISA_MIPS1;
489489 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
490490 ISA_MIPS1, FGR_64 {
491491 let DecoderNamespace = "MipsFP64";
492492 }
493 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
494 bitconvert>, MFC1_FM<4>, ISA_MIPS1;
493 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
494 bitconvert>, MFC1_FM<4>, ISA_MIPS1;
495495 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
496496 ISA_MIPS1, FGR_64 {
497497 let DecoderNamespace = "MipsFP64";
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
2 ; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM2 %s
3 ; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
4 ; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM6 %s
5
6 define double @foo(double %a, double %b) {
7 ; MM2-LABEL: foo:
8 ; MM2: # %bb.0: # %entry
9 ; MM2-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b]
10 ; MM2-NEXT: mtc1 $zero, $f2 # encoding: [0x54,0x02,0x28,0x3b]
11 ; MM2-NEXT: mthc1 $zero, $f2 # encoding: [0x54,0x02,0x38,0x3b]
12 ; MM2-NEXT: c.ule.d $f12, $f2 # encoding: [0x54,0x4c,0x05,0xfc]
13 ; MM2-NEXT: bc1t $BB0_2 # encoding: [0x43,0xa0,A,A]
14 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_PC16_S1
15 ; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00]
16 ; MM2-NEXT: # %bb.1: # %entry
17 ; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A]
18 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1
19 ; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00]
20 ; MM2-NEXT: $BB0_2: # %return
21 ; MM2-NEXT: jrc $ra # encoding: [0x45,0xbf]
22 ;
23 ; MM6-LABEL: foo:
24 ; MM6: # %bb.0: # %entry
25 ; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06]
26 ; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b]
27 ; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b]
28 ; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5]
29 ; MM6-NEXT: mfc1 $2, $f1 # encoding: [0x54,0x41,0x20,0x3b]
30 ; MM6-NEXT: andi16 $2, $2, 1 # encoding: [0x2d,0x21]
31 ; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf]
32 entry:
33 %cmp = fcmp ogt double %a, 0.000000e+00
34 br i1 %cmp, label %if.end, label %if.else
35
36 if.else:
37 br label %return
38
39 if.end:
40 %mul = fmul double %a, 2.000000e+00
41 br label %return
42
43 return:
44 ret double %a
45 }
46
47 define double @bar(double %x, double %y) {
48 ; MM2-LABEL: bar:
49 ; MM2: # %bb.0: # %entry
50 ; MM2-NEXT: mov.d $f0, $f14 # encoding: [0x54,0x0e,0x20,0x7b]
51 ; MM2-NEXT: c.olt.d $f12, $f14 # encoding: [0x55,0xcc,0x05,0x3c]
52 ; MM2-NEXT: jr $ra # encoding: [0x00,0x1f,0x0f,0x3c]
53 ; MM2-NEXT: movt.d $f0, $f12, $fcc0 # encoding: [0x54,0x0c,0x02,0x60]
54 ;
55 ; MM6-LABEL: bar:
56 ; MM6: # %bb.0: # %entry
57 ; MM6-NEXT: cmp.lt.d $f0, $f12, $f14 # encoding: [0x55,0xcc,0x01,0x15]
58 ; MM6-NEXT: mfc1 $1, $f0 # encoding: [0x54,0x20,0x20,0x3b]
59 ; MM6-NEXT: mtc1 $1, $f0 # encoding: [0x44,0x81,0x00,0x00]
60 ; MM6-NEXT: sel.d $f0, $f14, $f12 # encoding: [0x55,0x8e,0x02,0xb8]
61 ; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf]
62 ; FIXME: mtc1 is encoded as a regular non-microMIPS instruction
63 entry:
64 %z = fcmp olt double %x, %y
65 %r = select i1 %z, double %x, double %y
66 ret double %r
67 }