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[ARM] Add the option to directly access TLS pointer This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc). Differential Revision: https://reviews.llvm.org/D34408 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309381 91177308-0d34-0410-b5e6-96231b3b80d8 Strahinja Petrovic 2 years ago
4 changed file(s) with 39 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
127127 // Fast execution of AES crypto operations
128128 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
129129 "CPU fuses AES crypto operations">;
130
131 // The way of reading thread pointer
132 def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
133 "Reading thread pointer from register">;
130134
131135 // Cyclone can zero VFP registers in 0 cycles.
132136 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
312312 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
313313 def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
314314 def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
315 def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">;
316 def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">;
315317 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
316318 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
317319 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
55185520 let isCall = 1,
55195521 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
55205522 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5521 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5522 }
5523 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>,
5524 Requires<[IsARM, IsReadTPSoft]>;
5525 }
5526
5527 // Reading thread pointer from coprocessor register
5528 def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>,
5529 Requires<[IsARM, IsReadTPHard]>;
55235530
55245531 //===----------------------------------------------------------------------===//
55255532 // SJLJ Exception handling intrinsics
329329
330330 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
331331 bool HasVMLxHazards = false;
332
333 // If true, read thread pointer from coprocessor register.
334 bool ReadTPHard = false;
332335
333336 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
334337 bool UseNEONForFPMovs = false;
656659 bool isMClass() const { return ARMProcClass == MClass; }
657660 bool isRClass() const { return ARMProcClass == RClass; }
658661 bool isAClass() const { return ARMProcClass == AClass; }
662 bool isReadTPHard() const { return ReadTPHard; }
659663
660664 bool isR9Reserved() const {
661665 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
0 ; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mattr=+read-tp-hard %s -o - | FileCheck %s -check-prefix=CHECK-HARD
1 ; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
2
3
4 ; __thread int counter;
5 ; void foo() {
6 ; counter = 5;
7 ; }
8
9
10 @counter = thread_local local_unnamed_addr global i32 0, align 4
11
12 define void @foo() local_unnamed_addr #0 {
13 entry:
14 store i32 5, i32* @counter, align 4
15 ret void
16 }
17
18
19 ; CHECK-LABEL: foo:
20 ; CHECK-HARD: mrc p15, #0, {{r[0-9]+}}, c13, c0, #3
21 ; CHECK-SOFT: bl __aeabi_read_tp