llvm.org GIT mirror llvm / b727933
Don't print (PLT) on arm. The R_ARM_PLT32 relocation is deprecated and is not produced by MC. This means that the code being deleted is dead from the .o point of view and was making the .s more confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272909 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 4 years ago
10 changed file(s) with 29 addition(s) and 57 deletion(s). Raw diff Collapse all Expand all
211211 GetARMGVSymbol(GV, TF)->print(O, MAI);
212212
213213 printOffset(MO.getOffset(), O);
214 if (TF == ARMII::MO_PLT)
215 O << "(PLT)";
216214 break;
217215 }
218216 case MachineOperand::MO_ConstantPoolIndex:
24292429 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
24302430 DbgLoc, TII.get(CallOpc));
24312431
2432 unsigned char OpFlags = 0;
2433
2434 // Add MO_PLT for global address or external symbol in the PIC relocation
2435 // model.
2436 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2437 OpFlags = ARMII::MO_PLT;
2438
24392432 // ARM calls don't take a predicate, but tBL / tBLX do.
24402433 if(isThumb2)
24412434 AddDefaultPred(MIB);
24422435 if (UseReg)
24432436 MIB.addReg(CalleeReg);
24442437 else if (!IntrMemName)
2445 MIB.addGlobalAddress(GV, 0, OpFlags);
2438 MIB.addGlobalAddress(GV, 0, 0);
24462439 else
2447 MIB.addExternalSymbol(IntrMemName, OpFlags);
2440 MIB.addExternalSymbol(IntrMemName, 0);
24482441
24492442 // Add implicit physical register uses to the call.
24502443 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
18771877 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
18781878 false, false, false, 0);
18791879 } else {
1880 // On ELF targets for PIC code, direct calls should go through the PLT
1881 unsigned OpFlags = 0;
1882 if (Subtarget->isTargetELF() &&
1883 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1884 OpFlags = ARMII::MO_PLT;
1885 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
1880 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
18861881 }
18871882 } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) {
18881883 isDirect = true;
19021897 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
19031898 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
19041899 } else {
1905 unsigned OpFlags = 0;
1906 // On ELF targets for PIC code, direct calls should go through the PLT
1907 if (Subtarget->isTargetELF() &&
1908 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1909 OpFlags = ARMII::MO_PLT;
1910 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
1900 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
19111901 }
19121902 }
19131903
4848 }
4949 break;
5050 }
51
52 case ARMII::MO_PLT:
53 Expr = MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_PLT,
54 OutContext);
55 break;
5651 }
5752
5853 if (!MO.isJTI() && MO.getOffset())
288288 /// higher 16 bit of the address. Used only via movt instruction.
289289 MO_HI16 = 0x2,
290290
291 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
292 /// call operand.
293 MO_PLT = 0x3,
294
295291 /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
296292 /// just that part of the flag set.
297293 MO_OPTION_MASK = 0x1f,
1111
1212 define void @t1() {
1313 ; CHECKELF-LABEL: t1:
14 ; CHECKELF: bl g(PLT)
14 ; CHECKELF: bl g
1515 call void @g( i32 1, i32 2, i32 3, i32 4 )
1616 ret void
1717 }
3232 ; CHECKV6-LABEL: t3:
3333 ; CHECKV6: b _t2
3434 ; CHECKELF-LABEL: t3:
35 ; CHECKELF: b t2(PLT)
35 ; CHECKELF: b t2
3636 ; CHECKT2D-LABEL: t3:
3737 ; CHECKT2D: b.w _t2
3838
4646 ; CHECKV6-LABEL: t4:
4747 ; CHECKV6: b _sin
4848 ; CHECKELF-LABEL: t4:
49 ; CHECKELF: b sin(PLT)
49 ; CHECKELF: b sin
5050 %0 = tail call double @sin(double %a) nounwind readonly ; [#uses=1]
5151 ret double %0
5252 }
5656 ; CHECKV6-LABEL: t5:
5757 ; CHECKV6: b _sinf
5858 ; CHECKELF-LABEL: t5:
59 ; CHECKELF: b sinf(PLT)
59 ; CHECKELF: b sinf
6060 %0 = tail call float @sinf(float %a) nounwind readonly ; [#uses=1]
6161 ret float %0
6262 }
7070 ; CHECKV6-LABEL: t6:
7171 ; CHECKV6: b ___divsi3
7272 ; CHECKELF-LABEL: t6:
73 ; CHECKELF: b __aeabi_idiv(PLT)
73 ; CHECKELF: b __aeabi_idiv
7474 %0 = sdiv i32 %a, %b
7575 ret i32 %0
7676 }
1111 declare void @g(i32, i32, i32, i32)
1212
1313 define void @f() {
14 ; CHECKELF: PLT
14 ; CHECKELF: bl g
1515 call void @g( i32 1, i32 2, i32 3, i32 4 )
1616 ret void
1717 }
1010 ; ARM32-LABEL: my_get_xyz:
1111 ; ARM32: ldr r0,
1212 ; ARM32: ldr r0, [pc, r0]
13 ; ARM32-NEXT: bl my_emutls_get_address(PLT)
13 ; ARM32-NEXT: bl my_emutls_get_address
1414 ; ARM32-NEXT: ldr r0, [r0]
1515 ; ARM32: .long my_emutls_v_xyz(GOT_PREL)
1616
3333 ; ARM32-LABEL: f1:
3434 ; ARM32: ldr r0,
3535 ; ARM32: ldr r0, [pc, r0]
36 ; ARM32-NEXT: bl __emutls_get_address(PLT)
36 ; ARM32-NEXT: bl __emutls_get_address
3737 ; ARM32-NEXT: ldr r0, [r0]
3838 ; ARM32: .long __emutls_v.i1(GOT_PREL)
3939
4646 ; ARM32-LABEL: f2:
4747 ; ARM32: ldr r0,
4848 ; ARM32: ldr r0, [pc, r0]
49 ; ARM32-NEXT: bl __emutls_get_address(PLT)
49 ; ARM32-NEXT: bl __emutls_get_address
5050 ; ARM32-NEXT: pop
5151 ; ARM32: .long __emutls_v.i1(GOT_PREL)
5252
5858 ; ARM32-LABEL: f3:
5959 ; ARM32: ldr r0,
6060 ; ARM32: ldr r0, [pc, r0]
61 ; ARM32-NEXT: bl __emutls_get_address(PLT)
61 ; ARM32-NEXT: bl __emutls_get_address
6262 ; ARM32-NEXT: ldr r0, [r0]
6363 ; ARM32: .long __emutls_v.i2(GOT_PREL)
6464
7171 ; ARM32-LABEL: f4:
7272 ; ARM32: ldr r0,
7373 ; ARM32: ldr r0, [pc, r0]
74 ; ARM32-NEXT: bl __emutls_get_address(PLT)
74 ; ARM32-NEXT: bl __emutls_get_address
7575 ; ARM32-NEXT: pop
7676 ; ARM32: .long __emutls_v.i2(GOT_PREL)
7777
8383 ; ARM32-LABEL: f5:
8484 ; ARM32: ldr r0,
8585 ; ARM32: add r0, pc, r0
86 ; ARM32-NEXT: bl __emutls_get_address(PLT)
86 ; ARM32-NEXT: bl __emutls_get_address
8787 ; ARM32-NEXT: ldr r0, [r0]
8888 ; ARM32: .long __emutls_v.i3-
8989
9696 ; ARM32-LABEL: f6:
9797 ; ARM32: ldr r0,
9898 ; ARM32: add r0, pc, r0
99 ; ARM32-NEXT: bl __emutls_get_address(PLT)
99 ; ARM32-NEXT: bl __emutls_get_address
100100 ; ARM32-NEXT: pop
101101 ; ARM32: .long __emutls_v.i3-
102102
108108 ; ARM32-LABEL: f7:
109109 ; ARM32: ldr r0,
110110 ; ARM32: add r0, pc, r0
111 ; ARM32-NEXT: bl __emutls_get_address(PLT)
111 ; ARM32-NEXT: bl __emutls_get_address
112112 ; ARM32-NEXT: ldr r0, [r0]
113113 ; ARM32: .long __emutls_v.i4-(.LPC
114114
121121 ; ARM32-LABEL: f8:
122122 ; ARM32: ldr r0,
123123 ; ARM32: add r0, pc, r0
124 ; ARM32-NEXT: bl __emutls_get_address(PLT)
124 ; ARM32-NEXT: bl __emutls_get_address
125125 ; ARM32-NEXT: pop
126126 ; ARM32: .long __emutls_v.i4-(.LPC
127127
133133 ; ARM32-LABEL: f9:
134134 ; ARM32: ldr r0,
135135 ; ARM32: add r0, pc, r0
136 ; ARM32-NEXT: bl __emutls_get_address(PLT)
136 ; ARM32-NEXT: bl __emutls_get_address
137137 ; ARM32-NEXT: ldr r0, [r0]
138138
139139 entry:
145145 ; ARM32-LABEL: f10:
146146 ; ARM32: ldr r0,
147147 ; ARM32: add r0, pc, r0
148 ; ARM32-NEXT: bl __emutls_get_address(PLT)
148 ; ARM32-NEXT: bl __emutls_get_address
149149 ; ARM32-NEXT: pop
150150
151151 entry:
156156 ; ARM32-LABEL: f11:
157157 ; ARM32: ldr r0,
158158 ; ARM32: ldr r0, [pc, r0]
159 ; ARM32-NEXT: bl __emutls_get_address(PLT)
159 ; ARM32-NEXT: bl __emutls_get_address
160160 ; ARM32-NEXT: ldrh r0, [r0]
161161
162162 entry:
168168 ; ARM32-LABEL: f12:
169169 ; ARM32: ldr r0,
170170 ; ARM32: ldr r0, [pc, r0]
171 ; ARM32-NEXT: bl __emutls_get_address(PLT)
171 ; ARM32-NEXT: bl __emutls_get_address
172172 ; ARM32-NEXT: ldrsh r0, [r0]
173173
174174 entry:
181181 ; ARM32-LABEL: f13:
182182 ; ARM32: ldr r0,
183183 ; ARM32: ldr r0, [pc, r0]
184 ; ARM32-NEXT: bl __emutls_get_address(PLT)
184 ; ARM32-NEXT: bl __emutls_get_address
185185 ; ARM32-NEXT: ldrb r0, [r0]
186186 ; ARM32-NEXT: pop
187187
194194 ; ARM32-LABEL: f14:
195195 ; ARM32: ldr r0,
196196 ; ARM32: ldr r0, [pc, r0]
197 ; ARM32-NEXT: bl __emutls_get_address(PLT)
197 ; ARM32-NEXT: bl __emutls_get_address
198198 ; ARM32-NEXT: ldrsb r0, [r0]
199199 ; ARM32-NEXT: pop
200200
1010 entry:
1111
1212 %0 = call i32 @get()
13 ; CHECK: bl get(PLT)
13 ; CHECK: bl get
1414
1515 call void @put(i32 %0)
16 ; CHECK: bl put(PLT)
16 ; CHECK: bl put
1717
1818 ret void
1919 }
1010 ; CHECK-NOT-PIC: i(GOTTPOFF)
1111
1212 ; CHECK-PIC-LABEL: f:
13 ; CHECK-PIC: bl __tls_get_addr(PLT)
13 ; CHECK-PIC: bl __tls_get_addr
1414 %tmp1 = load i32, i32* @i ; [#uses=1]
1515 ret i32 %tmp1
1616 }
2323 ; CHECK-NOT-PIC: i(GOTTPOFF)
2424
2525 ; CHECK-PIC-LABEL: g:
26 ; CHECK-PIC: bl __tls_get_addr(PLT)
26 ; CHECK-PIC: bl __tls_get_addr
2727 ret i32* @i
2828 }