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[XCore] Add missing l2r instructions. These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Osborne 7 years ago
2 changed file(s) with 24 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
810810 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
811811
812812 // Two operand long
813 // getd, testlcl
814813 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
815814 "bitrev $dst, $src",
816815 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
823822 "clz $dst, $src",
824823 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
825824
825 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
826 "getd $dst, res[$src]", []>;
827
828 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
829 "getn $dst, res[$src]", []>;
830
826831 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
827832 "setc res[$r], $val",
828833 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
847852 "setclk res[$src1], $src2",
848853 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
849854
855 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
856 "setn res[$src1], $src2", []>;
857
850858 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
851859 "setrdy res[$src1], $src2",
852860 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
861
862 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
863 "testlcl $dst, res[$src]", []>;
853864
854865 // One operand short
855866 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
274274 # CHECK: settw res[r7], r2
275275 0x9b 0xff 0xec 0x27
276276
277 # CHECK: getd r8, res[r3]
278 0x53 0xff 0xec 0x1f
279
280 # CHECK: getn r10, res[r11]
281 0xbb 0xff 0xec 0x37
282
283 # CHECK: testlcl r2, res[r0]
284 0xc8 0xfe 0xec 0x27
285
286 # CHECK: setn res[r9], r7
287 0x6d 0xff 0xec 0x37
288
277289 # 3r instructions
278290
279291 # CHECK: add r1, r2, r3