llvm.org GIT mirror llvm / b70ea0b
Some clean up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50929 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
1 changed file(s) with 18 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
674674 def MOVLPSrm : PSI<0x12, MRMSrcMem,
675675 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
676676 "movlps\t{$src2, $dst|$dst, $src2}",
677 [(set VR128:$dst,
678 (v4f32 (vector_shuffle VR128:$src1,
679 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
680 MOVLP_shuffle_mask)))]>;
677 [(set VR128:$dst,
678 (v4f32 (vector_shuffle VR128:$src1,
679 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
680 MOVLP_shuffle_mask)))]>;
681681 def MOVHPSrm : PSI<0x16, MRMSrcMem,
682682 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
683683 "movhps\t{$src2, $dst|$dst, $src2}",
684 [(set VR128:$dst,
685 (v4f32 (vector_shuffle VR128:$src1,
686 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
687 MOVHP_shuffle_mask)))]>;
684 [(set VR128:$dst,
685 (v4f32 (vector_shuffle VR128:$src1,
686 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
687 MOVHP_shuffle_mask)))]>;
688688 } // AddedComplexity
689689 } // Constraints = "$src1 = $dst"
690
690691
691692 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
692693 "movlps\t{$src, $dst|$dst, $src}",
22642265
22652266 // Move to lower bits of a VR128 and zeroing upper bits.
22662267 // Loading from memory automatically zeroing upper bits.
2267 let AddedComplexity = 20 in
2268 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2269 "movsd\t{$src, $dst|$dst, $src}",
2270 [(set VR128:$dst,
2271 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2272 (loadf64 addr:$src))))))]>;
2268 let AddedComplexity = 20 in {
2269 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2270 "movsd\t{$src, $dst|$dst, $src}",
2271 [(set VR128:$dst,
2272 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2273 (loadf64 addr:$src))))))]>;
22732274
22742275 def : Pat<(v2f64 (X86vzmovl (memopv2f64 addr:$src))),
2275 (MOVZSD2PDrm addr:$src)>;
2276 (MOVZSD2PDrm addr:$src)>;
22762277 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2278 }
22772279
22782280 // movd / movq to XMM register zero-extends
22792281 let AddedComplexity = 15 in {
23002302 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
23012303 (loadi64 addr:$src))))))]>, XS,
23022304 Requires<[HasSSE2]>;
2303 }
23042305
23052306 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2307 }
23062308
23072309 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
23082310 // IA32 document. movq xmm1, xmm2 does clear the high bits.