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[ARM] Fix parsing of special register masks This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296607 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 3 years ago
2 changed file(s) with 12 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
43294329
43304330 // If some specific flag is already set, it means that some letter is
43314331 // present more than once, this is not acceptable.
4332 if (FlagsVal == ~0U || (FlagsVal & Flag))
4332 if (Flag == ~0U || (FlagsVal & Flag))
43334333 return MatchOperand_NoMatch;
43344334 FlagsVal |= Flag;
43354335 }
0 @ RUN: not llvm-mc -triple armv7a--none-eabi < %s |& FileCheck %s
1 @ RUN: not llvm-mc -triple thumbv7a--none-eabi < %s |& FileCheck %s
2
3 msr apsr_c, r0
4 @ CHECK: invalid operand for instruction
5 msr cpsr_w
6 @ CHECK: invalid operand for instruction
7 msr cpsr_cc
8 @ CHECK: invalid operand for instruction
9 msr xpsr_c
10 @ CHECK: invalid operand for instruction