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[PhaseOrdering] add tests for bittest patterns from bitfields; NFC As mentioned in D45986, there's a potential ordering dependency between instcombine and aggressive-instcombine for detecting these, so I'm adding a few tests to confirm that the expected folds occur using -O3 (because aggressive-instcombine only runs at -O3 currently). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331308 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 1 year, 4 months ago
1 changed file(s) with 152 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt -O3 -S < %s | FileCheck %s
2 ; RUN: opt -passes='default' -S < %s | FileCheck %s
3
4 ; These are tests that check for set/clear bits in a bitfield based on PR37098:
5 ; https://bugs.llvm.org/show_bug.cgi?id=37098
6 ;
7 ; The initial IR from clang has been transformed by SROA, but no other passes
8 ; have run yet. In all cases, we should reduce these to a mask and compare
9 ; instead of shift/cast/logic ops.
10 ;
11 ; Currently, this happens mostly through a combination of instcombine and
12 ; aggressive-instcombine. If pass ordering changes, we may have to adjust
13 ; the pattern matching in 1 or both of those passes.
14
15 ; Legal i32 is required to allow casting transforms that eliminate the zexts.
16 target datalayout = "n32"
17
18 define i32 @allclear(i32 %a) {
19 ; CHECK-LABEL: @allclear(
20 ; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1
21 ; CHECK-NEXT: [[BF_CLEAR1:%.*]] = or i32 [[BF_LSHR]], [[A]]
22 ; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2
23 ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[BF_CLEAR1]], [[BF_LSHR5]]
24 ; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3
25 ; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR2]], [[BF_LSHR10]]
26 ; CHECK-NEXT: [[OR13:%.*]] = and i32 [[OR83]], 1
27 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[OR13]], 1
28 ; CHECK-NEXT: ret i32 [[TMP1]]
29 ;
30 %a.sroa.0.0.trunc = trunc i32 %a to i8
31 %a.sroa.5.0.shift = lshr i32 %a, 8
32 %bf.clear = and i8 %a.sroa.0.0.trunc, 1
33 %bf.cast = zext i8 %bf.clear to i32
34 %bf.lshr = lshr i8 %a.sroa.0.0.trunc, 1
35 %bf.clear2 = and i8 %bf.lshr, 1
36 %bf.cast3 = zext i8 %bf.clear2 to i32
37 %or = or i32 %bf.cast, %bf.cast3
38 %bf.lshr5 = lshr i8 %a.sroa.0.0.trunc, 2
39 %bf.clear6 = and i8 %bf.lshr5, 1
40 %bf.cast7 = zext i8 %bf.clear6 to i32
41 %or8 = or i32 %or, %bf.cast7
42 %bf.lshr10 = lshr i8 %a.sroa.0.0.trunc, 3
43 %bf.clear11 = and i8 %bf.lshr10, 1
44 %bf.cast12 = zext i8 %bf.clear11 to i32
45 %or13 = or i32 %or8, %bf.cast12
46 %cmp = icmp eq i32 %or13, 0
47 %conv = zext i1 %cmp to i32
48 ret i32 %conv
49 }
50
51 define i32 @anyset(i32 %a) {
52 ; CHECK-LABEL: @anyset(
53 ; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1
54 ; CHECK-NEXT: [[BF_CLEAR1:%.*]] = or i32 [[BF_LSHR]], [[A]]
55 ; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2
56 ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[BF_CLEAR1]], [[BF_LSHR5]]
57 ; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3
58 ; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR2]], [[BF_LSHR10]]
59 ; CHECK-NEXT: [[OR13:%.*]] = and i32 [[OR83]], 1
60 ; CHECK-NEXT: ret i32 [[OR13]]
61 ;
62 %a.sroa.0.0.trunc = trunc i32 %a to i8
63 %a.sroa.5.0.shift = lshr i32 %a, 8
64 %bf.clear = and i8 %a.sroa.0.0.trunc, 1
65 %bf.cast = zext i8 %bf.clear to i32
66 %bf.lshr = lshr i8 %a.sroa.0.0.trunc, 1
67 %bf.clear2 = and i8 %bf.lshr, 1
68 %bf.cast3 = zext i8 %bf.clear2 to i32
69 %or = or i32 %bf.cast, %bf.cast3
70 %bf.lshr5 = lshr i8 %a.sroa.0.0.trunc, 2
71 %bf.clear6 = and i8 %bf.lshr5, 1
72 %bf.cast7 = zext i8 %bf.clear6 to i32
73 %or8 = or i32 %or, %bf.cast7
74 %bf.lshr10 = lshr i8 %a.sroa.0.0.trunc, 3
75 %bf.clear11 = and i8 %bf.lshr10, 1
76 %bf.cast12 = zext i8 %bf.clear11 to i32
77 %or13 = or i32 %or8, %bf.cast12
78 %cmp = icmp ne i32 %or13, 0
79 %conv = zext i1 %cmp to i32
80 ret i32 %conv
81 }
82
83 ; FIXME: aggressive-instcombine does not match this yet.
84
85 define i32 @allset(i32 %a) {
86 ; CHECK-LABEL: @allset(
87 ; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1
88 ; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2
89 ; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3
90 ; CHECK-NEXT: [[BF_CLEAR2:%.*]] = and i32 [[A]], 1
91 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[BF_CLEAR2]], [[BF_LSHR]]
92 ; CHECK-NEXT: [[AND8:%.*]] = and i32 [[AND]], [[BF_LSHR5]]
93 ; CHECK-NEXT: [[AND13:%.*]] = and i32 [[AND8]], [[BF_LSHR10]]
94 ; CHECK-NEXT: ret i32 [[AND13]]
95 ;
96 %a.sroa.0.0.trunc = trunc i32 %a to i8
97 %a.sroa.5.0.shift = lshr i32 %a, 8
98 %bf.clear = and i8 %a.sroa.0.0.trunc, 1
99 %bf.cast = zext i8 %bf.clear to i32
100 %bf.lshr = lshr i8 %a.sroa.0.0.trunc, 1
101 %bf.clear2 = and i8 %bf.lshr, 1
102 %bf.cast3 = zext i8 %bf.clear2 to i32
103 %and = and i32 %bf.cast, %bf.cast3
104 %bf.lshr5 = lshr i8 %a.sroa.0.0.trunc, 2
105 %bf.clear6 = and i8 %bf.lshr5, 1
106 %bf.cast7 = zext i8 %bf.clear6 to i32
107 %and8 = and i32 %and, %bf.cast7
108 %bf.lshr10 = lshr i8 %a.sroa.0.0.trunc, 3
109 %bf.clear11 = and i8 %bf.lshr10, 1
110 %bf.cast12 = zext i8 %bf.clear11 to i32
111 %and13 = and i32 %and8, %bf.cast12
112 %cmp = icmp ne i32 %and13, 0
113 %conv = zext i1 %cmp to i32
114 ret i32 %conv
115 }
116
117 ; FIXME: aggressive-instcombine does not match this yet.
118
119 define i32 @anyclear(i32 %a) {
120 ; CHECK-LABEL: @anyclear(
121 ; CHECK-NEXT: [[BF_LSHR:%.*]] = lshr i32 [[A:%.*]], 1
122 ; CHECK-NEXT: [[BF_LSHR5:%.*]] = lshr i32 [[A]], 2
123 ; CHECK-NEXT: [[BF_LSHR10:%.*]] = lshr i32 [[A]], 3
124 ; CHECK-NEXT: [[BF_CLEAR2:%.*]] = and i32 [[A]], 1
125 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[BF_CLEAR2]], [[BF_LSHR]]
126 ; CHECK-NEXT: [[AND8:%.*]] = and i32 [[AND]], [[BF_LSHR5]]
127 ; CHECK-NEXT: [[AND13:%.*]] = and i32 [[AND8]], [[BF_LSHR10]]
128 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND13]], 1
129 ; CHECK-NEXT: ret i32 [[TMP1]]
130 ;
131 %a.sroa.0.0.trunc = trunc i32 %a to i8
132 %a.sroa.5.0.shift = lshr i32 %a, 8
133 %bf.clear = and i8 %a.sroa.0.0.trunc, 1
134 %bf.cast = zext i8 %bf.clear to i32
135 %bf.lshr = lshr i8 %a.sroa.0.0.trunc, 1
136 %bf.clear2 = and i8 %bf.lshr, 1
137 %bf.cast3 = zext i8 %bf.clear2 to i32
138 %and = and i32 %bf.cast, %bf.cast3
139 %bf.lshr5 = lshr i8 %a.sroa.0.0.trunc, 2
140 %bf.clear6 = and i8 %bf.lshr5, 1
141 %bf.cast7 = zext i8 %bf.clear6 to i32
142 %and8 = and i32 %and, %bf.cast7
143 %bf.lshr10 = lshr i8 %a.sroa.0.0.trunc, 3
144 %bf.clear11 = and i8 %bf.lshr10, 1
145 %bf.cast12 = zext i8 %bf.clear11 to i32
146 %and13 = and i32 %and8, %bf.cast12
147 %cmp = icmp eq i32 %and13, 0
148 %conv = zext i1 %cmp to i32
149 ret i32 %conv
150 }
151