llvm.org GIT mirror llvm / b66f184
Constrain both operands on MOVZX32_NOREXrr8. This instruction is explicitly encoded without an REX prefix, so both operands but be *_NOREX. Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX constraints are not satisfied. This fixes a miscompilation in 20040709-2 in the gcc test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
2 changed file(s) with 7 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
7575 // except that they use GR32_NOREX for the output operand register class
7676 // instead of GR32. This allows them to operate on h registers on x86-64.
7777 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
78 (outs GR32_NOREX:$dst), (ins GR8:$src),
78 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
7979 "movz{bl|x}\t{$src, $dst|$dst, $src}",
8080 []>, TB;
8181 let mayLoad = 1 in
8282 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
83 (outs GR32_NOREX:$dst), (ins i8mem:$src),
83 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
8484 "movz{bl|x}\t{$src, $dst|$dst, $src}",
8585 []>, TB;
8686
21882188 // Copying to or from a physical H register on x86-64 requires a NOREX
21892189 // move. Otherwise use a normal move.
21902190 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2191 TM.getSubtarget().is64Bit())
2191 TM.getSubtarget().is64Bit()) {
21922192 Opc = X86::MOV8rr_NOREX;
2193 else
2193 // Both operands must be encodable without an REX prefix.
2194 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2195 "8-bit H register can not be copied outside GR8_NOREX");
2196 } else
21942197 Opc = X86::MOV8rr;
21952198 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
21962199 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;