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Fix line endings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293554 91177308-0d34-0410-b5e6-96231b3b80d8 Eli Friedman 3 years ago
4 changed file(s) with 12072 addition(s) and 12072 deletion(s). Raw diff Collapse all Expand all
None //=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of custom routines for the X86
10 // Calling Convention that aren't done by tablegen.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86Subtarget.h"
16 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/IR/CallingConv.h"
18
19 namespace llvm {
20
21 bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
22 CCValAssign::LocInfo &LocInfo,
23 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
24 // List of GPR registers that are available to store values in regcall
25 // calling convention.
26 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
27 X86::ESI};
28
29 // The vector will save all the available registers for allocation.
30 SmallVector AvailableRegs;
31
32 // searching for the available registers.
33 for (auto Reg : RegList) {
34 if (!State.isAllocated(Reg))
35 AvailableRegs.push_back(Reg);
36 }
37
38 const size_t RequiredGprsUponSplit = 2;
39 if (AvailableRegs.size() < RequiredGprsUponSplit)
40 return false; // Not enough free registers - continue the search.
41
42 // Allocating the available registers.
43 for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {
44
45 // Marking the register as located.
46 unsigned Reg = State.AllocateReg(AvailableRegs[I]);
47
48 // Since we previously made sure that 2 registers are available
49 // we expect that a real register number will be returned.
50 assert(Reg && "Expecting a register will be available");
51
52 // Assign the value to the allocated register
53 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
54 }
55
56 // Successful in allocating regsiters - stop scanning next rules.
57 return true;
58 }
59
60 static ArrayRef CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
61 if (ValVT.is512BitVector()) {
62 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
63 X86::ZMM3, X86::ZMM4, X86::ZMM5};
64 return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
65 }
66
67 if (ValVT.is256BitVector()) {
68 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
69 X86::YMM3, X86::YMM4, X86::YMM5};
70 return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
71 }
72
73 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
74 X86::XMM3, X86::XMM4, X86::XMM5};
75 return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
76 }
77
78 static ArrayRef CC_X86_64_VectorCallGetGPRs() {
79 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
80 return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
81 }
82
83 static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,
84 MVT &LocVT,
85 CCValAssign::LocInfo &LocInfo,
86 ISD::ArgFlagsTy &ArgFlags,
87 CCState &State) {
88
89 ArrayRef RegList = CC_X86_VectorCallGetSSEs(ValVT);
90 bool Is64bit = static_cast(
91 State.getMachineFunction().getSubtarget())
92 .is64Bit();
93
94 for (auto Reg : RegList) {
95 // If the register is not marked as allocated - assign to it.
96 if (!State.isAllocated(Reg)) {
97 unsigned AssigedReg = State.AllocateReg(Reg);
98 assert(AssigedReg == Reg && "Expecting a valid register allocation");
99 State.addLoc(
100 CCValAssign::getReg(ValNo, ValVT, AssigedReg, LocVT, LocInfo));
101 return true;
102 }
103 // If the register is marked as shadow allocated - assign to it.
104 if (Is64bit && State.IsShadowAllocatedReg(Reg)) {
105 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
106 return true;
107 }
108 }
109
110 llvm_unreachable("Clang should ensure that hva marked vectors will have "
111 "an available register.");
112 return false;
113 }
114
115 bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
116 CCValAssign::LocInfo &LocInfo,
117 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
118 // On the second pass, go through the HVAs only.
119 if (ArgFlags.isSecArgPass()) {
120 if (ArgFlags.isHva())
121 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
122 ArgFlags, State);
123 return true;
124 }
125
126 // Process only vector types as defined by vectorcall spec:
127 // "A vector type is either a floating-point type, for example,
128 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
129 if (!(ValVT.isFloatingPoint() ||
130 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
131 // If R9 was already assigned it means that we are after the fourth element
132 // and because this is not an HVA / Vector type, we need to allocate
133 // shadow XMM register.
134 if (State.isAllocated(X86::R9)) {
135 // Assign shadow XMM register.
136 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
137 }
138
139 return false;
140 }
141
142 if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
143 // Assign shadow GPR register.
144 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
145
146 // Assign XMM register - (shadow for HVA and non-shadow for non HVA).
147 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
148 // In Vectorcall Calling convention, additional shadow stack can be
149 // created on top of the basic 32 bytes of win64.
150 // It can happen if the fifth or sixth argument is vector type or HVA.
151 // At that case for each argument a shadow stack of 8 bytes is allocated.
152 if (Reg == X86::XMM4 || Reg == X86::XMM5)
153 State.AllocateStack(8, 8);
154
155 if (!ArgFlags.isHva()) {
156 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
157 return true; // Allocated a register - Stop the search.
158 }
159 }
160 }
161
162 // If this is an HVA - Stop the search,
163 // otherwise continue the search.
164 return ArgFlags.isHva();
165 }
166
167 bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
168 CCValAssign::LocInfo &LocInfo,
169 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
170 // On the second pass, go through the HVAs only.
171 if (ArgFlags.isSecArgPass()) {
172 if (ArgFlags.isHva())
173 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
174 ArgFlags, State);
175 return true;
176 }
177
178 // Process only vector types as defined by vectorcall spec:
179 // "A vector type is either a floating point type, for example,
180 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
181 if (!(ValVT.isFloatingPoint() ||
182 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
183 return false;
184 }
185
186 if (ArgFlags.isHva())
187 return true; // If this is an HVA - Stop the search.
188
189 // Assign XMM register.
190 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
191 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
192 return true;
193 }
194
195 // In case we did not find an available XMM register for a vector -
196 // pass it indirectly.
197 // It is similar to CCPassIndirect, with the addition of inreg.
198 if (!ValVT.isFloatingPoint()) {
199 LocVT = MVT::i32;
200 LocInfo = CCValAssign::Indirect;
201 ArgFlags.setInReg();
202 }
203
204 return false; // No register was assigned - Continue the search.
205 }
206
207 } // End llvm namespace
0 //=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of custom routines for the X86
10 // Calling Convention that aren't done by tablegen.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86Subtarget.h"
16 #include "llvm/CodeGen/CallingConvLower.h"
17 #include "llvm/IR/CallingConv.h"
18
19 namespace llvm {
20
21 bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
22 CCValAssign::LocInfo &LocInfo,
23 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
24 // List of GPR registers that are available to store values in regcall
25 // calling convention.
26 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
27 X86::ESI};
28
29 // The vector will save all the available registers for allocation.
30 SmallVector AvailableRegs;
31
32 // searching for the available registers.
33 for (auto Reg : RegList) {
34 if (!State.isAllocated(Reg))
35 AvailableRegs.push_back(Reg);
36 }
37
38 const size_t RequiredGprsUponSplit = 2;
39 if (AvailableRegs.size() < RequiredGprsUponSplit)
40 return false; // Not enough free registers - continue the search.
41
42 // Allocating the available registers.
43 for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {
44
45 // Marking the register as located.
46 unsigned Reg = State.AllocateReg(AvailableRegs[I]);
47
48 // Since we previously made sure that 2 registers are available
49 // we expect that a real register number will be returned.
50 assert(Reg && "Expecting a register will be available");
51
52 // Assign the value to the allocated register
53 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
54 }
55
56 // Successful in allocating regsiters - stop scanning next rules.
57 return true;
58 }
59
60 static ArrayRef CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
61 if (ValVT.is512BitVector()) {
62 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
63 X86::ZMM3, X86::ZMM4, X86::ZMM5};
64 return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
65 }
66
67 if (ValVT.is256BitVector()) {
68 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
69 X86::YMM3, X86::YMM4, X86::YMM5};
70 return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
71 }
72
73 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
74 X86::XMM3, X86::XMM4, X86::XMM5};
75 return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
76 }
77
78 static ArrayRef CC_X86_64_VectorCallGetGPRs() {
79 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
80 return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
81 }
82
83 static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,
84 MVT &LocVT,
85 CCValAssign::LocInfo &LocInfo,
86 ISD::ArgFlagsTy &ArgFlags,
87 CCState &State) {
88
89 ArrayRef RegList = CC_X86_VectorCallGetSSEs(ValVT);
90 bool Is64bit = static_cast(
91 State.getMachineFunction().getSubtarget())
92 .is64Bit();
93
94 for (auto Reg : RegList) {
95 // If the register is not marked as allocated - assign to it.
96 if (!State.isAllocated(Reg)) {
97 unsigned AssigedReg = State.AllocateReg(Reg);
98 assert(AssigedReg == Reg && "Expecting a valid register allocation");
99 State.addLoc(
100 CCValAssign::getReg(ValNo, ValVT, AssigedReg, LocVT, LocInfo));
101 return true;
102 }
103 // If the register is marked as shadow allocated - assign to it.
104 if (Is64bit && State.IsShadowAllocatedReg(Reg)) {
105 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
106 return true;
107 }
108 }
109
110 llvm_unreachable("Clang should ensure that hva marked vectors will have "
111 "an available register.");
112 return false;
113 }
114
115 bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
116 CCValAssign::LocInfo &LocInfo,
117 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
118 // On the second pass, go through the HVAs only.
119 if (ArgFlags.isSecArgPass()) {
120 if (ArgFlags.isHva())
121 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
122 ArgFlags, State);
123 return true;
124 }
125
126 // Process only vector types as defined by vectorcall spec:
127 // "A vector type is either a floating-point type, for example,
128 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
129 if (!(ValVT.isFloatingPoint() ||
130 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
131 // If R9 was already assigned it means that we are after the fourth element
132 // and because this is not an HVA / Vector type, we need to allocate
133 // shadow XMM register.
134 if (State.isAllocated(X86::R9)) {
135 // Assign shadow XMM register.
136 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
137 }
138
139 return false;
140 }
141
142 if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
143 // Assign shadow GPR register.
144 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
145
146 // Assign XMM register - (shadow for HVA and non-shadow for non HVA).
147 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
148 // In Vectorcall Calling convention, additional shadow stack can be
149 // created on top of the basic 32 bytes of win64.
150 // It can happen if the fifth or sixth argument is vector type or HVA.
151 // At that case for each argument a shadow stack of 8 bytes is allocated.
152 if (Reg == X86::XMM4 || Reg == X86::XMM5)
153 State.AllocateStack(8, 8);
154
155 if (!ArgFlags.isHva()) {
156 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
157 return true; // Allocated a register - Stop the search.
158 }
159 }
160 }
161
162 // If this is an HVA - Stop the search,
163 // otherwise continue the search.
164 return ArgFlags.isHva();
165 }
166
167 bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
168 CCValAssign::LocInfo &LocInfo,
169 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
170 // On the second pass, go through the HVAs only.
171 if (ArgFlags.isSecArgPass()) {
172 if (ArgFlags.isHva())
173 return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,
174 ArgFlags, State);
175 return true;
176 }
177
178 // Process only vector types as defined by vectorcall spec:
179 // "A vector type is either a floating point type, for example,
180 // a float or double, or an SIMD vector type, for example, __m128 or __m256".
181 if (!(ValVT.isFloatingPoint() ||
182 (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
183 return false;
184 }
185
186 if (ArgFlags.isHva())
187 return true; // If this is an HVA - Stop the search.
188
189 // Assign XMM register.
190 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
191 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
192 return true;
193 }
194
195 // In case we did not find an available XMM register for a vector -
196 // pass it indirectly.
197 // It is similar to CCPassIndirect, with the addition of inreg.
198 if (!ValVT.isFloatingPoint()) {
199 LocVT = MVT::i32;
200 LocInfo = CCValAssign::Indirect;
201 ArgFlags.setInReg();
202 }
203
204 return false; // No register was assigned - Continue the search.
205 }
206
207 } // End llvm namespace
None //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the X86 conditional move and set on condition
10 // instructions.
11 //
12 //===----------------------------------------------------------------------===//
13
14
15 // CMOV instructions.
16 multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> {
17 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
18 isCommutable = 1, SchedRW = [WriteALU] in {
19 def NAME#16rr
20 : I
21 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
22 [(set GR16:$dst,
23 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
24 IIC_CMOV16_RR>, TB, OpSize16;
25 def NAME#32rr
26 : I
27 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
28 [(set GR32:$dst,
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
30 IIC_CMOV32_RR>, TB, OpSize32;
31 def NAME#64rr
32 :RI
33 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
34 [(set GR64:$dst,
35 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
36 IIC_CMOV32_RR>, TB;
37 }
38
39 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
40 SchedRW = [WriteALULd, ReadAfterLd] in {
41 def NAME#16rm
42 : I
43 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
44 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
45 CondNode, EFLAGS))], IIC_CMOV16_RM>,
46 TB, OpSize16;
47 def NAME#32rm
48 : I
49 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
50 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
51 CondNode, EFLAGS))], IIC_CMOV32_RM>,
52 TB, OpSize32;
53 def NAME#64rm
54 :RI
55 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
56 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
57 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
58 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
59 } // end multiclass
60
61
62 // Conditional Moves.
63 defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
64 defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
65 defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
66 defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
67 defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
68 defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
69 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
70 defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
71 defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>;
72 defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
73 defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>;
74 defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
75 defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>;
76 defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
77 defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
78 defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>;
79
80
81 // SetCC instructions.
82 multiclass SETCC opc, string Mnemonic, PatLeaf OpNode> {
83 let Uses = [EFLAGS] in {
84 def r : I
85 !strconcat(Mnemonic, "\t$dst"),
86 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
87 IIC_SET_R>, TB, Sched<[WriteALU]>;
88 def m : I
89 !strconcat(Mnemonic, "\t$dst"),
90 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
91 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
92 } // Uses = [EFLAGS]
93 }
94
95 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
96 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
97 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
98 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
99 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
100 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
101 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
102 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
103 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
104 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed
105 defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set
106 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set
107 defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than
108 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
109 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal
110 defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than
111
112 // SALC is an undocumented instruction. Information for this instruction can be found
113 // here http://www.rcollins.org/secrets/opcodes/SALC.html
114 // Set AL if carry.
115 let Uses = [EFLAGS], Defs = [AL] in {
116 def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
117 }
0 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the X86 conditional move and set on condition
10 // instructions.
11 //
12 //===----------------------------------------------------------------------===//
13
14
15 // CMOV instructions.
16 multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> {
17 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
18 isCommutable = 1, SchedRW = [WriteALU] in {
19 def NAME#16rr
20 : I
21 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
22 [(set GR16:$dst,
23 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
24 IIC_CMOV16_RR>, TB, OpSize16;
25 def NAME#32rr
26 : I
27 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
28 [(set GR32:$dst,
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
30 IIC_CMOV32_RR>, TB, OpSize32;
31 def NAME#64rr
32 :RI
33 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
34 [(set GR64:$dst,
35 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
36 IIC_CMOV32_RR>, TB;
37 }
38
39 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
40 SchedRW = [WriteALULd, ReadAfterLd] in {
41 def NAME#16rm
42 : I
43 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
44 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
45 CondNode, EFLAGS))], IIC_CMOV16_RM>,
46 TB, OpSize16;
47 def NAME#32rm
48 : I
49 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
50 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
51 CondNode, EFLAGS))], IIC_CMOV32_RM>,
52 TB, OpSize32;
53 def NAME#64rm
54 :RI
55 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
56 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
57 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
58 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
59 } // end multiclass
60
61
62 // Conditional Moves.
63 defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
64 defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
65 defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
66 defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
67 defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
68 defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
69 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
70 defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
71 defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>;
72 defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>;
73 defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>;
74 defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>;
75 defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>;
76 defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>;
77 defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>;
78 defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>;
79
80
81 // SetCC instructions.
82 multiclass SETCC opc, string Mnemonic, PatLeaf OpNode> {
83 let Uses = [EFLAGS] in {
84 def r : I
85 !strconcat(Mnemonic, "\t$dst"),
86 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
87 IIC_SET_R>, TB, Sched<[WriteALU]>;
88 def m : I
89 !strconcat(Mnemonic, "\t$dst"),
90 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
91 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
92 } // Uses = [EFLAGS]
93 }
94
95 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
96 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
97 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
98 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
99 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
100 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
101 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
102 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
103 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
104 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed
105 defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set
106 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set
107 defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than
108 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
109 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal
110 defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than
111
112 // SALC is an undocumented instruction. Information for this instruction can be found
113 // here http://www.rcollins.org/secrets/opcodes/SALC.html
114 // Set AL if carry.
115 let Uses = [EFLAGS], Defs = [AL] in {
116 def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
117 }
None //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the shift and rotate instructions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 // FIXME: Someone needs to smear multipattern goodness all over this file.
14
15 let Defs = [EFLAGS] in {
16
17 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
18 let Uses = [CL] in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
20 "shl{b}\t{%cl, $dst|$dst, cl}",
21 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
23 "shl{w}\t{%cl, $dst|$dst, cl}",
24 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
26 "shl{l}\t{%cl, $dst|$dst, cl}",
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
29 "shl{q}\t{%cl, $dst|$dst, cl}",
30 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
31 } // Uses = [CL]
32
33 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
34 "shl{b}\t{$src2, $dst|$dst, $src2}",
35 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
36
37 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
39 "shl{w}\t{$src2, $dst|$dst, $src2}",
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
41 OpSize16;
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
45 OpSize32;
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
47 (ins GR64:$src1, u8imm:$src2),
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
50 IIC_SR>;
51 } // isConvertibleToThreeAddress = 1
52
53 // NOTE: We don't include patterns for shifts of a register by one, because
54 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
55 let hasSideEffects = 0 in {
56 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 "shl{b}\t$dst", [], IIC_SR>;
58 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
59 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
60 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
61 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
62 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
63 "shl{q}\t$dst", [], IIC_SR>;
64 } // hasSideEffects = 0
65 } // Constraints = "$src = $dst", SchedRW
66
67
68 let SchedRW = [WriteShiftLd, WriteRMW] in {
69 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
70 // using CL?
71 let Uses = [CL] in {
72 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
73 "shl{b}\t{%cl, $dst|$dst, cl}",
74 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
75 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
76 "shl{w}\t{%cl, $dst|$dst, cl}",
77 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
78 OpSize16;
79 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
80 "shl{l}\t{%cl, $dst|$dst, cl}",
81 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
82 OpSize32;
83 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
84 "shl{q}\t{%cl, $dst|$dst, cl}",
85 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
86 }
87 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
88 "shl{b}\t{$src, $dst|$dst, $src}",
89 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
90 IIC_SR>;
91 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
92 "shl{w}\t{$src, $dst|$dst, $src}",
93 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 IIC_SR>, OpSize16;
95 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
96 "shl{l}\t{$src, $dst|$dst, $src}",
97 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 IIC_SR>, OpSize32;
99 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
100 "shl{q}\t{$src, $dst|$dst, $src}",
101 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 IIC_SR>;
103
104 // Shift by 1
105 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
106 "shl{b}\t$dst",
107 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
108 IIC_SR>;
109 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
110 "shl{w}\t$dst",
111 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
112 IIC_SR>, OpSize16;
113 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
114 "shl{l}\t$dst",
115 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
116 IIC_SR>, OpSize32;
117 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
118 "shl{q}\t$dst",
119 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
120 IIC_SR>;
121 } // SchedRW
122
123 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
124 let Uses = [CL] in {
125 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
126 "shr{b}\t{%cl, $dst|$dst, cl}",
127 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
128 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
129 "shr{w}\t{%cl, $dst|$dst, cl}",
130 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
131 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132 "shr{l}\t{%cl, $dst|$dst, cl}",
133 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
134 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
135 "shr{q}\t{%cl, $dst|$dst, cl}",
136 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
137 }
138
139 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
140 "shr{b}\t{$src2, $dst|$dst, $src2}",
141 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
142 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
143 "shr{w}\t{$src2, $dst|$dst, $src2}",
144 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
145 IIC_SR>, OpSize16;
146 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
147 "shr{l}\t{$src2, $dst|$dst, $src2}",
148 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
149 IIC_SR>, OpSize32;
150 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
151 "shr{q}\t{$src2, $dst|$dst, $src2}",
152 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
153
154 // Shift right by 1
155 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
156 "shr{b}\t$dst",
157 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
158 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
159 "shr{w}\t$dst",
160 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
161 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
162 "shr{l}\t$dst",
163 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
164 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
165 "shr{q}\t$dst",
166 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
167 } // Constraints = "$src = $dst", SchedRW
168
169
170 let SchedRW = [WriteShiftLd, WriteRMW] in {
171 let Uses = [CL] in {
172 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
173 "shr{b}\t{%cl, $dst|$dst, cl}",
174 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
175 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
176 "shr{w}\t{%cl, $dst|$dst, cl}",
177 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
178 OpSize16;
179 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
180 "shr{l}\t{%cl, $dst|$dst, cl}",
181 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
182 OpSize32;
183 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
184 "shr{q}\t{%cl, $dst|$dst, cl}",
185 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
186 }
187 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
188 "shr{b}\t{$src, $dst|$dst, $src}",
189 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
190 IIC_SR>;
191 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
192 "shr{w}\t{$src, $dst|$dst, $src}",
193 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
194 IIC_SR>, OpSize16;
195 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
196 "shr{l}\t{$src, $dst|$dst, $src}",
197 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
198 IIC_SR>, OpSize32;
199 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
200 "shr{q}\t{$src, $dst|$dst, $src}",
201 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
202 IIC_SR>;
203
204 // Shift by 1
205 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
206 "shr{b}\t$dst",
207 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
208 IIC_SR>;
209 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
210 "shr{w}\t$dst",
211 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
212 IIC_SR>, OpSize16;
213 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
214 "shr{l}\t$dst",
215 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
216 IIC_SR>, OpSize32;
217 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
218 "shr{q}\t$dst",
219 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
220 IIC_SR>;
221 } // SchedRW
222
223 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
224 let Uses = [CL] in {
225 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
226 "sar{b}\t{%cl, $dst|$dst, cl}",
227 [(set GR8:$dst, (sra GR8:$src1, CL))],
228 IIC_SR>;
229 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
230 "sar{w}\t{%cl, $dst|$dst, cl}",
231 [(set GR16:$dst, (sra GR16:$src1, CL))],
232 IIC_SR>, OpSize16;
233 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234 "sar{l}\t{%cl, $dst|$dst, cl}",
235 [(set GR32:$dst, (sra GR32:$src1, CL))],
236 IIC_SR>, OpSize32;
237 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
238 "sar{q}\t{%cl, $dst|$dst, cl}",
239 [(set GR64:$dst, (sra GR64:$src1, CL))],
240 IIC_SR>;
241 }
242
243 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
244 "sar{b}\t{$src2, $dst|$dst, $src2}",
245 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
246 IIC_SR>;
247 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
248 "sar{w}\t{$src2, $dst|$dst, $src2}",
249 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
250 IIC_SR>, OpSize16;
251 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
252 "sar{l}\t{$src2, $dst|$dst, $src2}",
253 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
254 IIC_SR>, OpSize32;
255 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
256 (ins GR64:$src1, u8imm:$src2),
257 "sar{q}\t{$src2, $dst|$dst, $src2}",
258 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
259 IIC_SR>;
260
261 // Shift by 1
262 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
263 "sar{b}\t$dst",
264 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
265 IIC_SR>;
266 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
267 "sar{w}\t$dst",
268 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
269 IIC_SR>, OpSize16;
270 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
271 "sar{l}\t$dst",
272 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
273 IIC_SR>, OpSize32;
274 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
275 "sar{q}\t$dst",
276 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
277 IIC_SR>;
278 } // Constraints = "$src = $dst", SchedRW
279
280
281 let SchedRW = [WriteShiftLd, WriteRMW] in {
282 let Uses = [CL] in {
283 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
284 "sar{b}\t{%cl, $dst|$dst, cl}",
285 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
286 IIC_SR>;
287 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
288 "sar{w}\t{%cl, $dst|$dst, cl}",
289 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
290 IIC_SR>, OpSize16;
291 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
292 "sar{l}\t{%cl, $dst|$dst, cl}",
293 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
294 IIC_SR>, OpSize32;
295 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
296 "sar{q}\t{%cl, $dst|$dst, cl}",
297 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
298 IIC_SR>;
299 }
300 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
301 "sar{b}\t{$src, $dst|$dst, $src}",
302 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
303 IIC_SR>;
304 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
305 "sar{w}\t{$src, $dst|$dst, $src}",
306 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
307 IIC_SR>, OpSize16;
308 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
309 "sar{l}\t{$src, $dst|$dst, $src}",
310 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
311 IIC_SR>, OpSize32;
312 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
313 "sar{q}\t{$src, $dst|$dst, $src}",
314 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
315 IIC_SR>;
316
317 // Shift by 1
318 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
319 "sar{b}\t$dst",
320 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
321 IIC_SR>;
322 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
323 "sar{w}\t$dst",
324 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
325 IIC_SR>, OpSize16;
326 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
327 "sar{l}\t$dst",
328 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
329 IIC_SR>, OpSize32;
330 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
331 "sar{q}\t$dst",
332 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
333 IIC_SR>;
334 } // SchedRW
335
336 //===----------------------------------------------------------------------===//
337 // Rotate instructions
338 //===----------------------------------------------------------------------===//
339
340 let hasSideEffects = 0 in {
341 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
342
343 let Uses = [CL, EFLAGS] in {
344 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
346 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
347 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
348 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
349 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
350 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
351 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
352 } // Uses = [CL, EFLAGS]
353
354 let Uses = [EFLAGS] in {
355 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
356 "rcl{b}\t$dst", [], IIC_SR>;
357 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
358 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
359 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
360 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
361 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
362 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
363 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
364 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
365 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
366 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
367 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
368 "rcl{q}\t$dst", [], IIC_SR>;
369 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
370 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
371 } // Uses = [EFLAGS]
372
373 let Uses = [CL, EFLAGS] in {
374 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
375 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
376 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
377 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
378 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
379 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
380 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
381 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
382 } // Uses = [CL, EFLAGS]
383
384 let Uses = [EFLAGS] in {
385 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
386 "rcr{b}\t$dst", [], IIC_SR>;
387 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
388 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
389 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
390 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
391 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
392 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
394 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
397 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
398 "rcr{q}\t$dst", [], IIC_SR>;
399 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
400 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
401 } // Uses = [EFLAGS]
402
403 } // Constraints = "$src = $dst"
404
405 let SchedRW = [WriteShiftLd, WriteRMW] in {
406 let Uses = [EFLAGS] in {
407 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
408 "rcl{b}\t$dst", [], IIC_SR>;
409 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt),
410 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
411 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
412 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
413 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt),
414 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
415 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
416 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
417 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt),
418 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
419 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
420 "rcl{q}\t$dst", [], IIC_SR>;
421 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt),
422 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
423
424 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
425 "rcr{b}\t$dst", [], IIC_SR>;
426 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt),
427 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
428 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
429 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
430 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt),
431 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
432 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
433 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
434 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt),
435 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
436 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
437 "rcr{q}\t$dst", [], IIC_SR>;
438 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt),
439 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
440 } // Uses = [EFLAGS]
441
442 let Uses = [CL, EFLAGS] in {
443 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
444 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
445 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
446 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
447 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
448 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
449 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
450 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
451
452 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
453 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
454 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
455 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
456 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
457 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
458 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
459 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
460 } // Uses = [CL, EFLAGS]
461 } // SchedRW
462 } // hasSideEffects = 0
463
464 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
465 // FIXME: provide shorter instructions when imm8 == 1
466 let Uses = [CL] in {
467 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
468 "rol{b}\t{%cl, $dst|$dst, cl}",
469 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
470 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
471 "rol{w}\t{%cl, $dst|$dst, cl}",
472 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
473 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
474 "rol{l}\t{%cl, $dst|$dst, cl}",
475 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
476 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
477 "rol{q}\t{%cl, $dst|$dst, cl}",
478 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
479 }
480
481 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
482 "rol{b}\t{$src2, $dst|$dst, $src2}",
483 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
484 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
485 "rol{w}\t{$src2, $dst|$dst, $src2}",
486 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
487 IIC_SR>, OpSize16;
488 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
489 "rol{l}\t{$src2, $dst|$dst, $src2}",
490 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
491 IIC_SR>, OpSize32;
492 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
493 (ins GR64:$src1, u8imm:$src2),
494 "rol{q}\t{$src2, $dst|$dst, $src2}",
495 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
496 IIC_SR>;
497
498 // Rotate by 1
499 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
500 "rol{b}\t$dst",
501 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
502 IIC_SR>;
503 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
504 "rol{w}\t$dst",
505 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
506 IIC_SR>, OpSize16;
507 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
508 "rol{l}\t$dst",
509 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
510 IIC_SR>, OpSize32;
511 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
512 "rol{q}\t$dst",
513 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
514 IIC_SR>;
515 } // Constraints = "$src = $dst", SchedRW
516
517 let SchedRW = [WriteShiftLd, WriteRMW] in {
518 let Uses = [CL] in {
519 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
520 "rol{b}\t{%cl, $dst|$dst, cl}",
521 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
522 IIC_SR>;
523 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
524 "rol{w}\t{%cl, $dst|$dst, cl}",
525 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
526 IIC_SR>, OpSize16;
527 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
528 "rol{l}\t{%cl, $dst|$dst, cl}",
529 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
530 IIC_SR>, OpSize32;
531 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
532 "rol{q}\t{%cl, $dst|$dst, cl}",
533 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
534 IIC_SR>;
535 }
536 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
537 "rol{b}\t{$src1, $dst|$dst, $src1}",
538 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
539 IIC_SR>;
540 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1),
541 "rol{w}\t{$src1, $dst|$dst, $src1}",
542 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
543 IIC_SR>, OpSize16;
544 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1),
545 "rol{l}\t{$src1, $dst|$dst, $src1}",
546 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
547 IIC_SR>, OpSize32;
548 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
549 "rol{q}\t{$src1, $dst|$dst, $src1}",
550 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
551 IIC_SR>;
552
553 // Rotate by 1
554 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
555 "rol{b}\t$dst",
556 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
557 IIC_SR>;
558 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
559 "rol{w}\t$dst",
560 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
561 IIC_SR>, OpSize16;
562 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
563 "rol{l}\t$dst",
564 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
565 IIC_SR>, OpSize32;
566 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
567 "rol{q}\t$dst",
568 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
569 IIC_SR>;
570 } // SchedRW
571
572 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
573 let Uses = [CL] in {
574 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
575 "ror{b}\t{%cl, $dst|$dst, cl}",
576 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
577 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
578 "ror{w}\t{%cl, $dst|$dst, cl}",
579 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
580 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
581 "ror{l}\t{%cl, $dst|$dst, cl}",
582 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
583 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
584 "ror{q}\t{%cl, $dst|$dst, cl}",
585 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
586 }
587
588 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
589 "ror{b}\t{$src2, $dst|$dst, $src2}",
590 [(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))],
591 IIC_SR>;
592 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
593 "ror{w}\t{$src2, $dst|$dst, $src2}",
594 [(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))],
595 IIC_SR>, OpSize16;
596 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
597 "ror{l}\t{$src2, $dst|$dst, $src2}",
598 [(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))],
599 IIC_SR>, OpSize32;
600 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
601 (ins GR64:$src1, u8imm:$src2),
602 "ror{q}\t{$src2, $dst|$dst, $src2}",
603 [(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))],
604 IIC_SR>;
605
606 // Rotate by 1
607 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
608 "ror{b}\t$dst",
609 [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))],
610 IIC_SR>;
611 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
612 "ror{w}\t$dst",
613 [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))],
614 IIC_SR>, OpSize16;
615 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
616 "ror{l}\t$dst",
617 [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))],
618 IIC_SR>, OpSize32;
619 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
620 "ror{q}\t$dst",
621 [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))],
622 IIC_SR>;
623 } // Constraints = "$src = $dst", SchedRW
624
625 let SchedRW = [WriteShiftLd, WriteRMW] in {
626 let Uses = [CL] in {
627 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
628 "ror{b}\t{%cl, $dst|$dst, cl}",
629 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
630 IIC_SR>;
631 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
632 "ror{w}\t{%cl, $dst|$dst, cl}",
633 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
634 IIC_SR>, OpSize16;
635 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
636 "ror{l}\t{%cl, $dst|$dst, cl}",
637 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
638 IIC_SR>, OpSize32;
639 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
640 "ror{q}\t{%cl, $dst|$dst, cl}",
641 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
642 IIC_SR>;
643 }
644 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
645 "ror{b}\t{$src, $dst|$dst, $src}",
646 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
647 IIC_SR>;
648 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src),
649 "ror{w}\t{$src, $dst|$dst, $src}",
650 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
651 IIC_SR>, OpSize16;
652 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src),
653 "ror{l}\t{$src, $dst|$dst, $src}",
654 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
655 IIC_SR>, OpSize32;
656 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
657 "ror{q}\t{$src, $dst|$dst, $src}",
658 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
659 IIC_SR>;
660
661 // Rotate by 1
662 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
663 "ror{b}\t$dst",
664 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
665 IIC_SR>;
666 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
667 "ror{w}\t$dst",
668 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
669 IIC_SR>, OpSize16;
670 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
671 "ror{l}\t$dst",
672 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
673 IIC_SR>, OpSize32;
674 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
675 "ror{q}\t$dst",
676 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
677 IIC_SR>;
678 } // SchedRW
679
680
681 //===----------------------------------------------------------------------===//
682 // Double shift instructions (generalizations of rotate)
683 //===----------------------------------------------------------------------===//
684
685 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
686
687 let Uses = [CL] in {
688 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
689 (ins GR16:$src1, GR16:$src2),
690 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
691 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
692 IIC_SHD16_REG_CL>,
693 TB, OpSize16;
694 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
695 (ins GR16:$src1, GR16:$src2),
696 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
697 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
698 IIC_SHD16_REG_CL>,
699 TB, OpSize16;
700 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
701 (ins GR32:$src1, GR32:$src2),
702 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
703 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
704 IIC_SHD32_REG_CL>, TB, OpSize32;
705 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
706 (ins GR32:$src1, GR32:$src2),
707 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
708 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
709 IIC_SHD32_REG_CL>, TB, OpSize32;
710 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
711 (ins GR64:$src1, GR64:$src2),
712 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
713 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
714 IIC_SHD64_REG_CL>,
715 TB;
716 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
717 (ins GR64:$src1, GR64:$src2),
718 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
719 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
720 IIC_SHD64_REG_CL>,
721 TB;
722 }
723
724 let isCommutable = 1 in { // These instructions commute to each other.
725 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
726 (outs GR16:$dst),
727 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
728 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
729 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
730 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
731 TB, OpSize16;
732 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
733 (outs GR16:$dst),
734 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
735 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
736 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
737 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
738 TB, OpSize16;
739 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
740 (outs GR32:$dst),
741 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
742 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
743 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
744 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
745 TB, OpSize32;
746 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
747 (outs GR32:$dst),
748 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
749 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
750 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
751 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
752 TB, OpSize32;
753 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
754 (outs GR64:$dst),
755 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
756 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
757 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
758 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
759 TB;
760 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
761 (outs GR64:$dst),
762 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
763 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
764 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
765 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
766 TB;
767 }
768 } // Constraints = "$src = $dst", SchedRW
769
770 let SchedRW = [WriteShiftLd, WriteRMW] in {
771 let Uses = [CL] in {
772 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
773 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
774 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
775 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
776 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
777 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
778 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
779 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
780
781 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
782 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
783 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
784 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
785 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
786 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
787 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
788 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
789
790 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
791 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
792 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
793 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
794 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
795 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
796 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
797 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
798 }
799
800 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
801 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
802 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
803 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
804 (i8 imm:$src3)), addr:$dst)],
805 IIC_SHD16_MEM_IM>,
806 TB, OpSize16;
807 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
808 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
809 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
810 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
811 (i8 imm:$src3)), addr:$dst)],
812 IIC_SHD16_MEM_IM>,
813 TB, OpSize16;
814
815 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
816 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
817 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
818 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
819 (i8 imm:$src3)), addr:$dst)],
820 IIC_SHD32_MEM_IM>,
821 TB, OpSize32;
822 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
823 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
824 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
825 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
826 (i8 imm:$src3)), addr:$dst)],
827 IIC_SHD32_MEM_IM>,
828 TB, OpSize32;
829
830 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
831 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
832 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
833 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
834 (i8 imm:$src3)), addr:$dst)],
835 IIC_SHD64_MEM_IM>,
836 TB;
837 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
838 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
839 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
840 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
841 (i8 imm:$src3)), addr:$dst)],
842 IIC_SHD64_MEM_IM>,
843 TB;
844 } // SchedRW
845
846 } // Defs = [EFLAGS]
847
848 def ROT32L2R_imm8 : SDNodeXForm
849 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
850 return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
851 }]>;
852
853 def ROT64L2R_imm8 : SDNodeXForm
854 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
855 return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
856 }]>;
857
858 multiclass bmi_rotate {
859 let hasSideEffects = 0 in {
860 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
861 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
862 []>, TAXD, VEX, Sched<[WriteShift]>;
863 let mayLoad = 1 in
864 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
865 (ins x86memop:$src1, u8imm:$src2),
866 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
867 []>, TAXD, VEX, Sched<[WriteShiftLd]>;
868 }
869 }
870
871 multiclass bmi_shift {
872 let hasSideEffects = 0 in {
873 def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
874 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
875 VEX, Sched<[WriteShift]>;
876 let mayLoad = 1 in
877 def rm : I<0xF7, MRMSrcMem4VOp3,
878 (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
879 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
880 VEX, Sched<[WriteShiftLd,
881 // x86memop:$src1
882 ReadDefault, ReadDefault, ReadDefault, ReadDefault,
883 ReadDefault,
884 // RC:$src1
885 ReadAfterLd]>;
886 }
887 }
888
889 let Predicates = [HasBMI2] in {
890 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
891 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
892 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
893 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
894 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
895 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
896 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
897 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
898
899 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
900 let AddedComplexity = 10 in {
901 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
902 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
903 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
904 (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
905 }
906
907 def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
908 (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
909 def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
910 (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
911
912 // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
913 // immedidate shift, i.e. the following code is considered better
914 //
915 // mov %edi, %esi
916 // shl $imm, %esi
917 // ... %edi, ...
918 //
919 // than
920 //
921 // movb $imm, %sil
922 // shlx %sil, %edi, %esi
923 // ... %edi, ...
924 //
925 let AddedComplexity = 1 in {
926 def : Pat<(sra GR32:$src1, GR8:$src2),
927 (SARX32rr GR32:$src1,
928 (INSERT_SUBREG
929 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
930 def : Pat<(sra GR64:$src1, GR8:$src2),
931 (SARX64rr GR64:$src1,
932 (INSERT_SUBREG
933 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
934
935 def : Pat<(srl GR32:$src1, GR8:$src2),
936 (SHRX32rr GR32:$src1,
937 (INSERT_SUBREG
938 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
939 def : Pat<(srl GR64:$src1, GR8:$src2),
940 (SHRX64rr GR64:$src1,
941 (INSERT_SUBREG
942 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
943
944 def : Pat<(shl GR32:$src1, GR8:$src2),
945 (SHLX32rr GR32:$src1,
946 (INSERT_SUBREG
947 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
948 def : Pat<(shl GR64:$src1, GR8:$src2),
949 (SHLX64rr GR64:$src1,
950 (INSERT_SUBREG
951 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
952 }
953
954 // Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
955 //
956 // mov (%ecx), %esi
957 // shl $imm, $esi
958 //
959 // over
960 //
961 // movb $imm %al
962 // shlx %al, (%ecx), %esi
963 //
964 // As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
965 // optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.
966 }
0 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the shift and rotate instructions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 // FIXME: Someone needs to smear multipattern goodness all over this file.
14
15 let Defs = [EFLAGS] in {
16
17 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
18 let Uses = [CL] in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
20 "shl{b}\t{%cl, $dst|$dst, cl}",
21 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
23 "shl{w}\t{%cl, $dst|$dst, cl}",
24 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
26 "shl{l}\t{%cl, $dst|$dst, cl}",
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
29 "shl{q}\t{%cl, $dst|$dst, cl}",
30 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
31 } // Uses = [CL]
32
33 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
34 "shl{b}\t{$src2, $dst|$dst, $src2}",
35 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
36
37 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
39 "shl{w}\t{$src2, $dst|$dst, $src2}",
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
41 OpSize16;
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
45 OpSize32;
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
47 (ins GR64:$src1, u8imm:$src2),
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
50 IIC_SR>;
51 } // isConvertibleToThreeAddress = 1
52
53 // NOTE: We don't include patterns for shifts of a register by one, because
54 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
55 let hasSideEffects = 0 in {
56 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 "shl{b}\t$dst", [], IIC_SR>;
58 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
59 "shl{w}\t$dst", [], IIC_SR>, OpSize16;
60 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
61 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
62 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
63 "shl{q}\t$dst", [], IIC_SR>;
64 } // hasSideEffects = 0
65 } // Constraints = "$src = $dst", SchedRW
66
67
68 let SchedRW = [WriteShiftLd, WriteRMW] in {
69 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
70 // using CL?
71 let Uses = [CL] in {
72 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
73 "shl{b}\t{%cl, $dst|$dst, cl}",
74 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
75 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
76 "shl{w}\t{%cl, $dst|$dst, cl}",
77 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
78 OpSize16;
79 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
80 "shl{l}\t{%cl, $dst|$dst, cl}",
81 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
82 OpSize32;
83 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
84 "shl{q}\t{%cl, $dst|$dst, cl}",
85 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
86 }
87 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
88 "shl{b}\t{$src, $dst|$dst, $src}",
89 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
90 IIC_SR>;
91 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
92 "shl{w}\t{$src, $dst|$dst, $src}",
93 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 IIC_SR>, OpSize16;
95 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
96 "shl{l}\t{$src, $dst|$dst, $src}",
97 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 IIC_SR>, OpSize32;
99 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
100 "shl{q}\t{$src, $dst|$dst, $src}",
101 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 IIC_SR>;
103
104 // Shift by 1
105 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
106 "shl{b}\t$dst",
107 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
108 IIC_SR>;
109 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
110 "shl{w}\t$dst",
111 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
112 IIC_SR>, OpSize16;
113 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
114 "shl{l}\t$dst",
115 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
116 IIC_SR>, OpSize32;
117 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
118 "shl{q}\t$dst",
119 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
120 IIC_SR>;
121 } // SchedRW
122
123 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
124 let Uses = [CL] in {
125 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
126 "shr{b}\t{%cl, $dst|$dst, cl}",
127 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
128 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
129 "shr{w}\t{%cl, $dst|$dst, cl}",
130 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
131 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132 "shr{l}\t{%cl, $dst|$dst, cl}",
133 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
134 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
135 "shr{q}\t{%cl, $dst|$dst, cl}",
136 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
137 }
138
139 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
140 "shr{b}\t{$src2, $dst|$dst, $src2}",
141 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
142 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
143 "shr{w}\t{$src2, $dst|$dst, $src2}",
144 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
145 IIC_SR>, OpSize16;
146 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
147 "shr{l}\t{$src2, $dst|$dst, $src2}",
148 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
149 IIC_SR>, OpSize32;
150 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
151 "shr{q}\t{$src2, $dst|$dst, $src2}",
152 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
153
154 // Shift right by 1
155 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
156 "shr{b}\t$dst",
157 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
158 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
159 "shr{w}\t$dst",
160 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
161 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
162 "shr{l}\t$dst",
163 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
164 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
165 "shr{q}\t$dst",
166 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
167 } // Constraints = "$src = $dst", SchedRW
168
169
170 let SchedRW = [WriteShiftLd, WriteRMW] in {
171 let Uses = [CL] in {
172 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
173 "shr{b}\t{%cl, $dst|$dst, cl}",
174 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
175 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
176 "shr{w}\t{%cl, $dst|$dst, cl}",
177 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
178 OpSize16;
179 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
180 "shr{l}\t{%cl, $dst|$dst, cl}",
181 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
182 OpSize32;
183 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
184 "shr{q}\t{%cl, $dst|$dst, cl}",
185 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
186 }
187 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
188 "shr{b}\t{$src, $dst|$dst, $src}",
189 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
190 IIC_SR>;
191 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
192 "shr{w}\t{$src, $dst|$dst, $src}",
193 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
194 IIC_SR>, OpSize16;
195 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
196 "shr{l}\t{$src, $dst|$dst, $src}",
197 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
198 IIC_SR>, OpSize32;
199 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
200 "shr{q}\t{$src, $dst|$dst, $src}",
201 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
202 IIC_SR>;
203
204 // Shift by 1
205 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
206 "shr{b}\t$dst",
207 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
208 IIC_SR>;
209 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
210 "shr{w}\t$dst",
211 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
212 IIC_SR>, OpSize16;
213 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
214 "shr{l}\t$dst",
215 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
216 IIC_SR>, OpSize32;
217 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
218 "shr{q}\t$dst",
219 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
220 IIC_SR>;
221 } // SchedRW
222
223 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
224 let Uses = [CL] in {
225 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
226 "sar{b}\t{%cl, $dst|$dst, cl}",
227 [(set GR8:$dst, (sra GR8:$src1, CL))],
228 IIC_SR>;
229 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
230 "sar{w}\t{%cl, $dst|$dst, cl}",
231 [(set GR16:$dst, (sra GR16:$src1, CL))],
232 IIC_SR>, OpSize16;
233 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234 "sar{l}\t{%cl, $dst|$dst, cl}",
235 [(set GR32:$dst, (sra GR32:$src1, CL))],
236 IIC_SR>, OpSize32;
237 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
238 "sar{q}\t{%cl, $dst|$dst, cl}",
239 [(set GR64:$dst, (sra GR64:$src1, CL))],
240 IIC_SR>;
241 }
242
243 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
244 "sar{b}\t{$src2, $dst|$dst, $src2}",
245 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
246 IIC_SR>;
247 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
248 "sar{w}\t{$src2, $dst|$dst, $src2}",
249 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
250 IIC_SR>, OpSize16;
251 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
252 "sar{l}\t{$src2, $dst|$dst, $src2}",
253 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
254 IIC_SR>, OpSize32;
255 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
256 (ins GR64:$src1, u8imm:$src2),
257 "sar{q}\t{$src2, $dst|$dst, $src2}",
258 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
259 IIC_SR>;
260
261 // Shift by 1
262 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
263 "sar{b}\t$dst",
264 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
265 IIC_SR>;
266 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
267 "sar{w}\t$dst",
268 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
269 IIC_SR>, OpSize16;
270 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
271 "sar{l}\t$dst",
272 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
273 IIC_SR>, OpSize32;
274 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
275 "sar{q}\t$dst",
276 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
277 IIC_SR>;
278 } // Constraints = "$src = $dst", SchedRW
279
280
281 let SchedRW = [WriteShiftLd, WriteRMW] in {
282 let Uses = [CL] in {
283 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
284 "sar{b}\t{%cl, $dst|$dst, cl}",
285 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
286 IIC_SR>;
287 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
288 "sar{w}\t{%cl, $dst|$dst, cl}",
289 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
290 IIC_SR>, OpSize16;
291 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
292 "sar{l}\t{%cl, $dst|$dst, cl}",
293 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
294 IIC_SR>, OpSize32;
295 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
296 "sar{q}\t{%cl, $dst|$dst, cl}",
297 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
298 IIC_SR>;
299 }
300 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
301 "sar{b}\t{$src, $dst|$dst, $src}",
302 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
303 IIC_SR>;
304 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
305 "sar{w}\t{$src, $dst|$dst, $src}",
306 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
307 IIC_SR>, OpSize16;
308 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
309 "sar{l}\t{$src, $dst|$dst, $src}",
310 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
311 IIC_SR>, OpSize32;
312 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
313 "sar{q}\t{$src, $dst|$dst, $src}",
314 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
315 IIC_SR>;
316
317 // Shift by 1
318 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
319 "sar{b}\t$dst",
320 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
321 IIC_SR>;
322 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
323 "sar{w}\t$dst",
324 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
325 IIC_SR>, OpSize16;
326 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
327 "sar{l}\t$dst",
328 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
329 IIC_SR>, OpSize32;
330 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
331 "sar{q}\t$dst",
332 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
333 IIC_SR>;
334 } // SchedRW
335
336 //===----------------------------------------------------------------------===//
337 // Rotate instructions
338 //===----------------------------------------------------------------------===//
339
340 let hasSideEffects = 0 in {
341 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
342
343 let Uses = [CL, EFLAGS] in {
344 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
346 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
347 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
348 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
349 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
350 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
351 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
352 } // Uses = [CL, EFLAGS]
353
354 let Uses = [EFLAGS] in {
355 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
356 "rcl{b}\t$dst", [], IIC_SR>;
357 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
358 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
359 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
360 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
361 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
362 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
363 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
364 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
365 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
366 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
367 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
368 "rcl{q}\t$dst", [], IIC_SR>;
369 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
370 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
371 } // Uses = [EFLAGS]
372
373 let Uses = [CL, EFLAGS] in {
374 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
375 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
376 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
377 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
378 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
379 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
380 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
381 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
382 } // Uses = [CL, EFLAGS]
383
384 let Uses = [EFLAGS] in {
385 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
386 "rcr{b}\t$dst", [], IIC_SR>;
387 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
388 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
389 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
390 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
391 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
392 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
394 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
397 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
398 "rcr{q}\t$dst", [], IIC_SR>;
399 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
400 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
401 } // Uses = [EFLAGS]
402
403 } // Constraints = "$src = $dst"
404
405 let SchedRW = [WriteShiftLd, WriteRMW] in {
406 let Uses = [EFLAGS] in {
407 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
408 "rcl{b}\t$dst", [], IIC_SR>;
409 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt),
410 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
411 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
412 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
413 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt),
414 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
415 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
416 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
417 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt),
418 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
419 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
420 "rcl{q}\t$dst", [], IIC_SR>;
421 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt),
422 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
423
424 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
425 "rcr{b}\t$dst", [], IIC_SR>;
426 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt),
427 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
428 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
429 "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
430 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt),
431 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
432 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
433 "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
434 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt),
435 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
436 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
437 "rcr{q}\t$dst", [], IIC_SR>;
438 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt),
439 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
440 } // Uses = [EFLAGS]
441
442 let Uses = [CL, EFLAGS] in {
443 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
444 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
445 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
446 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
447 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
448 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
449 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
450 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
451
452 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
453 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
454 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
455 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
456 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
457 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
458 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
459 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
460 } // Uses = [CL, EFLAGS]
461 } // SchedRW
462 } // hasSideEffects = 0
463
464 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
465 // FIXME: provide shorter instructions when imm8 == 1
466 let Uses = [CL] in {
467 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
468 "rol{b}\t{%cl, $dst|$dst, cl}",
469 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
470 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
471 "rol{w}\t{%cl, $dst|$dst, cl}",
472 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
473 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
474 "rol{l}\t{%cl, $dst|$dst, cl}",
475 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
476 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
477 "rol{q}\t{%cl, $dst|$dst, cl}",
478 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
479 }
480
481 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
482 "rol{b}\t{$src2, $dst|$dst, $src2}",
483 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
484 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
485 "rol{w}\t{$src2, $dst|$dst, $src2}",
486 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
487 IIC_SR>, OpSize16;
488 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
489 "rol{l}\t{$src2, $dst|$dst, $src2}",
490 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
491 IIC_SR>, OpSize32;
492 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
493 (ins GR64:$src1, u8imm:$src2),
494 "rol{q}\t{$src2, $dst|$dst, $src2}",
495 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
496 IIC_SR>;
497
498 // Rotate by 1
499 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
500 "rol{b}\t$dst",
501 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
502 IIC_SR>;
503 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
504 "rol{w}\t$dst",
505 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
506 IIC_SR>, OpSize16;
507 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
508 "rol{l}\t$dst",
509 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
510 IIC_SR>, OpSize32;
511 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
512 "rol{q}\t$dst",
513 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
514 IIC_SR>;
515 } // Constraints = "$src = $dst", SchedRW
516
517 let SchedRW = [WriteShiftLd, WriteRMW] in {
518 let Uses = [CL] in {
519 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
520 "rol{b}\t{%cl, $dst|$dst, cl}",
521 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
522 IIC_SR>;
523 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
524 "rol{w}\t{%cl, $dst|$dst, cl}",
525 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
526 IIC_SR>, OpSize16;
527 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
528 "rol{l}\t{%cl, $dst|$dst, cl}",
529 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
530 IIC_SR>, OpSize32;
531 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
532 "rol{q}\t{%cl, $dst|$dst, cl}",
533 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
534 IIC_SR>;
535 }
536 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
537 "rol{b}\t{$src1, $dst|$dst, $src1}",
538 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
539 IIC_SR>;
540 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1),
541 "rol{w}\t{$src1, $dst|$dst, $src1}",
542 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
543 IIC_SR>, OpSize16;
544 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1),
545 "rol{l}\t{$src1, $dst|$dst, $src1}",
546 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
547 IIC_SR>, OpSize32;
548 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
549 "rol{q}\t{$src1, $dst|$dst, $src1}",
550 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
551 IIC_SR>;
552
553 // Rotate by 1
554 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
555 "rol{b}\t$dst",
556 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
557 IIC_SR>;
558 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
559 "rol{w}\t$dst",
560 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
561 IIC_SR>, OpSize16;
562 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
563 "rol{l}\t$dst",
564 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
565 IIC_SR>, OpSize32;
566 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
567 "rol{q}\t$dst",
568 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
569 IIC_SR>;
570 } // SchedRW
571
572 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
573 let Uses = [CL] in {
574 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
575 "ror{b}\t{%cl, $dst|$dst, cl}",
576 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
577 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
578 "ror{w}\t{%cl, $dst|$dst, cl}",
579 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
580 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
581 "ror{l}\t{%cl, $dst|$dst, cl}",
582 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
583 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
584 "ror{q}\t{%cl, $dst|$dst, cl}",
585 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
586 }
587
588 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
589 "ror{b}\t{$src2, $dst|$dst, $src2}",
590 [(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))],
591 IIC_SR>;
592 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
593 "ror{w}\t{$src2, $dst|$dst, $src2}",
594 [(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))],
595 IIC_SR>, OpSize16;
596 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
597 "ror{l}\t{$src2, $dst|$dst, $src2}",
598 [(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))],
599 IIC_SR>, OpSize32;
600 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
601 (ins GR64:$src1, u8imm:$src2),
602 "ror{q}\t{$src2, $dst|$dst, $src2}",
603 [(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))],
604 IIC_SR>;
605
606 // Rotate by 1
607 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
608 "ror{b}\t$dst",
609 [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))],
610 IIC_SR>;
611 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
612 "ror{w}\t$dst",
613 [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))],
614 IIC_SR>, OpSize16;
615 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
616 "ror{l}\t$dst",
617 [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))],
618 IIC_SR>, OpSize32;
619 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
620 "ror{q}\t$dst",
621 [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))],
622 IIC_SR>;
623 } // Constraints = "$src = $dst", SchedRW
624
625 let SchedRW = [WriteShiftLd, WriteRMW] in {
626 let Uses = [CL] in {
627 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
628 "ror{b}\t{%cl, $dst|$dst, cl}",
629 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
630 IIC_SR>;
631 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
632 "ror{w}\t{%cl, $dst|$dst, cl}",
633 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
634 IIC_SR>, OpSize16;
635 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
636 "ror{l}\t{%cl, $dst|$dst, cl}",
637 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
638 IIC_SR>, OpSize32;
639 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
640 "ror{q}\t{%cl, $dst|$dst, cl}",
641 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
642 IIC_SR>;
643 }
644 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
645 "ror{b}\t{$src, $dst|$dst, $src}",
646 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
647 IIC_SR>;
648 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src),
649 "ror{w}\t{$src, $dst|$dst, $src}",
650 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
651 IIC_SR>, OpSize16;
652 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src),
653 "ror{l}\t{$src, $dst|$dst, $src}",
654 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
655 IIC_SR>, OpSize32;
656 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
657 "ror{q}\t{$src, $dst|$dst, $src}",
658 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
659 IIC_SR>;
660
661 // Rotate by 1
662 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
663 "ror{b}\t$dst",
664 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
665 IIC_SR>;
666 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
667 "ror{w}\t$dst",
668 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
669 IIC_SR>, OpSize16;
670 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
671 "ror{l}\t$dst",
672 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
673 IIC_SR>, OpSize32;
674 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
675 "ror{q}\t$dst",
676 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
677 IIC_SR>;
678 } // SchedRW
679
680
681 //===----------------------------------------------------------------------===//
682 // Double shift instructions (generalizations of rotate)
683 //===----------------------------------------------------------------------===//
684
685 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
686
687 let Uses = [CL] in {
688 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
689 (ins GR16:$src1, GR16:$src2),
690 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
691 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
692 IIC_SHD16_REG_CL>,
693 TB, OpSize16;
694 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
695 (ins GR16:$src1, GR16:$src2),
696 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
697 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
698 IIC_SHD16_REG_CL>,
699 TB, OpSize16;
700 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
701 (ins GR32:$src1, GR32:$src2),
702 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
703 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
704 IIC_SHD32_REG_CL>, TB, OpSize32;
705 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
706 (ins GR32:$src1, GR32:$src2),
707 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
708 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
709 IIC_SHD32_REG_CL>, TB, OpSize32;
710 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
711 (ins GR64:$src1, GR64:$src2),
712 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
713 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
714 IIC_SHD64_REG_CL>,
715 TB;
716 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
717 (ins GR64:$src1, GR64:$src2),
718 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
719 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
720 IIC_SHD64_REG_CL>,
721 TB;
722 }
723
724 let isCommutable = 1 in { // These instructions commute to each other.
725 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
726 (outs GR16:$dst),
727 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
728 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
729 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
730 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
731 TB, OpSize16;
732 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
733 (outs GR16:$dst),
734 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
735 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
736 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
737 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
738 TB, OpSize16;
739 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
740 (outs GR32:$dst),
741 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
742 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
743 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
744 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
745 TB, OpSize32;
746 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
747 (outs GR32:$dst),
748 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
749 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
750 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
751 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
752 TB, OpSize32;
753 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
754 (outs GR64:$dst),
755 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
756 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
757 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
758 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
759 TB;
760 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
761 (outs GR64:$dst),
762 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
763 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
764 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
765 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
766 TB;
767 }
768 } // Constraints = "$src = $dst", SchedRW
769
770 let SchedRW = [WriteShiftLd, WriteRMW] in {
771 let Uses = [CL] in {
772 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
773 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
774 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
775 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
776 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
777 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
778 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
779 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
780
781 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
782 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
783 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
784 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
785 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
786 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
787 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
788 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
789
790 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
791 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
792 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
793 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
794 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
795 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
796 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
797 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
798 }
799
800 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
801 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
802 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
803 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
804 (i8 imm:$src3)), addr:$dst)],
805 IIC_SHD16_MEM_IM>,
806 TB, OpSize16;
807 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
808 (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
809 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
810 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
811 (i8 imm:$src3)), addr:$dst)],
812 IIC_SHD16_MEM_IM>,
813 TB, OpSize16;
814
815 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
816 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
817 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
818 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
819 (i8 imm:$src3)), addr:$dst)],
820 IIC_SHD32_MEM_IM>,
821 TB, OpSize32;
822 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
823 (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
824 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
825 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
826 (i8 imm:$src3)), addr:$dst)],
827 IIC_SHD32_MEM_IM>,
828 TB, OpSize32;
829
830 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
831 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
832 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
833 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
834 (i8 imm:$src3)), addr:$dst)],
835 IIC_SHD64_MEM_IM>,
836 TB;
837 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
838 (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
839 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
840 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
841 (i8 imm:$src3)), addr:$dst)],
842 IIC_SHD64_MEM_IM>,
843 TB;
844 } // SchedRW
845
846 } // Defs = [EFLAGS]
847
848 def ROT32L2R_imm8 : SDNodeXForm
849 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
850 return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
851 }]>;
852
853 def ROT64L2R_imm8 : SDNodeXForm
854 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
855 return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
856 }]>;
857
858 multiclass bmi_rotate {
859 let hasSideEffects = 0 in {
860 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
861 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
862 []>, TAXD, VEX, Sched<[WriteShift]>;
863 let mayLoad = 1 in
864 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
865 (ins x86memop:$src1, u8imm:$src2),
866 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
867 []>, TAXD, VEX, Sched<[WriteShiftLd]>;
868 }
869 }
870
871 multiclass bmi_shift {
872 let hasSideEffects = 0 in {
873 def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
874 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
875 VEX, Sched<[WriteShift]>;
876 let mayLoad = 1 in
877 def rm : I<0xF7, MRMSrcMem4VOp3,
878 (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
879 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
880 VEX, Sched<[WriteShiftLd,
881 // x86memop:$src1
882 ReadDefault, ReadDefault, ReadDefault, ReadDefault,
883 ReadDefault,
884 // RC:$src1
885 ReadAfterLd]>;
886 }
887 }
888
889 let Predicates = [HasBMI2] in {
890 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
891 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
892 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
893 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
894 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
895 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
896 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
897 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
898
899 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
900 let AddedComplexity = 10 in {
901 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
902 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
903 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
904 (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
905 }
906
907 def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
908 (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
909 def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
910 (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
911
912 // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
913 // immedidate shift, i.e. the following code is considered better
914 //
915 // mov %edi, %esi
916 // shl $imm, %esi
917 // ... %edi, ...
918 //
919 // than
920 //
921 // movb $imm, %sil
922 // shlx %sil, %edi, %esi
923 // ... %edi, ...
924 //
925 let AddedComplexity = 1 in {
926 def : Pat<(sra GR32:$src1, GR8:$src2),
927 (SARX32rr GR32:$src1,
928 (INSERT_SUBREG
929 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
930 def : Pat<(sra GR64:$src1, GR8:$src2),
931 (SARX64rr GR64:$src1,
932 (INSERT_SUBREG
933 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
934
935 def : Pat<(srl GR32:$src1, GR8:$src2),
936 (SHRX32rr GR32:$src1,
937 (INSERT_SUBREG
938 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
939 def : Pat<(srl GR64:$src1, GR8:$src2),
940 (SHRX64rr GR64:$src1,
941 (INSERT_SUBREG
942 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
943
944 def : Pat<(shl GR32:$src1, GR8:$src2),
945 (SHLX32rr GR32:$src1,
946 (INSERT_SUBREG
947 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
948 def : Pat<(shl GR64:$src1, GR8:$src2),
949 (SHLX64rr GR64:$src1,
950 (INSERT_SUBREG
951 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
952 }
953
954 // Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
955 //
956 // mov (%ecx), %esi
957 // shl $imm, $esi
958 //
959 // over
960 //
961 // movb $imm %al
962 // shlx %al, (%ecx), %esi
963 //
964 // As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
965 // optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.
966 }
None // RUN: llvm-mc -triple i386-unknown-unknown %s --show-encoding | FileCheck %s
1 // RUN: llvm-mc -triple i386-unknown-unknown -output-asm-variant=1 %s | FileCheck --check-prefix=INTEL %s
2
3 // CHECK: flds (%edi)
4 // CHECK: encoding: [0xd9,0x07]
5 flds (%edi)
6
7 // CHECK: filds (%edi)
8 // CHECK: encoding: [0xdf,0x07]
9 filds (%edi)
10
11 // CHECK: movb $127, 3735928559(%ebx,%ecx,8)
12 // CHECK: encoding: [0xc6,0x84,0xcb,0xef,0xbe,0xad,0xde,0x7f]
13 movb $0x7f,0xdeadbeef(%ebx,%ecx,8)
14
15 // CHECK: movb $127, 69
16 // CHECK: encoding: [0xc6,0x05,0x45,0x00,0x00,0x00,0x7f]
17 movb $0x7f,0x45
18
19 // CHECK: movb $127, 32493
20 // CHECK: encoding: [0xc6,0x05,0xed,0x7e,0x00,0x00,0x7f]
21 movb $0x7f,0x7eed
22
23 // CHECK: movb $127, 3133065982
24 // CHECK: encoding: [0xc6,0x05,0xfe,0xca,0xbe,0xba,0x7f]
25 movb $0x7f,0xbabecafe
26
27 // CHECK: movb $127, 305419896
28 // CHECK: encoding: [0xc6,0x05,0x78,0x56,0x34,0x12,0x7f]
29 movb $0x7f,0x12345678
30
31 // CHECK: movw $31438, 3735928559(%ebx,%ecx,8)
32 // CHECK: encoding: [0x66,0xc7,0x84,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
33 movw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
34
35 // CHECK: movw $31438, 69
36 // CHECK: encoding: [0x66,0xc7,0x05,0x45,0x00,0x00,0x00,0xce,0x7a]
37 movw $0x7ace,0x45
38
39 // CHECK: movw $31438, 32493
40 // CHECK: encoding: [0x66,0xc7,0x05,0xed,0x7e,0x00,0x00,0xce,0x7a]
41 movw $0x7ace,0x7eed
42
43 // CHECK: movw $31438, 3133065982
44 // CHECK: encoding: [0x66,0xc7,0x05,0xfe,0xca,0xbe,0xba,0xce,0x7a]
45 movw $0x7ace,0xbabecafe
46
47 // CHECK: movw $31438, 305419896
48 // CHECK: encoding: [0x66,0xc7,0x05,0x78,0x56,0x34,0x12,0xce,0x7a]
49 movw $0x7ace,0x12345678
50
51 // CHECK: movl $2063514302, 3735928559(%ebx,%ecx,8)
52 // CHECK: encoding: [0xc7,0x84,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
53 movl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
54
55 // CHECK: movl $2063514302, 69
56 // CHECK: encoding: [0xc7,0x05,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
57 movl $0x7afebabe,0x45
58
59 // CHECK: movl $2063514302, 32493
60 // CHECK: encoding: [0xc7,0x05,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
61 movl $0x7afebabe,0x7eed
62
63 // CHECK: movl $2063514302, 3133065982
64 // CHECK: encoding: [0xc7,0x05,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
65 movl $0x7afebabe,0xbabecafe
66
67 // CHECK: movl $2063514302, 305419896
68 // CHECK: encoding: [0xc7,0x05,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
69 movl $0x7afebabe,0x12345678
70
71 // CHECK: movl $324478056, 3735928559(%ebx,%ecx,8)
72 // CHECK: encoding: [0xc7,0x84,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
73 movl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
74
75 // CHECK: movl $324478056, 69
76 // CHECK: encoding: [0xc7,0x05,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
77 movl $0x13572468,0x45
78
79 // CHECK: movl $324478056, 32493
80 // CHECK: encoding: [0xc7,0x05,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
81 movl $0x13572468,0x7eed
82
83 // CHECK: movl $324478056, 3133065982
84 // CHECK: encoding: [0xc7,0x05,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
85 movl $0x13572468,0xbabecafe
86
87 // CHECK: movl $324478056, 305419896
88 // CHECK: encoding: [0xc7,0x05,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
89 movl $0x13572468,0x12345678
90
91 // CHECK: movsbl 3735928559(%ebx,%ecx,8), %ecx
92 // CHECK: encoding: [0x0f,0xbe,0x8c,0xcb,0xef,0xbe,0xad,0xde]
93 movsbl 0xdeadbeef(%ebx,%ecx,8),%ecx
94
95 // CHECK: movsbl 69, %ecx
96 // CHECK: encoding: [0x0f,0xbe,0x0d,0x45,0x00,0x00,0x00]
97 movsbl 0x45,%ecx
98
99 // CHECK: movsbl 32493, %ecx
100 // CHECK: encoding: [0x0f,0xbe,0x0d,0xed,0x7e,0x00,0x00]
101 movsbl 0x7eed,%ecx
102
103 // CHECK: movsbl 3133065982, %ecx
104 // CHECK: encoding: [0x0f,0xbe,0x0d,0xfe,0xca,0xbe,0xba]
105 movsbl 0xbabecafe,%ecx
106
107 // CHECK: movsbl 305419896, %ecx
108 // CHECK: encoding: [0x0f,0xbe,0x0d,0x78,0x56,0x34,0x12]
109 movsbl 0x12345678,%ecx
110
111 // CHECK: movsbw 3735928559(%ebx,%ecx,8), %bx
112 // CHECK: encoding: [0x66,0x0f,0xbe,0x9c,0xcb,0xef,0xbe,0xad,0xde]
113 movsbw 0xdeadbeef(%ebx,%ecx,8),%bx
114
115 // CHECK: movsbw 69, %bx
116 // CHECK: encoding: [0x66,0x0f,0xbe,0x1d,0x45,0x00,0x00,0x00]
117 movsbw 0x45,%bx
118
119 // CHECK: movsbw 32493, %bx
120 // CHECK: encoding: [0x66,0x0f,0xbe,0x1d,0xed,0x7e,0x00,0x00]
121 movsbw 0x7eed,%bx
122
123 // CHECK: movsbw 3133065982, %bx
124 // CHECK: encoding: [0x66,0x0f,0xbe,0x1d,0xfe,0xca,0xbe,0xba]
125 movsbw 0xbabecafe,%bx
126
127 // CHECK: movsbw 305419896, %bx
128 // CHECK: encoding: [0x66,0x0f,0xbe,0x1d,0x78,0x56,0x34,0x12]
129 movsbw 0x12345678,%bx
130
131 // CHECK: movswl 3735928559(%ebx,%ecx,8), %ecx
132 // CHECK: encoding: [0x0f,0xbf,0x8c,0xcb,0xef,0xbe,0xad,0xde]
133 movswl 0xdeadbeef(%ebx,%ecx,8),%ecx
134
135 // CHECK: movswl 69, %ecx
136 // CHECK: encoding: [0x0f,0xbf,0x0d,0x45,0x00,0x00,0x00]
137 movswl 0x45,%ecx
138
139 // CHECK: movswl 32493, %ecx
140 // CHECK: encoding: [0x0f,0xbf,0x0d,0xed,0x7e,0x00,0x00]
141 movswl 0x7eed,%ecx
142
143 // CHECK: movswl 3133065982, %ecx
144 // CHECK: encoding: [0x0f,0xbf,0x0d,0xfe,0xca,0xbe,0xba]
145 movswl 0xbabecafe,%ecx
146
147 // CHECK: movswl 305419896, %ecx
148 // CHECK: encoding: [0x0f,0xbf,0x0d,0x78,0x56,0x34,0x12]
149 movswl 0x12345678,%ecx
150
151 // CHECK: movzbl 3735928559(%ebx,%ecx,8), %ecx
152 // CHECK: encoding: [0x0f,0xb6,0x8c,0xcb,0xef,0xbe,0xad,0xde]
153 movzbl 0xdeadbeef(%ebx,%ecx,8),%ecx
154
155 // CHECK: movzbl 69, %ecx
156 // CHECK: encoding: [0x0f,0xb6,0x0d,0x45,0x00,0x00,0x00]
157 movzbl 0x45,%ecx
158
159 // CHECK: movzbl 32493, %ecx
160 // CHECK: encoding: [0x0f,0xb6,0x0d,0xed,0x7e,0x00,0x00]
161 movzbl 0x7eed,%ecx
162
163 // CHECK: movzbl 3133065982, %ecx
164 // CHECK: encoding: [0x0f,0xb6,0x0d,0xfe,0xca,0xbe,0xba]
165 movzbl 0xbabecafe,%ecx
166
167 // CHECK: movzbl 305419896, %ecx
168 // CHECK: encoding: [0x0f,0xb6,0x0d,0x78,0x56,0x34,0x12]
169 movzbl 0x12345678,%ecx
170
171 // CHECK: movzbw 3735928559(%ebx,%ecx,8), %bx
172 // CHECK: encoding: [0x66,0x0f,0xb6,0x9c,0xcb,0xef,0xbe,0xad,0xde]
173 movzbw 0xdeadbeef(%ebx,%ecx,8),%bx
174
175 // CHECK: movzbw 69, %bx
176 // CHECK: encoding: [0x66,0x0f,0xb6,0x1d,0x45,0x00,0x00,0x00]
177 movzbw 0x45,%bx
178
179 // CHECK: movzbw 32493, %bx
180 // CHECK: encoding: [0x66,0x0f,0xb6,0x1d,0xed,0x7e,0x00,0x00]
181 movzbw 0x7eed,%bx
182
183 // CHECK: movzbw 3133065982, %bx
184 // CHECK: encoding: [0x66,0x0f,0xb6,0x1d,0xfe,0xca,0xbe,0xba]
185 movzbw 0xbabecafe,%bx
186
187 // CHECK: movzbw 305419896, %bx
188 // CHECK: encoding: [0x66,0x0f,0xb6,0x1d,0x78,0x56,0x34,0x12]
189 movzbw 0x12345678,%bx
190
191 // CHECK: movzwl 3735928559(%ebx,%ecx,8), %ecx
192 // CHECK: encoding: [0x0f,0xb7,0x8c,0xcb,0xef,0xbe,0xad,0xde]
193 movzwl 0xdeadbeef(%ebx,%ecx,8),%ecx
194
195 // CHECK: movzwl 69, %ecx
196 // CHECK: encoding: [0x0f,0xb7,0x0d,0x45,0x00,0x00,0x00]
197 movzwl 0x45,%ecx
198
199 // CHECK: movzwl 32493, %ecx
200 // CHECK: encoding: [0x0f,0xb7,0x0d,0xed,0x7e,0x00,0x00]
201 movzwl 0x7eed,%ecx
202
203 // CHECK: movzwl 3133065982, %ecx
204 // CHECK: encoding: [0x0f,0xb7,0x0d,0xfe,0xca,0xbe,0xba]
205 movzwl 0xbabecafe,%ecx
206
207 // CHECK: movzwl 305419896, %ecx
208 // CHECK: encoding: [0x0f,0xb7,0x0d,0x78,0x56,0x34,0x12]
209 movzwl 0x12345678,%ecx
210
211 // CHECK: pushl 3735928559(%ebx,%ecx,8)
212 // CHECK: encoding: [0xff,0xb4,0xcb,0xef,0xbe,0xad,0xde]
213 pushl 0xdeadbeef(%ebx,%ecx,8)
214
215 // CHECK: pushw 32493
216 // CHECK: encoding: [0x66,0xff,0x35,0xed,0x7e,0x00,0x00]
217 pushw 0x7eed
218
219 // CHECK: pushl 3133065982
220 // CHECK: encoding: [0xff,0x35,0xfe,0xca,0xbe,0xba]
221 pushl 0xbabecafe
222
223 // CHECK: pushl 305419896
224 // CHECK: encoding: [0xff,0x35,0x78,0x56,0x34,0x12]
225 pushl 0x12345678
226
227 // CHECK: popl 3735928559(%ebx,%ecx,8)
228 // CHECK: encoding: [0x8f,0x84,0xcb,0xef,0xbe,0xad,0xde]
229 popl 0xdeadbeef(%ebx,%ecx,8)
230
231 // CHECK: popw 32493
232 // CHECK: encoding: [0x66,0x8f,0x05,0xed,0x7e,0x00,0x00]
233 popw 0x7eed
234
235 // CHECK: popl 3133065982
236 // CHECK: encoding: [0x8f,0x05,0xfe,0xca,0xbe,0xba]
237 popl 0xbabecafe
238
239 // CHECK: popl 305419896
240 // CHECK: encoding: [0x8f,0x05,0x78,0x56,0x34,0x12]
241 popl 0x12345678
242
243 // CHECK: clc
244 // CHECK: encoding: [0xf8]
245 clc
246
247 // CHECK: cld
248 // CHECK: encoding: [0xfc]
249 cld
250
251 // CHECK: cli
252 // CHECK: encoding: [0xfa]
253 cli
254
255 // CHECK: clts
256 // CHECK: encoding: [0x0f,0x06]
257 clts
258
259 // CHECK: cmc
260 // CHECK: encoding: [0xf5]
261 cmc
262
263 // CHECK: lahf
264 // CHECK: encoding: [0x9f]
265 lahf
266
267 // CHECK: sahf
268 // CHECK: encoding: [0x9e]
269 sahf
270
271 // CHECK: stc
272 // CHECK: encoding: [0xf9]
273 stc
274
275 // CHECK: std
276 // CHECK: encoding: [0xfd]
277 std
278
279 // CHECK: sti
280 // CHECK: encoding: [0xfb]
281 sti
282
283 // CHECK: salc
284 // CHECK: encoding: [0xd6]
285 salc
286
287 // CHECK: addb $254, 3735928559(%ebx,%ecx,8)
288 // CHECK: encoding: [0x80,0x84,0xcb,0xef,0xbe,0xad,0xde,0xfe]
289 addb $0xfe,0xdeadbeef(%ebx,%ecx,8)
290
291 // CHECK: addb $254, 69
292 // CHECK: encoding: [0x80,0x05,0x45,0x00,0x00,0x00,0xfe]
293 addb $0xfe,0x45
294
295 // CHECK: addb $254, 32493
296 // CHECK: encoding: [0x80,0x05,0xed,0x7e,0x00,0x00,0xfe]
297 addb $0xfe,0x7eed
298
299 // CHECK: addb $254, 3133065982
300 // CHECK: encoding: [0x80,0x05,0xfe,0xca,0xbe,0xba,0xfe]
301 addb $0xfe,0xbabecafe
302
303 // CHECK: addb $254, 305419896
304 // CHECK: encoding: [0x80,0x05,0x78,0x56,0x34,0x12,0xfe]
305 addb $0xfe,0x12345678
306
307 // CHECK: addb $127, 3735928559(%ebx,%ecx,8)
308 // CHECK: encoding: [0x80,0x84,0xcb,0xef,0xbe,0xad,0xde,0x7f]
309 addb $0x7f,0xdeadbeef(%ebx,%ecx,8)
310
311 // CHECK: addb $127, 69
312 // CHECK: encoding: [0x80,0x05,0x45,0x00,0x00,0x00,0x7f]
313 addb $0x7f,0x45
314
315 // CHECK: addb $127, 32493
316 // CHECK: encoding: [0x80,0x05,0xed,0x7e,0x00,0x00,0x7f]
317 addb $0x7f,0x7eed
318
319 // CHECK: addb $127, 3133065982
320 // CHECK: encoding: [0x80,0x05,0xfe,0xca,0xbe,0xba,0x7f]
321 addb $0x7f,0xbabecafe
322
323 // CHECK: addb $127, 305419896
324 // CHECK: encoding: [0x80,0x05,0x78,0x56,0x34,0x12,0x7f]
325 addb $0x7f,0x12345678
326
327 // CHECK: addw $31438, 3735928559(%ebx,%ecx,8)
328 // CHECK: encoding: [0x66,0x81,0x84,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
329 addw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
330
331 // CHECK: addw $31438, 69
332 // CHECK: encoding: [0x66,0x81,0x05,0x45,0x00,0x00,0x00,0xce,0x7a]
333 addw $0x7ace,0x45
334
335 // CHECK: addw $31438, 32493
336 // CHECK: encoding: [0x66,0x81,0x05,0xed,0x7e,0x00,0x00,0xce,0x7a]
337 addw $0x7ace,0x7eed
338
339 // CHECK: addw $31438, 3133065982
340 // CHECK: encoding: [0x66,0x81,0x05,0xfe,0xca,0xbe,0xba,0xce,0x7a]
341 addw $0x7ace,0xbabecafe
342
343 // CHECK: addw $31438, 305419896
344 // CHECK: encoding: [0x66,0x81,0x05,0x78,0x56,0x34,0x12,0xce,0x7a]
345 addw $0x7ace,0x12345678
346
347 // CHECK: addl $2063514302, 3735928559(%ebx,%ecx,8)
348 // CHECK: encoding: [0x81,0x84,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
349 addl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
350
351 // CHECK: addl $2063514302, 69
352 // CHECK: encoding: [0x81,0x05,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
353 addl $0x7afebabe,0x45
354
355 // CHECK: addl $2063514302, 32493
356 // CHECK: encoding: [0x81,0x05,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
357 addl $0x7afebabe,0x7eed
358
359 // CHECK: addl $2063514302, 3133065982
360 // CHECK: encoding: [0x81,0x05,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
361 addl $0x7afebabe,0xbabecafe
362
363 // CHECK: addl $2063514302, 305419896
364 // CHECK: encoding: [0x81,0x05,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
365 addl $0x7afebabe,0x12345678
366
367 // CHECK: addl $324478056, 3735928559(%ebx,%ecx,8)
368 // CHECK: encoding: [0x81,0x84,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
369 addl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
370
371 // CHECK: addl $324478056, 69
372 // CHECK: encoding: [0x81,0x05,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
373 addl $0x13572468,0x45
374
375 // CHECK: addl $324478056, 32493
376 // CHECK: encoding: [0x81,0x05,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
377 addl $0x13572468,0x7eed
378
379 // CHECK: addl $324478056, 3133065982
380 // CHECK: encoding: [0x81,0x05,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
381 addl $0x13572468,0xbabecafe
382
383 // CHECK: addl $324478056, 305419896
384 // CHECK: encoding: [0x81,0x05,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
385 addl $0x13572468,0x12345678
386
387 // CHECK: incl 3735928559(%ebx,%ecx,8)
388 // CHECK: encoding: [0xff,0x84,0xcb,0xef,0xbe,0xad,0xde]
389 incl 0xdeadbeef(%ebx,%ecx,8)
390
391 // CHECK: incw 32493
392 // CHECK: encoding: [0x66,0xff,0x05,0xed,0x7e,0x00,0x00]
393 incw 0x7eed
394
395 // CHECK: incl 3133065982
396 // CHECK: encoding: [0xff,0x05,0xfe,0xca,0xbe,0xba]
397 incl 0xbabecafe
398
399 // CHECK: incl 305419896
400 // CHECK: encoding: [0xff,0x05,0x78,0x56,0x34,0x12]
401 incl 0x12345678
402
403 // CHECK: subb $254, 3735928559(%ebx,%ecx,8)
404 // CHECK: encoding: [0x80,0xac,0xcb,0xef,0xbe,0xad,0xde,0xfe]
405 subb $0xfe,0xdeadbeef(%ebx,%ecx,8)
406
407 // CHECK: subb $254, 69
408 // CHECK: encoding: [0x80,0x2d,0x45,0x00,0x00,0x00,0xfe]
409 subb $0xfe,0x45
410
411 // CHECK: subb $254, 32493
412 // CHECK: encoding: [0x80,0x2d,0xed,0x7e,0x00,0x00,0xfe]
413 subb $0xfe,0x7eed
414
415 // CHECK: subb $254, 3133065982
416 // CHECK: encoding: [0x80,0x2d,0xfe,0xca,0xbe,0xba,0xfe]
417 subb $0xfe,0xbabecafe
418
419 // CHECK: subb $254, 305419896
420 // CHECK: encoding: [0x80,0x2d,0x78,0x56,0x34,0x12,0xfe]
421 subb $0xfe,0x12345678
422
423 // CHECK: subb $127, 3735928559(%ebx,%ecx,8)
424 // CHECK: encoding: [0x80,0xac,0xcb,0xef,0xbe,0xad,0xde,0x7f]
425 subb $0x7f,0xdeadbeef(%ebx,%ecx,8)
426
427 // CHECK: subb $127, 69
428 // CHECK: encoding: [0x80,0x2d,0x45,0x00,0x00,0x00,0x7f]
429 subb $0x7f,0x45
430
431 // CHECK: subb $127, 32493
432 // CHECK: encoding: [0x80,0x2d,0xed,0x7e,0x00,0x00,0x7f]
433 subb $0x7f,0x7eed
434
435 // CHECK: subb $127, 3133065982
436 // CHECK: encoding: [0x80,0x2d,0xfe,0xca,0xbe,0xba,0x7f]
437 subb $0x7f,0xbabecafe
438
439 // CHECK: subb $127, 305419896
440 // CHECK: encoding: [0x80,0x2d,0x78,0x56,0x34,0x12,0x7f]
441 subb $0x7f,0x12345678
442
443 // CHECK: subw $31438, 3735928559(%ebx,%ecx,8)
444 // CHECK: encoding: [0x66,0x81,0xac,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
445 subw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
446
447 // CHECK: subw $31438, 69
448 // CHECK: encoding: [0x66,0x81,0x2d,0x45,0x00,0x00,0x00,0xce,0x7a]
449 subw $0x7ace,0x45
450
451 // CHECK: subw $31438, 32493
452 // CHECK: encoding: [0x66,0x81,0x2d,0xed,0x7e,0x00,0x00,0xce,0x7a]
453 subw $0x7ace,0x7eed
454
455 // CHECK: subw $31438, 3133065982
456 // CHECK: encoding: [0x66,0x81,0x2d,0xfe,0xca,0xbe,0xba,0xce,0x7a]
457 subw $0x7ace,0xbabecafe
458
459 // CHECK: subw $31438, 305419896
460 // CHECK: encoding: [0x66,0x81,0x2d,0x78,0x56,0x34,0x12,0xce,0x7a]
461 subw $0x7ace,0x12345678
462
463 // CHECK: subl $2063514302, 3735928559(%ebx,%ecx,8)
464 // CHECK: encoding: [0x81,0xac,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
465 subl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
466
467 // CHECK: subl $2063514302, 69
468 // CHECK: encoding: [0x81,0x2d,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
469 subl $0x7afebabe,0x45
470
471 // CHECK: subl $2063514302, 32493
472 // CHECK: encoding: [0x81,0x2d,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
473 subl $0x7afebabe,0x7eed
474
475 // CHECK: subl $2063514302, 3133065982
476 // CHECK: encoding: [0x81,0x2d,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
477 subl $0x7afebabe,0xbabecafe
478
479 // CHECK: subl $2063514302, 305419896
480 // CHECK: encoding: [0x81,0x2d,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
481 subl $0x7afebabe,0x12345678
482
483 // CHECK: subl $324478056, 3735928559(%ebx,%ecx,8)
484 // CHECK: encoding: [0x81,0xac,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
485 subl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
486
487 // CHECK: subl $324478056, 69
488 // CHECK: encoding: [0x81,0x2d,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
489 subl $0x13572468,0x45
490
491 // CHECK: subl $324478056, 32493
492 // CHECK: encoding: [0x81,0x2d,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
493 subl $0x13572468,0x7eed
494
495 // CHECK: subl $324478056, 3133065982
496 // CHECK: encoding: [0x81,0x2d,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
497 subl $0x13572468,0xbabecafe
498
499 // CHECK: subl $324478056, 305419896
500 // CHECK: encoding: [0x81,0x2d,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
501 subl $0x13572468,0x12345678
502
503 // CHECK: decl 3735928559(%ebx,%ecx,8)
504 // CHECK: encoding: [0xff,0x8c,0xcb,0xef,0xbe,0xad,0xde]
505 decl 0xdeadbeef(%ebx,%ecx,8)
506
507 // CHECK: decw 32493
508 // CHECK: encoding: [0x66,0xff,0x0d,0xed,0x7e,0x00,0x00]
509 decw 0x7eed
510
511 // CHECK: decl 3133065982
512 // CHECK: encoding: [0xff,0x0d,0xfe,0xca,0xbe,0xba]
513 decl 0xbabecafe
514
515 // CHECK: decl 305419896
516 // CHECK: encoding: [0xff,0x0d,0x78,0x56,0x34,0x12]
517 decl 0x12345678
518
519 // CHECK: sbbb $254, 3735928559(%ebx,%ecx,8)
520 // CHECK: encoding: [0x80,0x9c,0xcb,0xef,0xbe,0xad,0xde,0xfe]
521 sbbb $0xfe,0xdeadbeef(%ebx,%ecx,8)
522
523 // CHECK: sbbb $254, 69
524 // CHECK: encoding: [0x80,0x1d,0x45,0x00,0x00,0x00,0xfe]
525 sbbb $0xfe,0x45
526
527 // CHECK: sbbb $254, 32493
528 // CHECK: encoding: [0x80,0x1d,0xed,0x7e,0x00,0x00,0xfe]
529 sbbb $0xfe,0x7eed
530
531 // CHECK: sbbb $254, 3133065982
532 // CHECK: encoding: [0x80,0x1d,0xfe,0xca,0xbe,0xba,0xfe]
533 sbbb $0xfe,0xbabecafe
534
535 // CHECK: sbbb $254, 305419896
536 // CHECK: encoding: [0x80,0x1d,0x78,0x56,0x34,0x12,0xfe]
537 sbbb $0xfe,0x12345678
538
539 // CHECK: sbbb $127, 3735928559(%ebx,%ecx,8)
540 // CHECK: encoding: [0x80,0x9c,0xcb,0xef,0xbe,0xad,0xde,0x7f]
541 sbbb $0x7f,0xdeadbeef(%ebx,%ecx,8)
542
543 // CHECK: sbbb $127, 69
544 // CHECK: encoding: [0x80,0x1d,0x45,0x00,0x00,0x00,0x7f]
545 sbbb $0x7f,0x45
546
547 // CHECK: sbbb $127, 32493
548 // CHECK: encoding: [0x80,0x1d,0xed,0x7e,0x00,0x00,0x7f]
549 sbbb $0x7f,0x7eed
550
551 // CHECK: sbbb $127, 3133065982
552 // CHECK: encoding: [0x80,0x1d,0xfe,0xca,0xbe,0xba,0x7f]
553 sbbb $0x7f,0xbabecafe
554
555 // CHECK: sbbb $127, 305419896
556 // CHECK: encoding: [0x80,0x1d,0x78,0x56,0x34,0x12,0x7f]
557 sbbb $0x7f,0x12345678
558
559 // CHECK: sbbw $31438, 3735928559(%ebx,%ecx,8)
560 // CHECK: encoding: [0x66,0x81,0x9c,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
561 sbbw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
562
563 // CHECK: sbbw $31438, 69
564 // CHECK: encoding: [0x66,0x81,0x1d,0x45,0x00,0x00,0x00,0xce,0x7a]
565 sbbw $0x7ace,0x45
566
567 // CHECK: sbbw $31438, 32493
568 // CHECK: encoding: [0x66,0x81,0x1d,0xed,0x7e,0x00,0x00,0xce,0x7a]
569 sbbw $0x7ace,0x7eed
570
571 // CHECK: sbbw $31438, 3133065982
572 // CHECK: encoding: [0x66,0x81,0x1d,0xfe,0xca,0xbe,0xba,0xce,0x7a]
573 sbbw $0x7ace,0xbabecafe
574
575 // CHECK: sbbw $31438, 305419896
576 // CHECK: encoding: [0x66,0x81,0x1d,0x78,0x56,0x34,0x12,0xce,0x7a]
577 sbbw $0x7ace,0x12345678
578
579 // CHECK: sbbl $2063514302, 3735928559(%ebx,%ecx,8)
580 // CHECK: encoding: [0x81,0x9c,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
581 sbbl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
582
583 // CHECK: sbbl $2063514302, 69
584 // CHECK: encoding: [0x81,0x1d,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
585 sbbl $0x7afebabe,0x45
586
587 // CHECK: sbbl $2063514302, 32493
588 // CHECK: encoding: [0x81,0x1d,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
589 sbbl $0x7afebabe,0x7eed
590
591 // CHECK: sbbl $2063514302, 3133065982
592 // CHECK: encoding: [0x81,0x1d,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
593 sbbl $0x7afebabe,0xbabecafe
594
595 // CHECK: sbbl $2063514302, 305419896
596 // CHECK: encoding: [0x81,0x1d,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
597 sbbl $0x7afebabe,0x12345678
598
599 // CHECK: sbbl $324478056, 3735928559(%ebx,%ecx,8)
600 // CHECK: encoding: [0x81,0x9c,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
601 sbbl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
602
603 // CHECK: sbbl $324478056, 69
604 // CHECK: encoding: [0x81,0x1d,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
605 sbbl $0x13572468,0x45
606
607 // CHECK: sbbl $324478056, 32493
608 // CHECK: encoding: [0x81,0x1d,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
609 sbbl $0x13572468,0x7eed
610
611 // CHECK: sbbl $324478056, 3133065982
612 // CHECK: encoding: [0x81,0x1d,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
613 sbbl $0x13572468,0xbabecafe
614
615 // CHECK: sbbl $324478056, 305419896
616 // CHECK: encoding: [0x81,0x1d,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
617 sbbl $0x13572468,0x12345678
618
619 // CHECK: cmpb $254, 3735928559(%ebx,%ecx,8)
620 // CHECK: encoding: [0x80,0xbc,0xcb,0xef,0xbe,0xad,0xde,0xfe]
621 cmpb $0xfe,0xdeadbeef(%ebx,%ecx,8)
622
623 // CHECK: cmpb $254, 69
624 // CHECK: encoding: [0x80,0x3d,0x45,0x00,0x00,0x00,0xfe]
625 cmpb $0xfe,0x45
626
627 // CHECK: cmpb $254, 32493
628 // CHECK: encoding: [0x80,0x3d,0xed,0x7e,0x00,0x00,0xfe]
629 cmpb $0xfe,0x7eed
630
631 // CHECK: cmpb $254, 3133065982
632 // CHECK: encoding: [0x80,0x3d,0xfe,0xca,0xbe,0xba,0xfe]
633 cmpb $0xfe,0xbabecafe
634
635 // CHECK: cmpb $254, 305419896
636 // CHECK: encoding: [0x80,0x3d,0x78,0x56,0x34,0x12,0xfe]
637 cmpb $0xfe,0x12345678
638
639 // CHECK: cmpb $127, 3735928559(%ebx,%ecx,8)
640 // CHECK: encoding: [0x80,0xbc,0xcb,0xef,0xbe,0xad,0xde,0x7f]
641 cmpb $0x7f,0xdeadbeef(%ebx,%ecx,8)
642
643 // CHECK: cmpb $127, 69
644 // CHECK: encoding: [0x80,0x3d,0x45,0x00,0x00,0x00,0x7f]
645 cmpb $0x7f,0x45
646
647 // CHECK: cmpb $127, 32493
648 // CHECK: encoding: [0x80,0x3d,0xed,0x7e,0x00,0x00,0x7f]
649 cmpb $0x7f,0x7eed
650
651 // CHECK: cmpb $127, 3133065982
652 // CHECK: encoding: [0x80,0x3d,0xfe,0xca,0xbe,0xba,0x7f]
653 cmpb $0x7f,0xbabecafe
654
655 // CHECK: cmpb $127, 305419896
656 // CHECK: encoding: [0x80,0x3d,0x78,0x56,0x34,0x12,0x7f]
657 cmpb $0x7f,0x12345678
658
659 // CHECK: cmpw $31438, 3735928559(%ebx,%ecx,8)
660 // CHECK: encoding: [0x66,0x81,0xbc,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
661 cmpw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
662
663 // CHECK: cmpw $31438, 69
664 // CHECK: encoding: [0x66,0x81,0x3d,0x45,0x00,0x00,0x00,0xce,0x7a]
665 cmpw $0x7ace,0x45
666
667 // CHECK: cmpw $31438, 32493
668 // CHECK: encoding: [0x66,0x81,0x3d,0xed,0x7e,0x00,0x00,0xce,0x7a]
669 cmpw $0x7ace,0x7eed
670
671 // CHECK: cmpw $31438, 3133065982
672 // CHECK: encoding: [0x66,0x81,0x3d,0xfe,0xca,0xbe,0xba,0xce,0x7a]
673 cmpw $0x7ace,0xbabecafe
674
675 // CHECK: cmpw $31438, 305419896
676 // CHECK: encoding: [0x66,0x81,0x3d,0x78,0x56,0x34,0x12,0xce,0x7a]
677 cmpw $0x7ace,0x12345678
678
679 // CHECK: cmpl $2063514302, 3735928559(%ebx,%ecx,8)
680 // CHECK: encoding: [0x81,0xbc,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
681 cmpl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
682
683 // CHECK: cmpl $2063514302, 69
684 // CHECK: encoding: [0x81,0x3d,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
685 cmpl $0x7afebabe,0x45
686
687 // CHECK: cmpl $2063514302, 32493
688 // CHECK: encoding: [0x81,0x3d,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
689 cmpl $0x7afebabe,0x7eed
690
691 // CHECK: cmpl $2063514302, 3133065982
692 // CHECK: encoding: [0x81,0x3d,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
693 cmpl $0x7afebabe,0xbabecafe
694
695 // CHECK: cmpl $2063514302, 305419896
696 // CHECK: encoding: [0x81,0x3d,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
697 cmpl $0x7afebabe,0x12345678
698
699 // CHECK: cmpl $324478056, 3735928559(%ebx,%ecx,8)
700 // CHECK: encoding: [0x81,0xbc,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
701 cmpl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
702
703 // CHECK: cmpl $324478056, 69
704 // CHECK: encoding: [0x81,0x3d,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
705 cmpl $0x13572468,0x45
706
707 // CHECK: cmpl $324478056, 32493
708 // CHECK: encoding: [0x81,0x3d,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
709 cmpl $0x13572468,0x7eed
710
711 // CHECK: cmpl $324478056, 3133065982
712 // CHECK: encoding: [0x81,0x3d,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
713 cmpl $0x13572468,0xbabecafe
714
715 // CHECK: cmpl $324478056, 305419896
716 // CHECK: encoding: [0x81,0x3d,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
717 cmpl $0x13572468,0x12345678
718
719 // CHECK: testb $127, 3735928559(%ebx,%ecx,8)
720 // CHECK: encoding: [0xf6,0x84,0xcb,0xef,0xbe,0xad,0xde,0x7f]
721 testb $0x7f,0xdeadbeef(%ebx,%ecx,8)
722
723 // CHECK: testb $127, 69
724 // CHECK: encoding: [0xf6,0x05,0x45,0x00,0x00,0x00,0x7f]
725 testb $0x7f,0x45
726
727 // CHECK: testb $127, 32493
728 // CHECK: encoding: [0xf6,0x05,0xed,0x7e,0x00,0x00,0x7f]
729 testb $0x7f,0x7eed
730
731 // CHECK: testb $127, 3133065982
732 // CHECK: encoding: [0xf6,0x05,0xfe,0xca,0xbe,0xba,0x7f]
733 testb $0x7f,0xbabecafe
734
735 // CHECK: testb $127, 305419896
736 // CHECK: encoding: [0xf6,0x05,0x78,0x56,0x34,0x12,0x7f]
737 testb $0x7f,0x12345678
738
739 // CHECK: testw $31438, 3735928559(%ebx,%ecx,8)
740 // CHECK: encoding: [0x66,0xf7,0x84,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
741 testw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
742
743 // CHECK: testw $31438, 69
744 // CHECK: encoding: [0x66,0xf7,0x05,0x45,0x00,0x00,0x00,0xce,0x7a]
745 testw $0x7ace,0x45
746
747 // CHECK: testw $31438, 32493
748 // CHECK: encoding: [0x66,0xf7,0x05,0xed,0x7e,0x00,0x00,0xce,0x7a]
749 testw $0x7ace,0x7eed
750
751 // CHECK: testw $31438, 3133065982
752 // CHECK: encoding: [0x66,0xf7,0x05,0xfe,0xca,0xbe,0xba,0xce,0x7a]
753 testw $0x7ace,0xbabecafe
754
755 // CHECK: testw $31438, 305419896
756 // CHECK: encoding: [0x66,0xf7,0x05,0x78,0x56,0x34,0x12,0xce,0x7a]
757 testw $0x7ace,0x12345678
758
759 // CHECK: testl $2063514302, 3735928559(%ebx,%ecx,8)
760 // CHECK: encoding: [0xf7,0x84,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
761 testl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
762
763 // CHECK: testl $2063514302, 69
764 // CHECK: encoding: [0xf7,0x05,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
765 testl $0x7afebabe,0x45
766
767 // CHECK: testl $2063514302, 32493
768 // CHECK: encoding: [0xf7,0x05,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
769 testl $0x7afebabe,0x7eed
770
771 // CHECK: testl $2063514302, 3133065982
772 // CHECK: encoding: [0xf7,0x05,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
773 testl $0x7afebabe,0xbabecafe
774
775 // CHECK: testl $2063514302, 305419896
776 // CHECK: encoding: [0xf7,0x05,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
777 testl $0x7afebabe,0x12345678
778
779 // CHECK: testl $324478056, 3735928559(%ebx,%ecx,8)
780 // CHECK: encoding: [0xf7,0x84,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
781 testl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
782
783 // CHECK: testl $324478056, 69
784 // CHECK: encoding: [0xf7,0x05,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
785 testl $0x13572468,0x45
786
787 // CHECK: testl $324478056, 32493
788 // CHECK: encoding: [0xf7,0x05,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
789 testl $0x13572468,0x7eed
790
791 // CHECK: testl $324478056, 3133065982
792 // CHECK: encoding: [0xf7,0x05,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
793 testl $0x13572468,0xbabecafe
794
795 // CHECK: testl $324478056, 305419896
796 // CHECK: encoding: [0xf7,0x05,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
797 testl $0x13572468,0x12345678
798
799 // CHECK: andb $254, 3735928559(%ebx,%ecx,8)
800 // CHECK: encoding: [0x80,0xa4,0xcb,0xef,0xbe,0xad,0xde,0xfe]
801 andb $0xfe,0xdeadbeef(%ebx,%ecx,8)
802
803 // CHECK: andb $254, 69
804 // CHECK: encoding: [0x80,0x25,0x45,0x00,0x00,0x00,0xfe]
805 andb $0xfe,0x45
806
807 // CHECK: andb $254, 32493
808 // CHECK: encoding: [0x80,0x25,0xed,0x7e,0x00,0x00,0xfe]
809 andb $0xfe,0x7eed
810
811 // CHECK: andb $254, 3133065982
812 // CHECK: encoding: [0x80,0x25,0xfe,0xca,0xbe,0xba,0xfe]
813 andb $0xfe,0xbabecafe
814
815 // CHECK: andb $254, 305419896
816 // CHECK: encoding: [0x80,0x25,0x78,0x56,0x34,0x12,0xfe]
817 andb $0xfe,0x12345678
818
819 // CHECK: andb $127, 3735928559(%ebx,%ecx,8)
820 // CHECK: encoding: [0x80,0xa4,0xcb,0xef,0xbe,0xad,0xde,0x7f]
821 andb $0x7f,0xdeadbeef(%ebx,%ecx,8)
822
823 // CHECK: andb $127, 69
824 // CHECK: encoding: [0x80,0x25,0x45,0x00,0x00,0x00,0x7f]
825 andb $0x7f,0x45
826
827 // CHECK: andb $127, 32493
828 // CHECK: encoding: [0x80,0x25,0xed,0x7e,0x00,0x00,0x7f]
829 andb $0x7f,0x7eed
830
831 // CHECK: andb $127, 3133065982
832 // CHECK: encoding: [0x80,0x25,0xfe,0xca,0xbe,0xba,0x7f]
833 andb $0x7f,0xbabecafe
834
835 // CHECK: andb $127, 305419896
836 // CHECK: encoding: [0x80,0x25,0x78,0x56,0x34,0x12,0x7f]
837 andb $0x7f,0x12345678
838
839 // CHECK: andw $31438, 3735928559(%ebx,%ecx,8)
840 // CHECK: encoding: [0x66,0x81,0xa4,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
841 andw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
842
843 // CHECK: andw $31438, 69
844 // CHECK: encoding: [0x66,0x81,0x25,0x45,0x00,0x00,0x00,0xce,0x7a]
845 andw $0x7ace,0x45
846
847 // CHECK: andw $31438, 32493
848 // CHECK: encoding: [0x66,0x81,0x25,0xed,0x7e,0x00,0x00,0xce,0x7a]
849 andw $0x7ace,0x7eed
850
851 // CHECK: andw $31438, 3133065982
852 // CHECK: encoding: [0x66,0x81,0x25,0xfe,0xca,0xbe,0xba,0xce,0x7a]
853 andw $0x7ace,0xbabecafe
854
855 // CHECK: andw $31438, 305419896
856 // CHECK: encoding: [0x66,0x81,0x25,0x78,0x56,0x34,0x12,0xce,0x7a]
857 andw $0x7ace,0x12345678
858
859 // CHECK: andl $2063514302, 3735928559(%ebx,%ecx,8)
860 // CHECK: encoding: [0x81,0xa4,0xcb,0xef,0xbe,0xad,0xde,0xbe,0xba,0xfe,0x7a]
861 andl $0x7afebabe,0xdeadbeef(%ebx,%ecx,8)
862
863 // CHECK: andl $2063514302, 69
864 // CHECK: encoding: [0x81,0x25,0x45,0x00,0x00,0x00,0xbe,0xba,0xfe,0x7a]
865 andl $0x7afebabe,0x45
866
867 // CHECK: andl $2063514302, 32493
868 // CHECK: encoding: [0x81,0x25,0xed,0x7e,0x00,0x00,0xbe,0xba,0xfe,0x7a]
869 andl $0x7afebabe,0x7eed
870
871 // CHECK: andl $2063514302, 3133065982
872 // CHECK: encoding: [0x81,0x25,0xfe,0xca,0xbe,0xba,0xbe,0xba,0xfe,0x7a]
873 andl $0x7afebabe,0xbabecafe
874
875 // CHECK: andl $2063514302, 305419896
876 // CHECK: encoding: [0x81,0x25,0x78,0x56,0x34,0x12,0xbe,0xba,0xfe,0x7a]
877 andl $0x7afebabe,0x12345678
878
879 // CHECK: andl $324478056, 3735928559(%ebx,%ecx,8)
880 // CHECK: encoding: [0x81,0xa4,0xcb,0xef,0xbe,0xad,0xde,0x68,0x24,0x57,0x13]
881 andl $0x13572468,0xdeadbeef(%ebx,%ecx,8)
882
883 // CHECK: andl $324478056, 69
884 // CHECK: encoding: [0x81,0x25,0x45,0x00,0x00,0x00,0x68,0x24,0x57,0x13]
885 andl $0x13572468,0x45
886
887 // CHECK: andl $324478056, 32493
888 // CHECK: encoding: [0x81,0x25,0xed,0x7e,0x00,0x00,0x68,0x24,0x57,0x13]
889 andl $0x13572468,0x7eed
890
891 // CHECK: andl $324478056, 3133065982
892 // CHECK: encoding: [0x81,0x25,0xfe,0xca,0xbe,0xba,0x68,0x24,0x57,0x13]
893 andl $0x13572468,0xbabecafe
894
895 // CHECK: andl $324478056, 305419896
896 // CHECK: encoding: [0x81,0x25,0x78,0x56,0x34,0x12,0x68,0x24,0x57,0x13]
897 andl $0x13572468,0x12345678
898
899 // CHECK: orb $254, 3735928559(%ebx,%ecx,8)
900 // CHECK: encoding: [0x80,0x8c,0xcb,0xef,0xbe,0xad,0xde,0xfe]
901 orb $0xfe,0xdeadbeef(%ebx,%ecx,8)
902
903 // CHECK: orb $254, 69
904 // CHECK: encoding: [0x80,0x0d,0x45,0x00,0x00,0x00,0xfe]
905 orb $0xfe,0x45
906
907 // CHECK: orb $254, 32493
908 // CHECK: encoding: [0x80,0x0d,0xed,0x7e,0x00,0x00,0xfe]
909 orb $0xfe,0x7eed
910
911 // CHECK: orb $254, 3133065982
912 // CHECK: encoding: [0x80,0x0d,0xfe,0xca,0xbe,0xba,0xfe]
913 orb $0xfe,0xbabecafe
914
915 // CHECK: orb $254, 305419896
916 // CHECK: encoding: [0x80,0x0d,0x78,0x56,0x34,0x12,0xfe]
917 orb $0xfe,0x12345678
918
919 // CHECK: orb $127, 3735928559(%ebx,%ecx,8)
920 // CHECK: encoding: [0x80,0x8c,0xcb,0xef,0xbe,0xad,0xde,0x7f]
921 orb $0x7f,0xdeadbeef(%ebx,%ecx,8)
922
923 // CHECK: orb $127, 69
924 // CHECK: encoding: [0x80,0x0d,0x45,0x00,0x00,0x00,0x7f]
925 orb $0x7f,0x45
926
927 // CHECK: orb $127, 32493
928 // CHECK: encoding: [0x80,0x0d,0xed,0x7e,0x00,0x00,0x7f]
929 orb $0x7f,0x7eed
930
931 // CHECK: orb $127, 3133065982
932 // CHECK: encoding: [0x80,0x0d,0xfe,0xca,0xbe,0xba,0x7f]
933 orb $0x7f,0xbabecafe
934
935 // CHECK: orb $127, 305419896
936 // CHECK: encoding: [0x80,0x0d,0x78,0x56,0x34,0x12,0x7f]
937 orb $0x7f,0x12345678
938
939 // CHECK: orw $31438, 3735928559(%ebx,%ecx,8)
940 // CHECK: encoding: [0x66,0x81,0x8c,0xcb,0xef,0xbe,0xad,0xde,0xce,0x7a]
941 orw $0x7ace,0xdeadbeef(%ebx,%ecx,8)
942
943 // CHECK: orw $31438, 69
944 // CHECK: encoding: [0x66,0x81,0x0d,0x45,0x00,0x00,0x00,0xce,0x7a]
945 orw $0x7ace,0x45
946
947 // CHECK: orw $31438, 32493
948 // CHECK: encoding: [0x66,0x81,0x0d,0xed,0x7e,0x00,0x00,0xce,0x7a]
949 orw $0x7ace,0x7eed
950
951 // CHECK: orw $31438, 3133065982
952 // CHECK: encoding: [0x66,0x81,0x0d,0xfe,0xca,0xbe,0xba,0xce,0x7a]
953 orw $0x7ace,0xbabecafe
954
955 // CHECK: orw $31438, 305419896
956 // CHECK: encoding: [0x66,0x81,0x0d,0x78,0x56