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[ARM] Add a batch of similarly encoded MVE instructions. Summary: This adds the `MVE_qDest_qSrc` superclass and all instructions that inherit from it. It's not the complete class of _everything_ with a q-register as both destination and source; it's a subset of them that all have similar encodings (but it would have been hopelessly unwieldy to call it anything like MVE_111x11100). This category includes add/sub with carry; long multiplies; halving multiplies; multiply and accumulate, and some more complex instructions. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364037 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
5 changed file(s) with 1277 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
24032403
24042404 // end of MVE compares
24052405
2406 // start of MVE_qDest_qSrc
2407
2408 class MVE_qDest_qSrc
2409 string ops, vpred_ops vpred, string cstr,
2410 list pattern=[]>
2411 : MVE_p
2412 ops, vpred, cstr, pattern> {
2413 bits<4> Qd;
2414 bits<4> Qm;
2415
2416 let Inst{25-23} = 0b100;
2417 let Inst{22} = Qd{3};
2418 let Inst{15-13} = Qd{2-0};
2419 let Inst{11-9} = 0b111;
2420 let Inst{6} = 0b0;
2421 let Inst{5} = Qm{3};
2422 let Inst{4} = 0b0;
2423 let Inst{3-1} = Qm{2-0};
2424 }
2425
2426 class MVE_VQxDMLxDH
2427 string suffix, bits<2> size, list pattern=[]>
2428 : MVE_qDest_qSrc
2429 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2430 vpred_r, "", pattern> {
2431 bits<4> Qn;
2432
2433 let Inst{28} = subtract;
2434 let Inst{21-20} = size;
2435 let Inst{19-17} = Qn{2-0};
2436 let Inst{16} = 0b0;
2437 let Inst{12} = exch;
2438 let Inst{8} = 0b0;
2439 let Inst{7} = Qn{3};
2440 let Inst{0} = round;
2441 }
2442
2443 multiclass MVE_VQxDMLxDH_multi
2444 bit round, bit subtract> {
2445 def s8 : MVE_VQxDMLxDH;
2446 def s16 : MVE_VQxDMLxDH;
2447 def s32 : MVE_VQxDMLxDH;
2448 }
2449
2450 defm MVE_VQDMLADH : MVE_VQxDMLxDH_multi<"vqdmladh", 0b0, 0b0, 0b0>;
2451 defm MVE_VQDMLADHX : MVE_VQxDMLxDH_multi<"vqdmladhx", 0b1, 0b0, 0b0>;
2452 defm MVE_VQRDMLADH : MVE_VQxDMLxDH_multi<"vqrdmladh", 0b0, 0b1, 0b0>;
2453 defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
2454 defm MVE_VQDMLSDH : MVE_VQxDMLxDH_multi<"vqdmlsdh", 0b0, 0b0, 0b1>;
2455 defm MVE_VQDMLSDHX : MVE_VQxDMLxDH_multi<"vqdmlsdhx", 0b1, 0b0, 0b1>;
2456 defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
2457 defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
2458
2459 class MVE_VCMUL pattern=[]>
2460 : MVE_qDest_qSrc
2461 (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
2462 "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
2463 bits<4> Qn;
2464 bits<2> rot;
2465
2466 let Inst{28} = size;
2467 let Inst{21-20} = 0b11;
2468 let Inst{19-17} = Qn{2-0};
2469 let Inst{16} = 0b0;
2470 let Inst{12} = rot{1};
2471 let Inst{8} = 0b0;
2472 let Inst{7} = Qn{3};
2473 let Inst{0} = rot{0};
2474
2475 let Predicates = [HasMVEFloat];
2476 }
2477
2478 def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
2479 def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1>;
2480
2481 class MVE_VMULL bits_21_20,
2482 bit T, list pattern=[]>
2483 : MVE_qDest_qSrc
2484 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2485 vpred_r, "", pattern> {
2486 bits<4> Qd;
2487 bits<4> Qn;
2488 bits<4> Qm;
2489
2490 let Inst{28} = bit_28;
2491 let Inst{21-20} = bits_21_20;
2492 let Inst{19-17} = Qn{2-0};
2493 let Inst{16} = 0b1;
2494 let Inst{12} = T;
2495 let Inst{8} = 0b0;
2496 let Inst{7} = Qn{3};
2497 let Inst{0} = 0b0;
2498 }
2499
2500 multiclass MVE_VMULL_multi
2501 bit bit_28, bits<2> bits_21_20> {
2502 def bh : MVE_VMULL;
2503 def th : MVE_VMULL;
2504 }
2505
2506 // For integer multiplies, bits 21:20 encode size, and bit 28 signedness.
2507 // For polynomial multiplies, bits 21:20 take the unused value 0b11, and
2508 // bit 28 switches to encoding the size.
2509
2510 defm MVE_VMULLs8 : MVE_VMULL_multi<"vmull", "s8", 0b0, 0b00>;
2511 defm MVE_VMULLs16 : MVE_VMULL_multi<"vmull", "s16", 0b0, 0b01>;
2512 defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10>;
2513 defm MVE_VMULLu8 : MVE_VMULL_multi<"vmull", "u8", 0b1, 0b00>;
2514 defm MVE_VMULLu16 : MVE_VMULL_multi<"vmull", "u16", 0b1, 0b01>;
2515 defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10>;
2516 defm MVE_VMULLp8 : MVE_VMULL_multi<"vmull", "p8", 0b0, 0b11>;
2517 defm MVE_VMULLp16 : MVE_VMULL_multi<"vmull", "p16", 0b1, 0b11>;
2518
2519 class MVE_VxMULH size,
2520 bit round, list pattern=[]>
2521 : MVE_qDest_qSrc
2522 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2523 vpred_r, "", pattern> {
2524 bits<4> Qn;
2525
2526 let Inst{28} = U;
2527 let Inst{21-20} = size;
2528 let Inst{19-17} = Qn{2-0};
2529 let Inst{16} = 0b1;
2530 let Inst{12} = round;
2531 let Inst{8} = 0b0;
2532 let Inst{7} = Qn{3};
2533 let Inst{0} = 0b1;
2534 }
2535
2536 def MVE_VMULHs8 : MVE_VxMULH<"vmulh", "s8", 0b0, 0b00, 0b0>;
2537 def MVE_VMULHs16 : MVE_VxMULH<"vmulh", "s16", 0b0, 0b01, 0b0>;
2538 def MVE_VMULHs32 : MVE_VxMULH<"vmulh", "s32", 0b0, 0b10, 0b0>;
2539 def MVE_VMULHu8 : MVE_VxMULH<"vmulh", "u8", 0b1, 0b00, 0b0>;
2540 def MVE_VMULHu16 : MVE_VxMULH<"vmulh", "u16", 0b1, 0b01, 0b0>;
2541 def MVE_VMULHu32 : MVE_VxMULH<"vmulh", "u32", 0b1, 0b10, 0b0>;
2542
2543 def MVE_VRMULHs8 : MVE_VxMULH<"vrmulh", "s8", 0b0, 0b00, 0b1>;
2544 def MVE_VRMULHs16 : MVE_VxMULH<"vrmulh", "s16", 0b0, 0b01, 0b1>;
2545 def MVE_VRMULHs32 : MVE_VxMULH<"vrmulh", "s32", 0b0, 0b10, 0b1>;
2546 def MVE_VRMULHu8 : MVE_VxMULH<"vrmulh", "u8", 0b1, 0b00, 0b1>;
2547 def MVE_VRMULHu16 : MVE_VxMULH<"vrmulh", "u16", 0b1, 0b01, 0b1>;
2548 def MVE_VRMULHu32 : MVE_VxMULH<"vrmulh", "u32", 0b1, 0b10, 0b1>;
2549
2550 class MVE_VxMOVxN
2551 bits<2> size, bit T, list pattern=[]>
2552 : MVE_qDest_qSrc
2553 (ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
2554 vpred_n, "$Qd = $Qd_src", pattern> {
2555
2556 let Inst{28} = bit_28;
2557 let Inst{21-20} = 0b11;
2558 let Inst{19-18} = size;
2559 let Inst{17} = bit_17;
2560 let Inst{16} = 0b1;
2561 let Inst{12} = T;
2562 let Inst{8} = 0b0;
2563 let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
2564 let Inst{0} = 0b1;
2565 }
2566
2567 multiclass MVE_VxMOVxN_halves
2568 bit bit_28, bit bit_17, bits<2> size> {
2569 def bh : MVE_VxMOVxN;
2570 def th : MVE_VxMOVxN;
2571 }
2572
2573 defm MVE_VMOVNi16 : MVE_VxMOVxN_halves<"vmovn", "i16", 0b1, 0b0, 0b00>;
2574 defm MVE_VMOVNi32 : MVE_VxMOVxN_halves<"vmovn", "i32", 0b1, 0b0, 0b01>;
2575 defm MVE_VQMOVNs16 : MVE_VxMOVxN_halves<"vqmovn", "s16", 0b0, 0b1, 0b00>;
2576 defm MVE_VQMOVNs32 : MVE_VxMOVxN_halves<"vqmovn", "s32", 0b0, 0b1, 0b01>;
2577 defm MVE_VQMOVNu16 : MVE_VxMOVxN_halves<"vqmovn", "u16", 0b1, 0b1, 0b00>;
2578 defm MVE_VQMOVNu32 : MVE_VxMOVxN_halves<"vqmovn", "u32", 0b1, 0b1, 0b01>;
2579 defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
2580 defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
2581
2582 class MVE_VCVT_ff
2583 list pattern=[]>
2584 : MVE_qDest_qSrc
2585 "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
2586 let Inst{28} = op;
2587 let Inst{21-16} = 0b111111;
2588 let Inst{12} = T;
2589 let Inst{8-7} = 0b00;
2590 let Inst{0} = 0b1;
2591
2592 let Predicates = [HasMVEFloat];
2593 }
2594
2595 multiclass MVE_VCVT_ff_halves {
2596 def bh : MVE_VCVT_ff<"vcvtb", suffix, op, 0b0>;
2597 def th : MVE_VCVT_ff<"vcvtt", suffix, op, 0b1>;
2598 }
2599
2600 defm MVE_VCVTf16f32 : MVE_VCVT_ff_halves<"f16.f32", 0b0>;
2601 defm MVE_VCVTf32f16 : MVE_VCVT_ff_halves<"f32.f16", 0b1>;
2602
2603 class MVE_VxCADD size, bit halve,
2604 list pattern=[]>
2605 : MVE_qDest_qSrc
2606 (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
2607 "$Qd, $Qn, $Qm, $rot", vpred_r, "",
2608 pattern> {
2609 bits<4> Qn;
2610 bit rot;
2611
2612 let Inst{28} = halve;
2613 let Inst{21-20} = size;
2614 let Inst{19-17} = Qn{2-0};
2615 let Inst{16} = 0b0;
2616 let Inst{12} = rot;
2617 let Inst{8} = 0b1;
2618 let Inst{7} = Qn{3};
2619 let Inst{0} = 0b0;
2620 }
2621
2622 def MVE_VCADDi8 : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
2623 def MVE_VCADDi16 : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
2624 def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1>;
2625
2626 def MVE_VHCADDs8 : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
2627 def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
2628 def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0>;
2629
2630 class MVE_VADCSBC
2631 dag carryin, list pattern=[]>
2632 : MVE_qDest_qSrc
2633 !con((ins MQPR:$Qn, MQPR:$Qm), carryin),
2634 "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
2635 bits<4> Qn;
2636
2637 let Inst{28} = subtract;
2638 let Inst{21-20} = 0b11;
2639 let Inst{19-17} = Qn{2-0};
2640 let Inst{16} = 0b0;
2641 let Inst{12} = I;
2642 let Inst{8} = 0b1;
2643 let Inst{7} = Qn{3};
2644 let Inst{0} = 0b0;
2645
2646 // Custom decoder method in order to add the FPSCR operand(s), which
2647 // Tablegen won't do right
2648 let DecoderMethod = "DecodeMVEVADCInstruction";
2649 }
2650
2651 def MVE_VADC : MVE_VADCSBC<"vadc", 0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
2652 def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
2653
2654 def MVE_VSBC : MVE_VADCSBC<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
2655 def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
2656
2657 class MVE_VQDMULL
2658 list pattern=[]>
2659 : MVE_qDest_qSrc
2660 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2661 vpred_r, "", pattern> {
2662 bits<4> Qn;
2663
2664 let Inst{28} = size;
2665 let Inst{21-20} = 0b11;
2666 let Inst{19-17} = Qn{2-0};
2667 let Inst{16} = 0b0;
2668 let Inst{12} = T;
2669 let Inst{8} = 0b1;
2670 let Inst{7} = Qn{3};
2671 let Inst{0} = 0b1;
2672 }
2673
2674 multiclass MVE_VQDMULL_halves {
2675 def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0>;
2676 def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1>;
2677 }
2678
2679 defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
2680 defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1>;
2681
2682 // end of mve_qDest_qSrc
2683
24062684 class MVE_VPT size, dag iops, string asm, list pattern=[]>
24072685 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
24082686 bits<3> fc;
59655965 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
59665966 Mnemonic == "vmule" || Mnemonic == "vmult" ||
59675967 Mnemonic == "vrintne" ||
5968 Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
59685969 Mnemonic.startswith("vq")))) {
59695970 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59705971 if (CC != ~0U) {
60096010 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
60106011 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
60116012 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6012 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vcvt") {
6013 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6014 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6015 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6016 Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
60136017 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
60146018 if (CC != ~0U) {
60156019 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
66826686 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
66836687 Operands.insert(Operands.begin(),
66846688 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
6689 } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
6690 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6691 // Another hack, this time to distinguish between scalar predicated vmul
6692 // with 'lt' predication code and the vector instruction vmullt with
6693 // vector predication code "none"
6694 Operands.erase(Operands.begin() + 1);
6695 Operands.erase(Operands.begin());
6696 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6697 Operands.insert(Operands.begin(),
6698 ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
66856699 }
66866700 // For vmov and vcmp, as mentioned earlier, we did not add the vector
66876701 // predication code, since these may contain operands that require
75387552 if (RegList.size() < 1 || RegList.size() > 16)
75397553 return Error(Operands[3]->getStartLoc(),
75407554 "list of registers must be at least 1 and at most 16");
7555 break;
7556 }
7557 case ARM::MVE_VQDMULLs32bh:
7558 case ARM::MVE_VQDMULLs32th:
7559 case ARM::MVE_VCMULf32:
7560 case ARM::MVE_VMULLs32bh:
7561 case ARM::MVE_VMULLs32th:
7562 case ARM::MVE_VMULLu32bh:
7563 case ARM::MVE_VMULLu32th:
7564 case ARM::MVE_VQDMLADHs32:
7565 case ARM::MVE_VQDMLADHXs32:
7566 case ARM::MVE_VQRDMLADHs32:
7567 case ARM::MVE_VQRDMLADHXs32:
7568 case ARM::MVE_VQDMLSDHs32:
7569 case ARM::MVE_VQDMLSDHXs32:
7570 case ARM::MVE_VQRDMLSDHs32:
7571 case ARM::MVE_VQRDMLSDHXs32: {
7572 if (Operands[3]->getReg() == Operands[4]->getReg()) {
7573 return Error (Operands[3]->getStartLoc(),
7574 "Qd register and Qn register can't be identical");
7575 }
7576 if (Operands[3]->getReg() == Operands[5]->getReg()) {
7577 return Error (Operands[3]->getStartLoc(),
7578 "Qd register and Qm register can't be identical");
7579 }
75417580 break;
75427581 }
75437582 }
310310 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
311311 uint64_t Address, const void *Decoder);
312312 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
313315 uint64_t Address, const void *Decoder);
314316 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
315317 uint64_t Address, const void *Decoder);
34613463 return S;
34623464 }
34633465
3466 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3467 uint64_t Address, const void *Decoder) {
3468 DecodeStatus S = MCDisassembler::Success;
3469
3470 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3471 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3472 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3473 return MCDisassembler::Fail;
3474 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3475
3476 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3477 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3478 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3479 return MCDisassembler::Fail;
3480 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3481 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3482 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3483 return MCDisassembler::Fail;
3484 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3485 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3486 Inst.addOperand(MCOperand::createImm(Qd));
3487
3488 return S;
3489 }
3490
34643491 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
34653492 uint64_t Address, const void *Decoder) {
34663493 DecodeStatus S = MCDisassembler::Success;
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5
6 # CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
7 # CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
8 vcvtb.f16.f32 q1, q4
9
10 # CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
11 # CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
12 vcvtt.f32.f16 q0, q1
13
14 # CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
15 # CHECK-NOFP-NOT: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
16 vcvtt.f64.f16 d0, s0
17
18 # CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
19 # CHECK-NOFP-NOT: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
20 vcvtt.f16.f64 s1, d2
21
22 # CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
23 # CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
24 vcvtt.f16.f32 q1, q4
25
26 # CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
27 # CHECK-NOFP: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
28 vqdmladhx.s8 q1, q6, q6
29
30 # CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
31 # CHECK-NOFP: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
32 vqdmladhx.s16 q0, q1, q4
33
34 # CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
35 # CHECK-NOFP: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
36 vqdmladhx.s32 q0, q3, q7
37
38 # CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
39 # CHECK-NOFP: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
40 vqdmladh.s8 q0, q1, q1
41
42 # CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
43 # CHECK-NOFP: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
44 vqdmladh.s16 q0, q2, q2
45
46 # CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
47 # CHECK-NOFP: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
48 vqdmladh.s32 q1, q5, q7
49
50 # CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
51 # CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
52 vqrdmladhx.s8 q0, q7, q0
53
54 # CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
55 # CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
56 vqrdmladhx.s16 q0, q0, q1
57
58 # CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
59 # CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
60 vqrdmladhx.s32 q1, q0, q4
61
62 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
63 vqrdmladhx.s32 q1, q1, q0
64
65 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
66 vqrdmladhx.s32 q1, q0, q1
67
68 # CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
69 # CHECK-NOFP: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
70 vqrdmladh.s8 q0, q6, q2
71
72 # CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
73 # CHECK-NOFP: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
74 vqrdmladh.s16 q1, q5, q4
75
76 # CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
77 # CHECK-NOFP: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
78 vqrdmladh.s32 q0, q2, q2
79
80 # CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
81 # CHECK-NOFP: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
82 vqdmlsdhx.s8 q1, q4, q7
83
84 # CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
85 # CHECK-NOFP: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
86 vqdmlsdhx.s16 q0, q2, q5
87
88 # CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
89 # CHECK-NOFP: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
90 vqdmlsdhx.s32 q3, q4, q6
91
92 # CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
93 # CHECK-NOFP: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
94 vqdmlsdh.s8 q0, q3, q6
95
96 # CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
97 # CHECK-NOFP: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
98 vqdmlsdh.s16 q0, q4, q1
99
100 # CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
101 # CHECK-NOFP: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
102 vqdmlsdh.s32 q2, q5, q0
103
104 # CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
105 # CHECK-NOFP: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
106 vqrdmlsdhx.s8 q0, q3, q1
107
108 # CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
109 # CHECK-NOFP: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
110 vqrdmlsdhx.s16 q0, q1, q4
111
112 # CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
113 # CHECK-NOFP: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
114 vqrdmlsdhx.s32 q1, q6, q3
115
116 # CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
117 # CHECK-NOFP: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
118 vqrdmlsdh.s8 q3, q3, q0
119
120 # CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
121 # CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
122 vqrdmlsdh.s16 q0, q7, q4
123
124 # CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
125 # CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
126 vqrdmlsdh.s32 q0, q6, q7
127
128 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
129 vqrdmlsdh.s32 q0, q0, q7
130
131 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
132 vqrdmlsdh.s32 q0, q6, q0
133
134 # CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
135 # CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
136 vcmul.f16 q0, q1, q2, #90
137
138 # CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
139 # CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
140 vcmul.f16 q6, q2, q5, #0
141
142 # CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
143 # CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
144 vcmul.f16 q1, q0, q5, #90
145
146 # CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
147 # CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
148 vcmul.f16 q1, q0, q5, #180
149
150 # CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
151 # CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
152 vcmul.f16 q1, q0, q5, #270
153
154 # CHECK: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
155 # CHECK-NOFP-NOT: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
156 vcmul.f16 q1, q0, q1, #270
157
158 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
159 vcmul.f16 q1, q0, q5, #300
160
161 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
162 vcmul.f32 q1, q1, q5, #0
163
164 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
165 vcmul.f32 q1, q5, q1, #0
166
167 # CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
168 # CHECK-NOFP-NOT: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
169 vcmul.f32 q1, q7, q5, #0
170
171 # CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
172 # CHECK-NOFP-NOT: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
173 vcmul.f32 q3, q4, q2, #90
174
175 # CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
176 # CHECK-NOFP-NOT: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
177 vcmul.f32 q5, q1, q3, #180
178
179 # CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
180 # CHECK-NOFP-NOT: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
181 vcmul.f32 q0, q7, q4, #270
182
183 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
184 vcmul.f32 q1, q0, q5, #300
185
186 # CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
187 # CHECK-NOFP: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
188 vmullb.s8 q2, q6, q0
189
190 # CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
191 # CHECK-NOFP: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
192 vmullb.s16 q3, q4, q3
193
194 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
195 vmullb.s32 q3, q4, q3
196
197 # CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
198 # CHECK-NOFP: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
199 vmullb.s32 q3, q5, q6
200
201 # CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
202 # CHECK-NOFP: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
203 vmullt.s8 q0, q6, q2
204
205 # CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
206 # CHECK-NOFP: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
207 vmullt.s16 q0, q0, q2
208
209 # CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
210 # CHECK-NOFP: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
211 vmullt.s32 q2, q4, q4
212
213 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
214 vmullt.s32 q4, q4, q2
215
216 # CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
217 # CHECK-NOFP: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
218 vmullb.p8 q2, q3, q7
219
220 # CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
221 # CHECK-NOFP: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
222 vmullb.p16 q0, q1, q3
223
224 # CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
225 # CHECK-NOFP: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
226 vmullt.p8 q1, q1, q7
227
228 # CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
229 # CHECK-NOFP: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
230 vmullt.p16 q0, q7, q7
231
232 # CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
233 # CHECK-NOFP: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
234 vmulh.s8 q0, q4, q5
235
236 # CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
237 # CHECK-NOFP: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
238 vmulh.s16 q0, q7, q4
239
240 # CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
241 # CHECK-NOFP: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
242 vmulh.s32 q0, q7, q4
243
244 # CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
245 # CHECK-NOFP: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
246 vmulh.u8 q3, q5, q2
247
248 # CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
249 # CHECK-NOFP: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
250 vmulh.u16 q2, q7, q4
251
252 # CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
253 # CHECK-NOFP: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
254 vmulh.u32 q1, q3, q2
255
256 # CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
257 # CHECK-NOFP: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
258 vrmulh.s8 q1, q1, q2
259
260 # CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
261 # CHECK-NOFP: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
262 vrmulh.s16 q1, q1, q2
263
264 # CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
265 # CHECK-NOFP: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
266 vrmulh.s32 q3, q1, q0
267
268 # CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
269 # CHECK-NOFP: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
270 vrmulh.u8 q1, q6, q0
271
272 # CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
273 # CHECK-NOFP: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
274 vrmulh.u16 q4, q3, q6
275
276 # CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
277 # CHECK-NOFP: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
278 vrmulh.u32 q1, q2, q2
279
280 # CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
281 # CHECK-NOFP: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
282 vqmovnb.s16 q0, q1
283
284 # CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
285 # CHECK-NOFP: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
286 vqmovnt.s16 q2, q0
287
288 # CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
289 # CHECK-NOFP: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
290 vqmovnb.s32 q0, q5
291
292 # CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
293 # CHECK-NOFP: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
294 vqmovnt.s32 q0, q1
295
296 # CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
297 # CHECK-NOFP: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
298 vqmovnb.u16 q0, q4
299
300 # CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
301 # CHECK-NOFP: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
302 vqmovnt.u16 q0, q7
303
304 # CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
305 # CHECK-NOFP: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
306 vqmovnb.u32 q0, q4
307
308 # CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
309 # CHECK-NOFP: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
310 vqmovnt.u32 q0, q2
311
312 # CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
313 # CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
314 vcvtb.f16.f32 q1, q4
315
316 # CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
317 # CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
318 vcvtt.f16.f32 q1, q4
319
320 # CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
321 # CHECK-NOFP-NOT: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
322 vcvtb.f32.f16 q0, q3
323
324 # CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
325 # CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
326 vcvtt.f32.f16 q0, q1
327
328 # CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
329 # CHECK-NOFP: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
330 vqmovunb.s16 q0, q3
331
332 # CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
333 # CHECK-NOFP: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
334 vqmovunt.s16 q4, q1
335
336 # CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
337 # CHECK-NOFP: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
338 vqmovunb.s32 q1, q7
339
340 # CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
341 # CHECK-NOFP: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
342 vqmovunt.s32 q0, q2
343
344 # CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
345 # CHECK-NOFP: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
346 vmovnb.i16 q1, q5
347
348 # CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
349 # CHECK-NOFP: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
350 vmovnt.i16 q0, q0
351
352 # CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
353 # CHECK-NOFP: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
354 vmovnb.i32 q1, q0
355
356 # CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
357 # CHECK-NOFP: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
358 vmovnt.i32 q3, q3
359
360 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
361 vhcadd.s8 q3, q7, q5, #0
362
363 # CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
364 # CHECK-NOFP: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
365 vhcadd.s8 q3, q7, q5, #90
366
367 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
368 vhcadd.s8 q3, q7, q5, #0
369
370 # CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
371 # CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
372 vhcadd.s16 q0, q0, q6, #90
373
374 # CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
375 # CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
376 vhcadd.s16 q0, q0, q6, #90
377
378 # CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
379 # CHECK-NOFP: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
380 vhcadd.s16 q3, q1, q0, #270
381
382 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
383 vhcadd.s32 q3, q4, q5, #0
384
385 # CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
386 # CHECK-NOFP: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
387 vhcadd.s32 q3, q4, q5, #90
388
389 # CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
390 # CHECK-NOFP: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
391 vhcadd.s32 q6, q7, q2, #270
392
393 # CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
394 # CHECK-NOFP: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
395 vadc.i32 q1, q0, q2
396
397 # CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
398 # CHECK-NOFP: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
399 vadci.i32 q0, q1, q1
400
401 # CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
402 # CHECK-NOFP: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
403 vcadd.i8 q1, q0, q2, #90
404
405 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
406 vcadd.i8 q1, q0, q2, #0
407
408 # CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
409 # CHECK-NOFP: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
410 vcadd.i16 q0, q2, q3, #90
411
412 # CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
413 # CHECK-NOFP: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
414 vcadd.i16 q0, q5, q5, #270
415
416 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
417 vcadd.i16 q1, q0, q2, #0
418
419 # CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
420 # CHECK-NOFP: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
421 vcadd.i32 q4, q2, q5, #90
422
423 # CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
424 # CHECK-NOFP: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
425 vcadd.i32 q5, q5, q0, #270
426
427 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
428 vcadd.i32 q4, q2, q5, #0
429
430 # CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
431 # CHECK-NOFP: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
432 vsbc.i32 q3, q1, q1
433
434 # CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
435 # CHECK-NOFP: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
436 vsbci.i32 q2, q6, q2
437
438 # CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
439 # CHECK-NOFP: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
440 vqdmullb.s16 q0, q4, q5
441
442 # CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
443 # CHECK-NOFP: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
444 vqdmullt.s16 q0, q6, q5
445
446 # CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
447 # CHECK-NOFP: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
448 vqdmullb.s32 q0, q3, q7
449
450 # CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
451 # CHECK-NOFP: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
452 vqdmullt.s32 q0, q7, q5
453
454 # CHECK: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
455 # CHECK-NOFP: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
456 vqdmullb.s16 q0, q1, q0
457
458 # CHECK: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
459 # CHECK-NOFP: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
460 vqdmullt.s16 q0, q0, q5
461
462 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
463 vqdmullb.s32 q0, q1, q0
464
465 vqdmullt.s16 q0, q1, q2
466 # CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
467 # CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
468
469 vpste
470 vqdmulltt.s32 q0, q1, q2
471 vqdmullbe.s16 q0, q1, q2
472 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
473 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
474 # CHECK: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
475 # CHECK-NOFP: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
476 # CHECK: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
477 # CHECK-NOFP: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
478
479 vpste
480 vmulltt.p8 q0, q1, q2
481 vmullbe.p16 q0, q1, q2
482 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
483 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
484 # CHECK: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
485 # CHECK-NOFP: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
486 # CHECK: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
487 # CHECK-NOFP: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
488
489 # ----------------------------------------------------------------------
490 # The following tests have to go last because of the NOFP-NOT checks inside the
491 # VPT block.
492
493 vpste
494 vcmult.f16 q0, q1, q2, #180
495 vcmule.f16 q0, q1, q2, #180
496 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
497 # CHECK: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
498 # CHECK-NOFP-NOT: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
499 # CHECK: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
500 # CHECK-NOFP-NOT: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
501
502 vpstet
503 vcvtbt.f16.f32 q0, q1
504 vcvtne.s16.f16 q0, q1
505 vcvtmt.s16.f16 q0, q1
506 # CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
507 # CHECK: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
508 # CHECK-NOFP-NOT: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
509 # CHECK: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
510 # CHECK-NOFP-NOT: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
511 # CHECK: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
512 # CHECK-NOFP-NOT: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
513
514 vpte.f32 lt, q3, r1
515 vcvttt.f16.f32 q2, q0
516 vcvtte.f32.f16 q1, q0
517 # CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
518 # CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
519 # CHECK: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
520 # CHECK-NOFP-NOT: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
521 # CHECK: vcvtte.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x3e]
522
523 vpte.f32 lt, q3, r1
524 vcvtbt.f16.f32 q2, q0
525 vcvtbe.f32.f16 q1, q0
526 # CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
527 # CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
528 # CHECK: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
529 # CHECK-NOFP-NOT: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
530 # CHECK: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
531 # CHECK-NOFP-NOT: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
532
533 ite eq
534 vcvtteq.f16.f32 s0, s1
535 vcvttne.f16.f32 s0, s1
536 # CHECK: ite eq @ encoding: [0x0c,0xbf]
537 # CHECK: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
538 # CHECK-NOFP-NOT: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
539 # CHECK: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
540 # CHECK-NOFP-NOT: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0x0c,0xee,0x0c,0x3e]
7
8 # CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0x12,0xee,0x08,0x1e]
11
12 # CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0x26,0xee,0x0e,0x1e]
15
16 # CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0x02,0xee,0x02,0x0e]
19
20 # CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0x14,0xee,0x04,0x0e]
23
24 # CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0x2a,0xee,0x0e,0x2e]
27
28 # CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0x0e,0xee,0x01,0x1e]
31
32 # CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0x10,0xee,0x03,0x1e]
35
36 # CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0x20,0xee,0x09,0x3e]
39
40 # CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0x0c,0xee,0x05,0x0e]
43
44 # CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0x1a,0xee,0x09,0x2e]
47
48 # CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0x24,0xee,0x05,0x0e]
51
52 # CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0x08,0xfe,0x0e,0x3e]
55
56 # CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0x14,0xfe,0x0a,0x1e]
59
60 # CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x28,0xfe,0x0c,0x7e]
63
64 # CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x06,0xfe,0x0c,0x0e]
67
68 # CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0x18,0xfe,0x02,0x0e]
71
72 # CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0x2a,0xfe,0x00,0x4e]
75
76 # CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x06,0xfe,0x03,0x1e]
79
80 # CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x12,0xfe,0x09,0x1e]
83
84 # CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x2c,0xfe,0x07,0x3e]
87
88 # CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x06,0xfe,0x01,0x6e]
91
92 # CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x1e,0xfe,0x09,0x0e]
95
96 # CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x2c,0xfe,0x0f,0x0e]
99
100 # CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x34,0xee,0x0a,0xce]
103
104 # CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x30,0xee,0x0b,0x2e]
107
108 # CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x30,0xee,0x0a,0x3e]
111
112 # CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x30,0xee,0x0b,0x3e]
115
116 # CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0x3e,0xfe,0x0a,0x2e]
119
120 # CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0x38,0xfe,0x05,0x6e]
123
124 # CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0x32,0xfe,0x06,0xbe]
127
128 # CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0x3e,0xfe,0x09,0x1e]
131
132 # CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0x0d,0xee,0x00,0x4e]
135
136 # CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0x19,0xee,0x06,0x6e]
139
140 # CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0x2b,0xee,0x0c,0x6e]
143
144 # CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0x0d,0xee,0x04,0x1e]
147
148 # CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0x11,0xee,0x04,0x1e]
151
152 # CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0x29,0xee,0x08,0x5e]
155
156 # CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0x37,0xee,0x0e,0x4e]
159
160 # CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0x33,0xfe,0x06,0x0e]
163
164 # CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0x33,0xee,0x0e,0x3e]
167
168 # CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0x3f,0xfe,0x0e,0x1e]
171
172 # CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0x09,0xee,0x0b,0x0e]
175
176 # CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0x1f,0xee,0x09,0x0e]
179
180 # CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x2f,0xee,0x09,0x0e]
183
184 # CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0x0b,0xfe,0x05,0x6e]
187
188 # CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x1f,0xfe,0x09,0x4e]
191
192 # CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0x27,0xfe,0x05,0x2e]
195
196 # CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
197 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
198 [0x03,0xee,0x05,0x3e]
199
200 # CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
201 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
202 [0x13,0xee,0x05,0x3e]
203
204 # CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
205 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
206 [0x23,0xee,0x01,0x7e]
207
208 # CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
209 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
210 [0x0d,0xfe,0x01,0x3e]
211
212 # CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
213 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
214 [0x17,0xfe,0x0d,0x9e]
215
216 # CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
217 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
218 [0x25,0xfe,0x05,0x3e]
219
220 # CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
221 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
222 [0x33,0xee,0x03,0x0e]
223
224 # CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
225 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
226 [0x33,0xee,0x01,0x5e]
227
228 # CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
229 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
230 [0x37,0xee,0x0b,0x0e]
231
232 # CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
233 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
234 [0x37,0xee,0x03,0x1e]
235
236 # CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
237 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
238 [0x33,0xfe,0x09,0x0e]
239
240 # CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
241 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
242 [0x33,0xfe,0x0f,0x1e]
243
244 # CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
245 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
246 [0x37,0xfe,0x09,0x0e]
247
248 # CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
249 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
250 [0x37,0xfe,0x05,0x1e]
251
252 # CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
253 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
254 [0x3f,0xee,0x09,0x2e]
255
256 # CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
257 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
258 [0x3f,0xee,0x09,0x3e]
259
260 # CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
261 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
262 [0x3f,0xfe,0x07,0x0e]
263
264 # CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
265 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
266 [0x3f,0xfe,0x03,0x1e]
267
268 # CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
269 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
270 [0x3f,0xee,0x09,0x2e]
271
272 # CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
273 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
274 [0x3f,0xfe,0x03,0x1e]
275
276 # CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
277 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
278 [0xb2,0xee,0xc0,0x0b]
279
280 # CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
281 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
282 [0xf3,0xee,0xc2,0x0b]
283
284 # CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
285 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
286 [0x31,0xee,0x87,0x0e]
287
288 # CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
289 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
290 [0x31,0xee,0x83,0x9e]
291
292 # CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
293 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
294 [0x35,0xee,0x8f,0x2e]
295
296 # CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
297 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
298 [0x35,0xee,0x85,0x1e]
299
300 # CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
301 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
302 [0x31,0xfe,0x8b,0x2e]
303
304 # CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
305 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
306 [0x31,0xfe,0x81,0x1e]
307
308 # CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
309 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
310 [0x35,0xfe,0x81,0x2e]
311
312 # CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
313 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
314 [0x35,0xfe,0x87,0x7e]
315
316 # CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
317 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
318 [0x0e,0xee,0x0a,0x6f]
319
320 # CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
321 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
322 [0x10,0xee,0x0c,0x0f]
323
324 # CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
325 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
326 [0x10,0xee,0x0c,0x0f]
327
328 # CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
329 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
330 [0x12,0xee,0x00,0x7f]
331
332 # CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
333 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
334 [0x28,0xee,0x0a,0x6f]
335
336 # CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
337 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
338 [0x2e,0xee,0x04,0xdf]
339
340 # CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
341 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
342 [0x30,0xee,0x04,0x2f]
343
344 # CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
345 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
346 [0x32,0xee,0x02,0x1f]
347
348 # CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
349 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
350 [0x00,0xfe,0x04,0x2f]
351
352 # CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
353 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
354 [0x14,0xfe,0x06,0x0f]
355
356 # CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
357 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
358 [0x1a,0xfe,0x0a,0x1f]
359
360 # CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
361 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
362 [0x24,0xfe,0x0a,0x8f]
363
364 # CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
365 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
366 [0x2a,0xfe,0x00,0xbf]
367
368 # CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
369 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
370 [0x32,0xfe,0x02,0x6f]
371
372 # CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
373 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
374 [0x3c,0xfe,0x04,0x5f]
375
376 # CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
377 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
378 [0x38,0xee,0x0b,0x0f]
379
380 # CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
381 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
382 [0x3c,0xee,0x0b,0x1f]
383
384 # CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
385 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
386 [0x36,0xfe,0x0f,0x0f]
387
388 # CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
389 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
390 [0x3e,0xfe,0x0b,0x1f]