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Remove trailing whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 14 years ago
133 changed file(s) with 3190 addition(s) and 3190 deletion(s). Raw diff Collapse all Expand all
0 //===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the entry points for global functions defined in the LLVM
0 //===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 #define DEBUG_TYPE "isel"
7575 MachineFunction *F; // The function we are compiling into
7676 MachineBasicBlock *BB; // The current MBB we are compiling
7777 int VarArgsFrameIndex; // FrameIndex for start of varargs area
78
79 /// CollapsedGepOp - This struct is for recording the intermediate results
78
79 /// CollapsedGepOp - This struct is for recording the intermediate results
8080 /// used to calculate the base, index, and offset of a GEP instruction.
8181 struct CollapsedGepOp {
8282 ConstantSInt *offset; // the current offset into the struct/array
8686 offset(o), index(i), size(s) {}
8787 };
8888
89 /// FoldedGEP - This struct is for recording the necessary information to
89 /// FoldedGEP - This struct is for recording the necessary information to
9090 /// emit the GEP in a load or store instruction, used by emitGEPOperation.
9191 struct FoldedGEP {
9292 unsigned base;
9393 unsigned index;
9494 ConstantSInt *offset;
9595 FoldedGEP() : base(0), index(0), offset(0) {}
96 FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
96 FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
9797 base(b), index(i), offset(o) {}
9898 };
99
100 /// RlwimiRec - This struct is for recording the arguments to a PowerPC
99
100 /// RlwimiRec - This struct is for recording the arguments to a PowerPC
101101 /// rlwimi instruction to be output for a particular Instruction::Or when
102102 /// we recognize the pattern for rlwimi, starting with a shift or and.
103 struct RlwimiRec {
103 struct RlwimiRec {
104104 Value *Target, *Insert;
105105 unsigned Shift, MB, ME;
106106 RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
107107 RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
108108 Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
109109 };
110
110
111111 // External functions we may use in compiling the Module
112 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
112 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
113113 *__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
114114 *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
115115
125125
126126 // GEPMap - Mapping between basic blocks and GEP definitions
127127 std::map GEPMap;
128
128
129129 // RlwimiMap - Mapping between BinaryOperand (Or) instructions and info
130130 // needed to properly emit a rlwimi instruction in its place.
131131 std::map InsertMap;
139139 // flag to set whether or not we need to emit it for this function.
140140 unsigned GlobalBaseReg;
141141 bool GlobalBaseInitialized;
142
142
143143 PPC32ISel(TargetMachine &tm):TM(reinterpret_cast(tm)),
144144 F(0), BB(0) {}
145145
295295 MachineBasicBlock *MBB,
296296 MachineBasicBlock::iterator MBBI);
297297 void visitSelectInst(SelectInst &SI);
298
299
298
299
300300 // Memory Instructions
301301 void visitLoadInst(LoadInst &I);
302302 void visitStoreInst(StoreInst &I);
304304 void visitAllocaInst(AllocaInst &I);
305305 void visitMallocInst(MallocInst &I);
306306 void visitFreeInst(FreeInst &I);
307
307
308308 // Other operators
309309 void visitShiftInst(ShiftInst &I);
310310 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
341341 /// emitBitfieldInsert - return true if we were able to fold the sequence of
342342 /// instructions into a bitfield insert (rlwimi).
343343 bool emitBitfieldInsert(User *OpUser, unsigned DestReg);
344
344
345345 /// emitBitfieldExtract - return true if we were able to fold the sequence
346346 /// of instructions into a bitfield extract (rlwinm).
347 bool emitBitfieldExtract(MachineBasicBlock *MBB,
347 bool emitBitfieldExtract(MachineBasicBlock *MBB,
348348 MachineBasicBlock::iterator IP,
349349 User *OpUser, unsigned DestReg);
350350
352352 /// arithmetic and logical operations with constants on a register rather
353353 /// than a Value.
354354 ///
355 void emitBinaryConstOperation(MachineBasicBlock *MBB,
355 void emitBinaryConstOperation(MachineBasicBlock *MBB,
356356 MachineBasicBlock::iterator IP,
357 unsigned Op0Reg, ConstantInt *Op1,
357 unsigned Op0Reg, ConstantInt *Op1,
358358 unsigned Opcode, unsigned DestReg);
359359
360 /// emitSimpleBinaryOperation - Implement simple binary operators for
361 /// integral types. OperatorClass is one of: 0 for Add, 1 for Sub,
360 /// emitSimpleBinaryOperation - Implement simple binary operators for
361 /// integral types. OperatorClass is one of: 0 for Add, 1 for Sub,
362362 /// 2 for And, 3 for Or, 4 for Xor.
363363 ///
364364 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
379379 void doMultiply(MachineBasicBlock *MBB,
380380 MachineBasicBlock::iterator IP,
381381 unsigned DestReg, Value *Op0, Value *Op1);
382
382
383383 /// doMultiplyConst - This method will multiply the value in Op0Reg by the
384384 /// value of the ContantInt *CI
385 void doMultiplyConst(MachineBasicBlock *MBB,
385 void doMultiplyConst(MachineBasicBlock *MBB,
386386 MachineBasicBlock::iterator IP,
387387 unsigned DestReg, Value *Op0, ConstantInt *CI);
388388
405405 void emitShiftOperation(MachineBasicBlock *MBB,
406406 MachineBasicBlock::iterator IP,
407407 Value *Op, Value *ShiftAmount, bool isLeftShift,
408 const Type *ResultTy, ShiftInst *SI,
408 const Type *ResultTy, ShiftInst *SI,
409409 unsigned DestReg);
410
410
411411 /// emitSelectOperation - Common code shared between visitSelectInst and the
412412 /// constant expression support.
413413 ///
467467 }
468468 unsigned getReg(Value *V, MachineBasicBlock *MBB,
469469 MachineBasicBlock::iterator IPt);
470
470
471471 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
472472 /// is okay to use as an immediate argument to a certain binary operation
473473 bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
541541
542542 // Treat subfic like addi for the purposes of constant validation
543543 if (Opcode == 5) Opcode = 0;
544
544
545545 // addi, subfic, compare, and non-indexed load take SIMM
546546 bool cond1 = (Opcode < 2)
547547 && ((int32_t)CI->getRawValue() <= 32767)
577577 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
578578 TySize *= CUI->getValue(); // Get total allocated size...
579579 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
580
580
581581 // Create a new stack object using the frame manager...
582582 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
583583 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
640640 abort();
641641 }
642642 }
643
643
644644 assert(Class <= cInt && "Type not handled yet!");
645645
646646 // Handle bool
648648 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
649649 return;
650650 }
651
651
652652 // Handle int
653653 if (ConstantUInt *CUI = dyn_cast(C)) {
654654 unsigned uval = CUI->getValue();
694694 } else if (GlobalValue *GV = dyn_cast(C)) {
695695 // GV is located at base + distance
696696 unsigned TmpReg = makeAnotherReg(GV->getType());
697
697
698698 // Move value at base + distance into return reg
699699 BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
700700 .addReg(getGlobalBaseReg()).addGlobalAddress(GV);
717717 unsigned GPR_remaining = 8;
718718 unsigned FPR_remaining = 13;
719719 unsigned GPR_idx = 0, FPR_idx = 0;
720 static const unsigned GPR[] = {
720 static const unsigned GPR[] = {
721721 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
722722 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
723723 };
725725 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
726726 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
727727 };
728
728
729729 MachineFrameInfo *MFI = F->getFrameInfo();
730
730
731731 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
732732 I != E; ++I) {
733733 bool ArgLive = !I->use_empty();
822822 }
823823
824824 // doubles require 4 additional bytes and use 2 GPRs of param space
825 ArgOffset += 4;
825 ArgOffset += 4;
826826 if (GPR_remaining > 0) {
827827 GPR_remaining--;
828828 GPR_idx++;
10031003 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
10041004 if (GetElementPtrInst *GEPI = dyn_cast(V)) {
10051005 bool AllUsesAreMem = true;
1006 for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
1006 for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
10071007 I != E; ++I) {
10081008 Instruction *User = cast(*I);
10091009
11101110 const Type *CompTy = Op0->getType();
11111111 unsigned Class = getClassB(CompTy);
11121112 unsigned Op0r = ExtendOrClear(MBB, IP, Op0);
1113
1113
11141114 // Use crand for lt, gt and crandc for le, ge
11151115 unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
11161116 // ? cr1[lt] : cr1[gt]
11251125 if (Class == cByte || Class == cShort || Class == cInt) {
11261126 unsigned Op1v = CI->getRawValue() & 0xFFFF;
11271127 unsigned OpClass = (CompTy->isSigned()) ? 0 : 2;
1128
1128
11291129 // Treat compare like ADDI for the purposes of immediate suitability
11301130 if (canUseAsImmediateForOpcode(CI, OpClass, false)) {
11311131 BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
12261226 const Type *Ty = Op0->getType();
12271227 unsigned Class = getClassB(Ty);
12281228 unsigned Opcode = I.getOpcode();
1229 unsigned OpNum = getSetCCNumber(Opcode);
1229 unsigned OpNum = getSetCCNumber(Opcode);
12301230 unsigned DestReg = getReg(I);
12311231
12321232 // If the comparison type is byte, short, or int, then we can emit a
12371237
12381238 if (CI && CI->getRawValue() == 0) {
12391239 unsigned Op0Reg = ExtendOrClear(BB, MI, Op0);
1240
1240
12411241 // comparisons against constant zero and negative one often have shorter
12421242 // and/or faster sequences than the set-and-branch general case, handled
12431243 // below.
12481248 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(TempReg).addImm(27)
12491249 .addImm(5).addImm(31);
12501250 break;
1251 }
1251 }
12521252 case 1: { // ne0
12531253 unsigned TempReg = makeAnotherReg(Type::IntTy);
12541254 BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
12551255 BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
12561256 break;
1257 }
1257 }
12581258 case 2: { // lt0, always false if unsigned
12591259 if (Ty->isSigned())
12601260 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(1)
12641264 break;
12651265 }
12661266 case 3: { // ge0, always true if unsigned
1267 if (Ty->isSigned()) {
1267 if (Ty->isSigned()) {
12681268 unsigned TempReg = makeAnotherReg(Type::IntTy);
12691269 BuildMI(*BB, MI, PPC::RLWINM, 4, TempReg).addReg(Op0Reg).addImm(1)
12701270 .addImm(31).addImm(31);
12771277 case 4: { // gt0, equivalent to ne0 if unsigned
12781278 unsigned Temp1 = makeAnotherReg(Type::IntTy);
12791279 unsigned Temp2 = makeAnotherReg(Type::IntTy);
1280 if (Ty->isSigned()) {
1280 if (Ty->isSigned()) {
12811281 BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
12821282 BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
12831283 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
12911291 case 5: { // le0, equivalent to eq0 if unsigned
12921292 unsigned Temp1 = makeAnotherReg(Type::IntTy);
12931293 unsigned Temp2 = makeAnotherReg(Type::IntTy);
1294 if (Ty->isSigned()) {
1294 if (Ty->isSigned()) {
12951295 BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
12961296 BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
12971297 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
13151315 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13161316 ilist::iterator It = BB;
13171317 ++It;
1318
1318
13191319 // thisMBB:
13201320 // ...
13211321 // cmpTY cr0, r1, r2
13561356 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
13571357 SI.getFalseValue(), DestReg);
13581358 }
1359
1359
13601360 /// emitSelect - Common code shared between visitSelectInst and the constant
13611361 /// expression support.
13621362 void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
13631363 MachineBasicBlock::iterator IP,
1364 Value *Cond, Value *TrueVal,
1364 Value *Cond, Value *TrueVal,
13651365 Value *FalseVal, unsigned DestReg) {
13661366 unsigned SelectClass = getClassB(TrueVal->getType());
13671367 unsigned Opcode;
14901490 BB = sinkMBB;
14911491 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
14921492 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1493
1493
14941494 // For a register pair representing a long value, define the top part.
14951495 if (getClassB(TrueVal->getType()) == cLong)
14961496 BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(FalseValue+1)
16011601 BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
16021602 if (BI.isConditional())
16031603 BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
1604
1604
16051605 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
16061606
16071607 if (!BI.isConditional()) { // Unconditional branch?
1608 if (BI.getSuccessor(0) != NextBB)
1608 if (BI.getSuccessor(0) != NextBB)
16091609 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
16101610 return;
16111611 }
1612
1612
16131613 // See if we can fold the setcc into the branch itself...
16141614 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
16151615 if (SCI == 0) {
16371637 unsigned Opcode = getPPCOpcodeForSetCCOpcode(SCI->getOpcode());
16381638 MachineBasicBlock::iterator MII = BB->end();
16391639 EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1640
1640
16411641 if (BI.getSuccessor(0) != NextBB) {
16421642 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
16431643 .addMBB(MBBMap[BI.getSuccessor(0)])
16831683 default: assert(0 && "Unknown class!");
16841684 }
16851685
1686 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
1686 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
16871687 // plus 32 bytes of argument space in case any called code gets funky on us.
16881688 if (NumBytes < 56) NumBytes = 56;
16891689
16951695 // Offset to the paramater area on the stack is 24.
16961696 int GPR_remaining = 8, FPR_remaining = 13;
16971697 unsigned GPR_idx = 0, FPR_idx = 0;
1698 static const unsigned GPR[] = {
1698 static const unsigned GPR[] = {
16991699 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
17001700 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
17011701 };
17021702 static const unsigned FPR[] = {
1703 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1704 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
1703 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1704 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
17051705 PPC::F13
17061706 };
1707
1707
17081708 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
17091709 unsigned ArgReg;
17101710 switch (getClassB(Args[i].Ty)) {
17131713 // Promote arg to 32 bits wide into a temporary register...
17141714 ArgReg = makeAnotherReg(Type::UIntTy);
17151715 promote32(ArgReg, Args[i]);
1716
1716
17171717 // Reg or stack?
17181718 if (GPR_remaining > 0) {
17191719 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
17711771 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
17721772 FPR_remaining--;
17731773 FPR_idx++;
1774
1774
17751775 // If this is a vararg function, and there are GPRs left, also
17761776 // pass the float in an int. Otherwise, put it on the stack.
17771777 if (isVarArg) {
18001800 if (isVarArg) {
18011801 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
18021802 .addReg(PPC::R1);
1803
1803
18041804 // Doubles can be split across reg + stack for varargs
18051805 if (GPR_remaining > 0) {
18061806 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
18221822 GPR_remaining--;
18231823 GPR_idx++;
18241824 break;
1825
1825
18261826 default: assert(0 && "Unknown class!");
18271827 }
18281828 ArgOffset += 4;
18321832 } else {
18331833 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
18341834 }
1835
1835
18361836 BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
18371837 BB->push_back(CallMI);
1838
1838
18391839 // These functions are automatically eliminated by the prolog/epilog pass
18401840 BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
18411841
18921892 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
18931893 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
18941894 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1895 }
1895 }
18961896
18971897
18981898 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
19791979 case Intrinsic::vastart:
19801980 // Get the address of the first vararg value...
19811981 TmpReg1 = getReg(CI);
1982 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
1982 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
19831983 0, false);
19841984 return;
19851985
19951995 if (cast(CI.getOperand(1))->isNullValue()) {
19961996 MachineFrameInfo *MFI = F->getFrameInfo();
19971997 unsigned NumBytes = MFI->getStackSize();
1998
1998
19991999 BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
20002000 .addReg(PPC::R1);
20012001 } else {
20132013 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
20142014 }
20152015 return;
2016
2016
20172017 #if 0
20182018 // This may be useful for supporting isunordered
20192019 case Intrinsic::isnan:
20272027 BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
20282028 return;
20292029 #endif
2030
2030
20312031 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
20322032 }
20332033 }
20502050 .addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
20512051 return;
20522052 }
2053
2053
20542054 unsigned Class = getClassB(B.getType());
20552055 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
20562056 emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
21012101 // not, since all 1's are not contiguous.
21022102 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
21032103 bool isRun = true;
2104 MB = 0;
2104 MB = 0;
21052105 ME = 0;
21062106
21072107 // look for first set bit
21132113 break;
21142114 }
21152115 }
2116
2116
21172117 // look for last set bit
21182118 for (; i < 32; i++) {
21192119 if ((Val & (1 << (31 - i))) == 0)
21262126 if ((Val & (1 << (31 - i))) != 0)
21272127 break;
21282128 }
2129
2129
21302130 // if we exhausted all the bits, we found a match at this point for 0*1*0*
21312131 if (i == 32)
21322132 return true;
21422142 if ((Val & (1 << (31 - i))) == 0)
21432143 break;
21442144 }
2145
2145
21462146 // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
21472147 // the value is not a run of ones.
21482148 if (i == 32)
21552155 /// second operand is a constant int. Optionally, set OrI to the Or instruction
21562156 /// that is the sole user of OpUser, and Op1User to the other operand of the Or
21572157 /// instruction.
2158 static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
2158 static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
21592159 Instruction **OrI, unsigned &Mask) {
21602160 // If this instruction doesn't have one use, then return false.
21612161 if (!OpUser->hasOneUse())
21622162 return false;
2163
2163
21642164 Mask = 0xFFFFFFFF;
21652165 if (BinaryOperator *BO = dyn_cast(OpUser))
21662166 if (BO->getOpcode() == Instruction::And) {
21892189 /// instruction that is either used directly by the or instruction, or is used
21902190 /// by an and instruction whose second operand is a constant int, and which is
21912191 /// used by the or instruction.
2192 static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
2193 Instruction **OrI, Instruction **OptAndI,
2192 static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
2193 Instruction **OrI, Instruction **OptAndI,
21942194 unsigned &Shift, unsigned &Mask) {
21952195 // If this instruction doesn't have one use, then return false.
21962196 if (!OpUser->hasOneUse())
21972197 return false;
2198
2198
21992199 Mask = 0xFFFFFFFF;
22002200 if (ShiftInst *SI = dyn_cast(OpUser)) {
22012201 if (ConstantInt *CI = dyn_cast(SI->getOperand(1))) {
22352235 return false;
22362236 }
22372237
2238 /// emitBitfieldInsert - turn a shift used only by an and with immediate into
2238 /// emitBitfieldInsert - turn a shift used only by an and with immediate into
22392239 /// the rotate left word immediate then mask insert (rlwimi) instruction.
22402240 /// Patterns matched:
22412241 /// 1. or shl, and 5. or (shl-and), and 9. or and, and
22602260 matched = true;
22612261 else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
22622262 matched = true;
2263
2263
22642264 // Look for cases 1, 3, 5, and 7. Force the shift argument to be the one
22652265 // inserted into the target, since rlwimi can only rotate the value inserted,
22662266 // not the value being inserted into.
22702270 std::swap(Op0User, Op1User);
22712271 matched = true;
22722272 }
2273
2273
22742274 // We didn't succeed in matching one of the patterns, so return false
22752275 if (matched == false)
22762276 return false;
2277
2277
22782278 // If the masks xor to -1, and the insert mask is a run of ones, then we have
22792279 // succeeded in matching one of the cases for generating rlwimi. Update the
22802280 // skip lists and users of the Instruction::Or.
22832283 SkipList.push_back(Op0User);
22842284 SkipList.push_back(Op1User);
22852285 SkipList.push_back(OptAndI);
2286 InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
2286 InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
22872287 Amount, MB, ME);
22882288 return true;
22892289 }
22922292
22932293 /// emitBitfieldExtract - turn a shift used only by an and with immediate into the
22942294 /// rotate left word immediate then and with mask (rlwinm) instruction.
2295 bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
2295 bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
22962296 MachineBasicBlock::iterator IP,
22972297 User *OpUser, unsigned DestReg) {
22982298 return false;
23102310 if (isExtractShiftHalf)
23112311 if (isExtractAndHalf)
23122312 matched = true;
2313
2313
23142314 if (matched == false && isExtractAndHalf)
23152315 if (isExtractShiftHalf)
23162316 matched = true;
2317
2317
23182318 if (matched == false)
23192319 return false;
23202320
23302330 }
23312331
23322332 /// emitBinaryConstOperation - Implement simple binary operators for integral
2333 /// types with a constant operand. Opcode is one of: 0 for Add, 1 for Sub,
2333 /// types with a constant operand. Opcode is one of: 0 for Add, 1 for Sub,
23342334 /// 2 for And, 3 for Or, 4 for Xor, and 5 for Subtract-From.
23352335 ///
2336 void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
2336 void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
23372337 MachineBasicBlock::iterator IP,
2338 unsigned Op0Reg, ConstantInt *Op1,
2338 unsigned Op0Reg, ConstantInt *Op1,
23392339 unsigned Opcode, unsigned DestReg) {
23402340 static const unsigned OpTab[] = {
23412341 PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR, PPC::SUBF
23502350 Op1 = cast(ConstantExpr::getNeg(Op1));
23512351 Opcode = 0;
23522352 }
2353
2353
23542354 // xor X, -1 -> not X
23552355 if (Opcode == 4 && Op1->isAllOnesValue()) {
23562356 BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
23572357 return;
23582358 }
2359
2359
23602360 if (Opcode == 2 && !Op1->isNullValue()) {
23612361 unsigned MB, ME, mask = Op1->getRawValue();
23622362 if (isRunOfOnes(mask, MB, ME)) {
23742374 bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
23752375
23762376 // For Add, Sub, and SubF the instruction takes a signed immediate. For And,
2377 // Or, and Xor, the instruction takes an unsigned immediate. There is no
2377 // Or, and Xor, the instruction takes an unsigned immediate. There is no
23782378 // shifted immediate form of SubF so disallow its opcode for those constants.
23792379 if (canUseAsImmediateForOpcode(Op1, Opcode, false)) {
23802380 if (Opcode < 2 || Opcode == 5)
24152415 ///
24162416 void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
24172417 MachineBasicBlock::iterator IP,
2418 BinaryOperator *BO,
2418 BinaryOperator *BO,
24192419 Value *Op0, Value *Op1,
2420 unsigned OperatorClass,
2420 unsigned OperatorClass,
24212421 unsigned DestReg) {
24222422 // Arithmetic and Bitwise operators
24232423 static const unsigned OpcodeTab[] = {
24272427 { PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
24282428 { PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
24292429 };
2430
2430
24312431 unsigned Class = getClassB(Op0->getType());
24322432
24332433 if (Class == cFP32 || Class == cFP64) {
24652465 if (Class != cLong) {
24662466 if (emitBitfieldInsert(BO, DestReg))
24672467 return;
2468
2468
24692469 unsigned Op0r = getReg(Op0, MBB, IP);
24702470 emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
24712471 return;
25072507 unsigned DestReg, Value *Op0, Value *Op1) {
25082508 unsigned Class0 = getClass(Op0->getType());
25092509 unsigned Class1 = getClass(Op1->getType());
2510
2510
25112511 unsigned Op0r = getReg(Op0, MBB, IP);
25122512 unsigned Op1r = getReg(Op1, MBB, IP);
2513
2513
25142514 // 64 x 64 -> 64
25152515 if (Class0 == cLong && Class1 == cLong) {
25162516 unsigned Tmp1 = makeAnotherReg(Type::IntTy);
25252525 BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
25262526 return;
25272527 }
2528
2528
25292529 // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
25302530 if (Class0 == cLong && Class1 <= cInt) {
25312531 unsigned Tmp0 = makeAnotherReg(Type::IntTy);
25452545 BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
25462546 return;
25472547 }
2548
2548
25492549 // 32 x 32 -> 32
25502550 if (Class0 <= cInt && Class1 <= cInt) {
25512551 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
25522552 return;
25532553 }
2554
2554
25552555 assert(0 && "doMultiply cannot operate on unknown type!");
25562556 }
25572557
25692569 BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
25702570 return;
25712571 }
2572
2572
25732573 // Mul op0, 1 ==> op0
25742574 if (CI->equalsInt(1)) {
25752575 unsigned Op0r = getReg(Op0, MBB, IP);
25852585 emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), 0, DestReg);
25862586 return;
25872587 }
2588
2588
25892589 // If 32 bits or less and immediate is in right range, emit mul by immediate
25902590 if (Class == cByte || Class == cShort || Class == cInt) {
25912591 if (canUseAsImmediateForOpcode(CI, 0, false)) {
25952595 return;
25962596 }
25972597 }
2598
2598
25992599 doMultiply(MBB, IP, DestReg, Op0, CI);
26002600 }
26012601
26772677 // Floating point divide...
26782678 emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
26792679 return;
2680 } else {
2680 } else {
26812681 // Floating point remainder via fmod(double x, double y);
26822682 unsigned Op0Reg = getReg(Op0, MBB, IP);
26832683 unsigned Op1Reg = getReg(Op1, MBB, IP);
27312731 if (log2V != 0 && Ty->isSigned()) {
27322732 unsigned Op0Reg = getReg(Op0, MBB, IP);
27332733 unsigned TmpReg = makeAnotherReg(Op0->getType());
2734
2734
27352735 BuildMI(*MBB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
27362736 BuildMI(*MBB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
27372737 return;
27822782 ///
27832783 void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
27842784 MachineBasicBlock::iterator IP,
2785 Value *Op, Value *ShiftAmount,
2785 Value *Op, Value *ShiftAmount,
27862786 bool isLeftShift, const Type *ResultTy,
27872787 ShiftInst *SI, unsigned DestReg) {
27882788 bool isSigned = ResultTy->isSigned ();
27892789 unsigned Class = getClass (ResultTy);
2790
2790
27912791 // Longs, as usual, are handled specially...
27922792 if (Class == cLong) {
27932793 unsigned SrcReg = getReg (Op, MBB, IP);
28602860 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
28612861 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
28622862 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2863
2863
28642864 if (isLeftShift) {
28652865 BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
28662866 .addSImm(32);
28782878 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
28792879 .addReg(ShiftAmountReg);
28802880 } else {
2881 if (isSigned) { // shift right algebraic
2881 if (isSigned) { // shift right algebraic
28822882 MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
28832883 MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
28842884 MachineBasicBlock *OldMBB = BB;
29032903 BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
29042904 .addReg(ShiftAmountReg);
29052905 BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2906
2906
29072907 // OrMBB:
29082908 // Select correct least significant half if the shift amount > 32
29092909 BB = TmpMBB;
29102910 unsigned OrReg = makeAnotherReg(Type::IntTy);
29112911 BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addReg(TmpReg6);
29122912 TmpMBB->addSuccessor(PhiMBB);
2913
2913
29142914 BB = PhiMBB;
29152915 BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
29162916 .addReg(OrReg).addMBB(TmpMBB);
29412941 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
29422942 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
29432943 unsigned Amount = CUI->getValue();
2944
2944
29452945 // If this is a shift with one use, and that use is an And instruction,
29462946 // then attempt to emit a bitfield operation.
29472947 if (SI && emitBitfieldInsert(SI, DestReg))
29482948 return;
2949
2949
29502950 unsigned SrcReg = getReg (Op, MBB, IP);
29512951 if (Amount == 0) {
29522952 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
30073007 ///
30083008 void PPC32ISel::visitLoadInst(LoadInst &I) {
30093009 // Immediate opcodes, for reg+imm addressing
3010 static const unsigned ImmOpcodes[] = {
3011 PPC::LBZ, PPC::LHZ, PPC::LWZ,
3010 static const unsigned ImmOpcodes[] = {
3011 PPC::LBZ, PPC::LHZ, PPC::LWZ,
30123012 PPC::LFS, PPC::LFD, PPC::LWZ
30133013 };
30143014 // Indexed opcodes, for reg+reg addressing
30223022 unsigned IdxOpcode = IdxOpcodes[Class];
30233023 unsigned DestReg = getReg(I);
30243024 Value *SourceAddr = I.getOperand(0);
3025
3025
30263026 if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
30273027 if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
30283028
30423042 }
30433043 return;
30443044 }
3045
3045
30463046 // If the offset fits in 16 bits, we can emit a reg+imm load, otherwise, we
30473047 // use the index from the FoldedGEP struct and use reg+reg addressing.
30483048 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
30723072 }
30733073 return;
30743074 }
3075
3075
30763076 // The fallback case, where the load was from a source that could not be
3077 // folded into the load instruction.
3077 // folded into the load instruction.
30783078 unsigned SrcAddrReg = getReg(SourceAddr);
3079
3079
30803080 if (Class == cLong) {
30813081 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
30823082 BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
30943094 void PPC32ISel::visitStoreInst(StoreInst &I) {
30953095 // Immediate opcodes, for reg+imm addressing
30963096 static const unsigned ImmOpcodes[] = {
3097 PPC::STB, PPC::STH, PPC::STW,
3097 PPC::STB, PPC::STH, PPC::STW,
30983098 PPC::STFS, PPC::STFD, PPC::STW
30993099 };
31003100 // Indexed opcodes, for reg+reg addressing
31013101 static const unsigned IdxOpcodes[] = {
3102 PPC::STBX, PPC::STHX, PPC::STWX,
3102 PPC::STBX, PPC::STHX, PPC::STWX,
31033103 PPC::STFSX, PPC::STFDX, PPC::STWX
31043104 };
3105
3105
31063106 Value *SourceAddr = I.getOperand(1);
31073107 const Type *ValTy = I.getOperand(0)->getType();
31083108 unsigned Class = getClassB(ValTy);
31193119 addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
31203120 return;
31213121 }
3122
3122
31233123 // If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
31243124 // use the index from the FoldedGEP struct and use reg+reg addressing.
31253125 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
31283128 unsigned baseReg = GEPMap[GEPI].base;
31293129 unsigned indexReg = GEPMap[GEPI].index;
31303130 ConstantSInt *offset = GEPMap[GEPI].offset;
3131
3131
31323132 if (Class != cLong) {
31333133 if (indexReg == 0)
31343134 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
31463146 }
31473147 return;
31483148 }
3149
3149
31503150 // If the store address wasn't the only use of a GEP, we fall back to the
31513151 // standard path: store the ValReg at the value in AddressReg.
31523152 unsigned AddressReg = getReg(I.getOperand(1));
31813181 if (!isa(*I)) {
31823182 AllUsesAreGEPs = false;
31833183 break;
3184 }
3184 }
31853185 if (AllUsesAreGEPs) return;
31863186 }
3187
3187
31883188 unsigned DestReg = getReg(CI);
31893189 MachineBasicBlock::iterator MI = BB->end();
31903190
31973197 if (SI && (SI->getOperand(1) == &CI)) {
31983198 unsigned SrcReg = getReg(Op, BB, MI);
31993199 BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3200 return;
3200 return;
32013201 }
32023202 }
32033203
32113211 if (!isa(*I)) {
32123212 AllUsesAreStores = false;
32133213 break;
3214 }
3214 }
32153215 // Turn this cast directly into a move instruction, which the register
32163216 // allocator will deal with.
3217 if (AllUsesAreStores) {
3217 if (AllUsesAreStores) {
32183218 unsigned SrcReg = getReg(Op, BB, MI);
32193219 BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3220 return;
3220 return;
32213221 }
32223222 }
32233223 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
32903290 BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
32913291 return;
32923292 }
3293
3293
32943294 // Handle cast of Double -> Float
32953295 if (SrcClass == cFP64 && DestClass == cFP32) {
32963296 BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
32973297 return;
32983298 }
3299
3299
33003300 // Handle casts from integer to floating point now...
33013301 if (DestClass == cFP32 || DestClass == cFP64) {
33023302
33423342 doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
33433343 BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
33443344 BB->addSuccessor(PhiMBB);
3345
3345
33463346 // SetMBB
33473347 BB = SetMBB;
33483348 unsigned SetReg = makeAnotherReg(DestTy);
33493349 unsigned CallReg = makeAnotherReg(DestTy);
33503350 unsigned ShiftedReg = makeAnotherReg(SrcTy);
33513351 ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
3352 emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
3352 emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
33533353 ShiftedReg);
33543354 SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
33553355 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
33573357 unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
33583358 BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
33593359 BB->addSuccessor(PhiMBB);
3360
3360
33613361 // PhiMBB
33623362 BB = PhiMBB;
33633363 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
33653365 }
33663366 return;
33673367 }
3368
3368
33693369 // Make sure we're dealing with a full 32 bits
33703370 if (SrcClass < cInt) {
33713371 unsigned TmpReg = makeAnotherReg(Type::IntTy);
33723372 promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
33733373 SrcReg = TmpReg;
33743374 }
3375
3375
33763376 // Spill the integer to memory and reload it from there.
33773377 // Also spill room for a special conversion constant
33783378 int ValueFrameIdx =
33803380
33813381 unsigned constantHi = makeAnotherReg(Type::IntTy);
33823382 unsigned TempF = makeAnotherReg(Type::DoubleTy);
3383
3383
33843384 if (!SrcTy->isSigned()) {
33853385 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
33863386 unsigned ConstF = getReg(CFP, BB, IP);
33873387 BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
3388 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
3388 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
33893389 ValueFrameIdx);
3390 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
3390 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
33913391 ValueFrameIdx, 4);
33923392 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
33933393 BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
33963396 unsigned ConstF = getReg(CFP, BB, IP);
33973397 unsigned TempLo = makeAnotherReg(Type::IntTy);
33983398 BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
3399 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
3399 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
34003400 ValueFrameIdx);
34013401 BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
3402 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
3402 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
34033403 ValueFrameIdx, 4);
34043404 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
34053405 BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
34293429
34303430 if (DestTy->isSigned()) {
34313431 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
3432
3432
34333433 // Convert to integer in the FP reg and store it to a stack slot
34343434 BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
34353435 addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
34363436 .addReg(TempReg), ValueFrameIdx);
34373437
34383438 // There is no load signed byte opcode, so we must emit a sign extend for
3439 // that particular size. Make sure to source the new integer from the
3439 // that particular size. Make sure to source the new integer from the
34403440 // correct offset.
34413441 if (DestClass == cByte) {
34423442 unsigned TempReg2 = makeAnotherReg(DestTy);
3443 addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
3443 addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
34443444 ValueFrameIdx, 7);
34453445 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
34463446 } else {
34473447 int offset = (DestClass == cShort) ? 6 : 4;
34483448 unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
3449 addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
3449 addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
34503450 ValueFrameIdx, offset);
34513451 }
34523452 } else {
34633463 unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
34643464 unsigned IntTmp = makeAnotherReg(Type::IntTy);
34653465 unsigned XorReg = makeAnotherReg(Type::IntTy);
3466 int FrameIdx =
3466 int FrameIdx =
34673467 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
34683468 // Update machine-CFG edges
34693469 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
35233523 }
35243524
35253525 // Check our invariants
3526 assert((SrcClass <= cInt || SrcClass == cLong) &&
3526 assert((SrcClass <= cInt || SrcClass == cLong) &&
35273527 "Unhandled source class for cast operation!");
3528 assert((DestClass <= cInt || DestClass == cLong) &&
3528 assert((DestClass <= cInt || DestClass == cLong) &&
35293529 "Unhandled destination class for cast operation!");
35303530
35313531 bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
35323532 bool destUnsigned = DestTy->isUnsigned();
35333533
3534 // Unsigned -> Unsigned, clear if larger,
3534 // Unsigned -> Unsigned, clear if larger,
35353535 if (sourceUnsigned && destUnsigned) {
35363536 // handle long dest class now to keep switch clean
35373537 if (DestClass == cLong) {
37533753 // multiple definitions of the base register.
37543754 if (GEPIsFolded && (GEPMap[GEPI].base != 0))
37553755 return;
3756
3756
37573757 Value *Src = GEPI->getOperand(0);
37583758 User::op_iterator IdxBegin = GEPI->op_begin()+1;
37593759 User::op_iterator IdxEnd = GEPI->op_end();
37603760 const TargetData &TD = TM.getTargetData();
37613761 const Type *Ty = Src->getType();
37623762 int32_t constValue = 0;
3763
3763
37643764 // Record the operations to emit the GEP in a vector so that we can emit them
37653765 // after having analyzed the entire instruction.
37663766 std::vector ops;
3767
3767
37683768 // GEPs have zero or more indices; we must perform a struct access
37693769 // or array access for each one.
37703770 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
37993799 // type is the type of the elements in the array).
38003800 Ty = SqTy->getElementType();
38013801 unsigned elementSize = TD.getTypeSize(Ty);
3802
3802
38033803 if (ConstantInt *C = dyn_cast(idx)) {
38043804 if (ConstantSInt *CS = dyn_cast(C))
38053805 constValue += CS->getValue() * elementSize;
38323832 TmpReg1 = makeAnotherReg(Type::IntTy);
38333833 doMultiplyConst(MBB, IP, TmpReg1, cgo.index, cgo.size);
38343834 }
3835
3835
38363836 unsigned TmpReg2;
3837 if (cgo.offset->isNullValue()) {
3837 if (cgo.offset->isNullValue()) {
38383838 TmpReg2 = TmpReg1;
38393839 } else {
38403840 TmpReg2 = makeAnotherReg(Type::IntTy);
38413841 emitBinaryConstOperation(MBB, IP, TmpReg1, cgo.offset, 0, TmpReg2);
38423842 }
3843
3843
38443844 if (indexReg == 0)
38453845 indexReg = TmpReg2;
38463846 else {
38493849 indexReg = TmpReg3;
38503850 }
38513851 }
3852
3852
38533853 // We now have a base register, an index register, and possibly a constant
38543854 // remainder. If the GEP is going to be folded, we try to generate the
38553855 // optimal addressing mode.
38563856 ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
3857
3857
38583858 // If we are emitting this during a fold, copy the current base register to
38593859 // the target, and save the current constant offset so the folding load or
38603860 // store can try and use it as an immediate.
39033903 // statically stack allocate the space, so we don't need to do anything here.
39043904 //
39053905 if (dyn_castFixedAlloca(&I)) return;
3906
3906
39073907 // Find the data size of the alloca inst's getAllocatedType.
39083908 const Type *Ty = I.getAllocatedType();
39093909 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
39113911 // Create a register to hold the temporary result of multiplying the type size
39123912 // constant by the variable amount.
39133913 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3914
3914
39153915 // TotalSizeReg = mul ,
39163916 MachineBasicBlock::iterator MBBI = BB->end();
39173917 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
39253925 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
39263926 BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
39273927 .addImm(0).addImm(27);
3928
3928
39293929 // Subtract size from stack pointer, thereby allocating some space.
39303930 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(AlignedSize).addReg(PPC::R1);
39313931
39563956
39573957 std::vector Args;
39583958 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3959 MachineInstr *TheCall =
3959 MachineInstr *TheCall =
39603960 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
39613961 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
39623962 }
39673967 void PPC32ISel::visitFreeInst(FreeInst &I) {
39683968 std::vector Args;
39693969 Args.push_back(ValueRecord(I.getOperand(0)));
3970 MachineInstr *TheCall =
3970 MachineInstr *TheCall =
39713971 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
39723972 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
39733973 }
3974
3974
39753975 /// createPPC32ISelSimple - This pass converts an LLVM function into a machine
39763976 /// code representation is a very simple peep-hole fashion.
39773977 ///
0 //===- PPC32JITInfo.h - PowerPC/Darwin JIT interface --------*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC implementation of the TargetJITInfo class.
0 //===-- PPC64CodeEmitter.cpp - JIT Code Emitter for PPC64 -----*- C++ -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
8 //
8 //
99 //
1010 //===----------------------------------------------------------------------===//
1111
33 //
44 // This file was developed by Nate Begeman and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines a pattern matching instruction selector for 64 bit PowerPC.
4444 addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
4545 addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);
4646 addRegisterClass(MVT::f64, PPC64::FPRCRegisterClass);
47
47
4848 // PowerPC has no intrinsics for these particular operations
4949 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
5050 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
6161
6262 setShiftAmountFlavor(Extend); // shl X, 32 == 0
6363 addLegalFPImmediate(+0.0); // Necessary for FSEL
64 addLegalFPImmediate(-0.0); //
64 addLegalFPImmediate(-0.0); //
6565
6666 computeRegisterProperties();
6767 }
7070 /// lower the arguments for the specified function, into the specified DAG.
7171 virtual std::vector
7272 LowerArguments(Function &F, SelectionDAG &DAG);
73
73
7474 /// LowerCallTo - This hook lowers an abstract call to a function into an
7575 /// actual call.
7676 virtual std::pair
7777 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
7878 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
79
79
8080 virtual std::pair
8181 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
82
82
8383 virtual std::pair
8484 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
8585 const Type *ArgTy, SelectionDAG &DAG);
100100 MachineFrameInfo *MFI = MF.getFrameInfo();
101101 MachineBasicBlock& BB = MF.front();
102102 std::vector ArgValues;
103
104 // Due to the rather complicated nature of the PowerPC ABI, rather than a
103
104 // Due to the rather complicated nature of the PowerPC ABI, rather than a
105105 // fixed size array of physical args, for the sake of simplicity let the STL
106106 // handle tracking them for us.
107107 std::vector argVR, argPR, argOp;
109109 unsigned GPR_remaining = 8;
110110 unsigned FPR_remaining = 13;
111111 unsigned GPR_idx = 0, FPR_idx = 0;
112 static const unsigned GPR[] = {
112 static const unsigned GPR[] = {
113113 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
114114 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
115115 };
125125 SDOperand newroot, argt;
126126 bool needsLoad = false;
127127 MVT::ValueType ObjectVT = getValueType(I->getType());
128
128
129129 switch (ObjectVT) {
130130 default: assert(0 && "Unhandled argument type!");
131131 case MVT::i1:
132132 case MVT::i8:
133133 case MVT::i16:
134 case MVT::i32:
134 case MVT::i32:
135135 case MVT::i64:
136136 if (GPR_remaining > 0) {
137137 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
147147 case MVT::f64:
148148 if (FPR_remaining > 0) {
149149 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
150 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
150 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
151151 DAG.getRoot());
152152 --FPR_remaining;
153153 ++FPR_idx;
156156 }
157157 break;
158158 }
159
159
160160 // We need to load the argument to a virtual register if we determined above
161 // that we ran out of physical registers of the appropriate type
161 // that we ran out of physical registers of the appropriate type
162162 if (needsLoad) {
163163 unsigned SubregOffset = 0;
164164 switch (ObjectVT) {
166166 case MVT::i1:
167167 case MVT::i8: SubregOffset = 7; break;
168168 case MVT::i16: SubregOffset = 6; break;
169 case MVT::i32:
169 case MVT::i32:
170170 case MVT::f32: SubregOffset = 4; break;
171 case MVT::i64:
171 case MVT::i64:
172172 case MVT::f64: SubregOffset = 0; break;
173173 }
174174 int FI = MFI->CreateFixedObject(8, ArgOffset);
175175 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
176 FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
176 FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
177177 DAG.getConstant(SubregOffset, MVT::i64));
178178 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
179179 }
180
180
181181 // Every 4 bytes of argument space consumes one of the GPRs available for
182182 // argument passing.
183183 if (GPR_remaining > 0) {
185185 ++GPR_idx;
186186 }
187187 ArgOffset += 8;
188
188
189189 DAG.setRoot(newroot.getValue(1));
190190 ArgValues.push_back(argt);
191191 }
202202 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
203203 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
204204 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
205 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
205 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
206206 Val, FIN);
207207 MemOps.push_back(Store);
208208 // Increment the address by eight for the next argument to store
232232 DAG.getConstant(NumBytes, getPointerTy()));
233233 } else {
234234 NumBytes = 8 * Args.size(); // All arguments are rounded up to 8 bytes
235
236 // Just to be safe, we'll always reserve the full 48 bytes of linkage area
235
236 // Just to be safe, we'll always reserve the full 48 bytes of linkage area
237237 // plus 64 bytes of argument space in case any called code gets funky on us.
238238 if (NumBytes < 112) NumBytes = 112;
239239
247247 // passing.
248248 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
249249 DAG.getEntryNode());
250
250
251251 // Figure out which arguments are going to go in registers, and which in
252252 // memory. Also, if this is a vararg function, floating point operations
253253 // must be stored to our stack, and loaded into integer regs as well, if
255255 unsigned ArgOffset = 48;
256256 unsigned GPR_remaining = 8;
257257 unsigned FPR_remaining = 13;
258
258
259259 std::vector MemOps;
260260 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
261261 // PtrOff will be used to store the current argument to the stack if a
263263 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
264264 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
265265 MVT::ValueType ArgVT = getValueType(Args[i].second);
266
266
267267 switch (ArgVT) {
268268 default: assert(0 && "Unexpected ValueType for argument!");
269269 case MVT::i1:
322322 if (!MemOps.empty())
323323 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
324324 }
325
325
326326 std::vector RetVals;
327327 MVT::ValueType RetTyVT = getValueType(RetTy);
328328 if (RetTyVT != MVT::isVoid)
329329 RetVals.push_back(RetTyVT);
330330 RetVals.push_back(MVT::Other);
331331
332 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
332 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
333333 Chain, Callee, args_to_use), 0);
334334 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
335335 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
356356 }
357357 return std::make_pair(Result, Chain);
358358 }
359
359
360360
361361 std::pair PPC64TargetLowering::
362362 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
373373 /// SelectionDAG operations.
374374 //===--------------------------------------------------------------------===//
375375 class ISel : public SelectionDAGISel {
376
376
377377 /// Comment Here.
378378 PPC64TargetLowering PPC64Lowering;
379
379
380380 /// ExprMap - As shared expressions are codegen'd, we keep track of which
381381 /// vreg the value is produced in, so we only emit one copy of each compiled
382382 /// tree.
384384
385385 unsigned GlobalBaseReg;
386386 bool GlobalBaseInitialized;
387
387
388388 public:
389 ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
389 ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
390390 {}
391
391
392392 /// runOnFunction - Override this function in order to reset our per-function
393393 /// variables.
394394 virtual bool runOnFunction(Function &Fn) {
395395 // Make sure we re-emit a set of the global base reg if necessary
396396 GlobalBaseInitialized = false;
397397 return SelectionDAGISel::runOnFunction(Fn);
398 }
399
398 }
399
400400 /// InstructionSelectBasicBlock - This callback is invoked by
401401 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
402402 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
403403 DEBUG(BB->dump());
404404 // Codegen the basic block.
405405 Select(DAG.getRoot());
406
406
407407 // Clear state used for selection.
408408 ExprMap.clear();
409409 }
410
410
411411 unsigned getGlobalBaseReg();
412412 unsigned getConstDouble(double floatVal, unsigned Result);
413413 unsigned SelectSetCR0(SDOperand CC);
414414 unsigned SelectExpr(SDOperand N);
415415 unsigned SelectExprFP(SDOperand N, unsigned Result);
416416 void Select(SDOperand N);
417
417
418418 bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
419419 void SelectBranchCC(SDOperand N);
420420 };
434434 /// getImmediateForOpcode - This method returns a value indicating whether
435435 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
436436 /// values are either 0, 1 or 2. 0 indicates that either N is not a
437 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
437 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
438438 /// of 1 indicates that the constant may be used in normal immediate form. A
439439 /// return value of 2 indicates that the constant may be used in shifted
440440 /// immediate form. A return value of 3 indicates that log base 2 of the
445445 if (N.getOpcode() != ISD::Constant) return 0;
446446
447447 int v = (int)cast(N)->getSignExtended();
448
448
449449 switch(Opcode) {
450450 default: return 0;
451451 case ISD::ADD:
527527 return GlobalBaseReg;
528528 }
529529
530 /// getConstDouble - Loads a floating point value into a register, via the
530 /// getConstDouble - Loads a floating point value into a register, via the
531531 /// Constant Pool. Optionally takes a register in which to load the value.
532532 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
533533 unsigned Tmp1 = MakeReg(MVT::i64);
543543
544544 unsigned ISel::SelectSetCR0(SDOperand CC) {
545545 unsigned Opc, Tmp1, Tmp2;
546 static const unsigned CompareOpcodes[] =
546 static const unsigned CompareOpcodes[] =
547547 { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
548
548
549549 // If the first operand to the select is a SETCC node, then we can fold it
550550 // into the branch that selects which value to return.
551551 SetCCSDNode* SetCC = dyn_cast(CC.Val);
556556
557557 // Pass the optional argument U to getImmediateForOpcode for SETCC,
558558 // so that it knows whether the SETCC immediate range is signed or not.
559 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
559 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
560560 Tmp2, U)) {
561561 if (U)
562562 BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
585585 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
586586 offset = imm;
587587 return false;
588 }
588 }
589589 offset = SelectExpr(N.getOperand(1));
590590 return true;
591591 }
597597 void ISel::SelectBranchCC(SDOperand N)
598598 {
599599 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
600 MachineBasicBlock *Dest =
600 MachineBasicBlock *Dest =
601601 cast(N.getOperand(2))->getBasicBlock();
602602
603603 // Get the MBB we will fall through to so that we can hand it off to the
604604 // branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
605605 //ilist::iterator It = BB;
606606 //MachineBasicBlock *Fallthrough = ++It;
607
607
608608 Select(N.getOperand(0)); //chain
609609 unsigned Opc = SelectSetCR0(N.getOperand(1));
610610 // FIXME: Use this once we have something approximating two-way branches
644644 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
645645 unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
646646 unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
647
647
648648 ConstantFPSDNode *CN = dyn_cast(SetCC->getOperand(1));
649649 if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
650650 switch(SetCC->getCondition()) {
703703 assert(0 && "Should never get here");
704704 return 0;
705705 }
706
706
707707 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
708708 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
709709 Opc = SelectSetCR0(N.getOperand(0));
710710
711 // Create an iterator with which to insert the MBB for copying the false
711 // Create an iterator with which to insert the MBB for copying the false
712712 // value and the MBB to hold the PHI instruction for this SetCC.
713713 MachineBasicBlock *thisMBB = BB;
714714 const BasicBlock *LLVM_BB = BB->getBasicBlock();
748748 }
749749
750750 case ISD::FNEG:
751 if (!NoExcessFPPrecision &&
751 if (!NoExcessFPPrecision &&
752752 ISD::ADD == N.getOperand(0).getOpcode() &&
753753 N.getOperand(0).Val->hasOneUse() &&
754754 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
759759 Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
760760 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
761761 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
762 } else if (!NoExcessFPPrecision &&
762 } else if (!NoExcessFPPrecision &&
763763 ISD::SUB == N.getOperand(0).getOpcode() &&
764764 N.getOperand(0).Val->hasOneUse() &&
765765 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
778778 BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
779779 }
780780 return Result;
781
781
782782 case ISD::FABS:
783783 Tmp1 = SelectExpr(N.getOperand(0));
784784 BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
785785 return Result;
786786
787787 case ISD::FP_ROUND:
788 assert (DestType == MVT::f32 &&
789 N.getOperand(0).getValueType() == MVT::f64 &&
788 assert (DestType == MVT::f32 &&
789 N.getOperand(0).getValueType() == MVT::f64 &&
790790 "only f64 to f32 conversion supported here");
791791 Tmp1 = SelectExpr(N.getOperand(0));
792792 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
793793 return Result;
794794
795795 case ISD::FP_EXTEND:
796 assert (DestType == MVT::f64 &&
797 N.getOperand(0).getValueType() == MVT::f32 &&
796 assert (DestType == MVT::f64 &&
797 N.getOperand(0).getValueType() == MVT::f32 &&
798798 "only f32 to f64 conversion supported here");
799799 Tmp1 = SelectExpr(N.getOperand(0));
800800 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
806806 Tmp1 = dyn_cast(Node)->getReg();
807807 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
808808 return Result;
809
809
810810 case ISD::ConstantFP: {
811811 ConstantFPSDNode *CN = cast(N);
812812 Result = getConstDouble(CN->getValue(), Result);
813813 return Result;
814814 }
815
815
816816 case ISD::ADD:
817817 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
818818 N.getOperand(0).Val->hasOneUse()) {
865865 Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
866866 Tmp3 = MakeReg(MVT::i64); // temp reg to hold the conversion constant
867867 unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
868
868
869869 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
870870 MachineConstantPool *CP = BB->getParent()->getConstantPool();
871
871
872872 // FIXME: pull this FP constant generation stuff out into something like
873873 // the simple ISel's getReg.
874874 if (IsUnsigned) {
934934
935935 if (ISD::CopyFromReg == opcode)
936936 DestType = N.getValue(0).getValueType();
937
937
938938 if (DestType == MVT::f64 || DestType == MVT::f32)
939939 if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
940940 return SelectExprFP(N, Result);
982982 Tmp1 = cast(N)->getIndex();
983983 addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
984984 return Result;
985
985
986986 case ISD::GlobalAddress: {
987987 GlobalValue *GV = cast(N)->getGlobal();
988988 Tmp1 = MakeReg(MVT::i64);
10031003 MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
10041004 Node->getValueType(0) : cast(Node)->getExtraValueType();
10051005 bool sext = (ISD::SEXTLOAD == opcode);
1006
1006
10071007 // Make sure we generate both values.
10081008 if (Result != 1)
10091009 ExprMap[N.getValue(1)] = 1; // Generate the token
10241024 case MVT::f32: Opc = PPC::LFS; break;
10251025 case MVT::f64: Opc = PPC::LFD; break;
10261026 }
1027
1027
10281028 if (ConstantPoolSDNode *CP = dyn_cast(Address)) {
10291029 Tmp1 = MakeReg(MVT::i64);
10301030 int CPI = CP->getIndex();
10471047 }
10481048 return Result;
10491049 }
1050
1050
10511051 case ISD::CALL: {
10521052 unsigned GPR_idx = 0, FPR_idx = 0;
1053 static const unsigned GPR[] = {
1053 static const unsigned GPR[] = {
10541054 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
10551055 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
10561056 };
10651065
10661066 MachineInstr *CallMI;
10671067 // Emit the correct call instruction based on the type of symbol called.
1068 if (GlobalAddressSDNode *GASD =
1068 if (GlobalAddressSDNode *GASD =
10691069 dyn_cast(N.getOperand(1))) {
1070 CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
1070 CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
10711071 true);
1072 } else if (ExternalSymbolSDNode *ESSDN =
1072 } else if (ExternalSymbolSDNode *ESSDN =
10731073 dyn_cast(N.getOperand(1))) {
1074 CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
1074 CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
10751075 true);
10761076 } else {
10771077 Tmp1 = SelectExpr(N.getOperand(1));
10801080 CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
10811081 .addReg(PPC::R12);
10821082 }
1083
1083
10841084 // Load the register args to virtual regs
10851085 std::vector ArgVR;
10861086 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
11111111 break;
11121112 }
11131113 }
1114
1114
11151115 // Put the call instruction in the correct place in the MachineBasicBlock
11161116 BB->push_back(CallMI);
11171117
11391139 switch(cast(Node)->getExtraValueType()) {
11401140 default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
11411141 case MVT::i32:
1142 BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
1142 BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
11431143 break;
11441144 case MVT::i16:
1145 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
1145 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
11461146 break;
11471147 case MVT::i8:
1148 BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
1148 BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
11491149 break;
11501150 case MVT::i1:
11511151 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
11521152 break;
11531153 }
11541154 return Result;
1155
1155
11561156 case ISD::CopyFromReg:
11571157 if (Result == 1)
11581158 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
11711171 BuildMI(BB, PPC::SLD, 2, Result).addReg(Tmp1).addReg(Tmp2);
11721172 }
11731173 return Result;
1174
1174
11751175 case ISD::SRL:
11761176 Tmp1 = SelectExpr(N.getOperand(0));
11771177 if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) {
11831183 BuildMI(BB, PPC::SRD, 2, Result).addReg(Tmp1).addReg(Tmp2);
11841184 }
11851185 return Result;
1186
1186
11871187 case ISD::SRA:
11881188 Tmp1 = SelectExpr(N.getOperand(0));
11891189 if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) {
11941194 BuildMI(BB, PPC::SRAD, 2, Result).addReg(Tmp1).addReg(Tmp2);
11951195 }
11961196 return Result;
1197
1197
11981198 case ISD::ADD:
11991199 Tmp1 = SelectExpr(N.getOperand(0));
12001200 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
13011301 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
13021302 }
13031303 return Result;
1304
1304
13051305 case ISD::MUL:
13061306 Tmp1 = SelectExpr(N.getOperand(0));
13071307 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
13371337 addFrameReference(BuildMI(BB, PPC::LD, 2, Result), FrameIdx);
13381338 return Result;
13391339 }
1340
1340
13411341 case ISD::SETCC:
13421342 if (SetCCSDNode *SetCC = dyn_cast(Node)) {
13431343 Opc = SelectSetCR0(N);
1344
1344
13451345 unsigned TrueValue = MakeReg(MVT::i32);
13461346 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
13471347 unsigned FalseValue = MakeReg(MVT::i32);
13481348 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
13491349
1350 // Create an iterator with which to insert the MBB for copying the false
1350 // Create an iterator with which to insert the MBB for copying the false
13511351 // value and the MBB to hold the PHI instruction for this SetCC.
13521352 MachineBasicBlock *thisMBB = BB;
13531353 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13541354 ilist::iterator It = BB;
13551355 ++It;
1356
1356
13571357 // thisMBB:
13581358 // ...
13591359 // cmpTY cr0, r1, r2
13861386 }
13871387 assert(0 && "Is this legal?");
13881388 return 0;
1389
1389
13901390 case ISD::SELECT: {
13911391 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
13921392 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
13931393 Opc = SelectSetCR0(N.getOperand(0));
13941394
1395 // Create an iterator with which to insert the MBB for copying the false
1395 // Create an iterator with which to insert the MBB for copying the false
13961396 // value and the MBB to hold the PHI instruction for this SetCC.
13971397 MachineBasicBlock *thisMBB = BB;
13981398 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14661466 return; // Already selected.
14671467
14681468 SDNode *Node = N.Val;
1469
1469
14701470 switch (Node->getOpcode()) {
14711471 default:
14721472 Node->dump(); std::cerr << "\n";
14911491 BuildMI(BB, PPC::B, 1).addMBB(Dest);
14921492 return;
14931493 }
1494 case ISD::BRCOND:
1494 case ISD::BRCOND:
14951495 SelectBranchCC(N);
14961496 return;
14971497 case ISD::CopyToReg:
14981498 Select(N.getOperand(0));
14991499 Tmp1 = SelectExpr(N.getOperand(1));
15001500 Tmp2 = cast(N)->getReg();
1501
1501
15021502 if (Tmp1 != Tmp2) {
1503 if (N.getOperand(1).getValueType() == MVT::f64 ||
1503 if (N.getOperand(1).getValueType() == MVT::f64 ||
15041504 N.getOperand(1).getValueType() == MVT::f32)
15051505 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
15061506 else
15451545 }
15461546 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
15471547 return;
1548 case ISD::TRUNCSTORE:
1549 case ISD::STORE:
1548 case ISD::TRUNCSTORE:
1549 case ISD::STORE:
15501550 {
15511551 SDOperand Chain = N.getOperand(0);
15521552 SDOperand Value = N.getOperand(1);
15811581 {
15821582 int offset;
15831583 bool idx = SelectAddr(Address, Tmp2, offset);
1584 if (idx) {
1584 if (idx) {
15851585 Opc = IndexedOpForOp(Opc);
15861586 BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
15871587 } else {
16101610 /// description file.
16111611 ///
16121612 FunctionPass *llvm::createPPC64ISelPattern(TargetMachine &TM) {
1613 return new ISel(TM);
1614 }
1615
1613 return new ISel(TM);
1614 }
1615
0 //===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC implementation of the TargetInstrInfo class.
0 //===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC64 implementation of the TargetInstrInfo class.
4646 case PPC::BGE: return PPC::BLT;
4747 case PPC::BGT: return PPC::BLE;
4848 case PPC::BLE: return PPC::BGT;
49 }
49 }
5050 }
5151 };
5252
0 //===- PPC64JITInfo.h - PowerPC/AIX impl. of the JIT interface -*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC/AIX implementation of the TargetJITInfo class.
0 //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC64 implementation of the MRegisterInfo class.
3737
3838 PPC64RegisterInfo::PPC64RegisterInfo()
3939 : PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
40 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
40 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
4141 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
4242 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
4343 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
6161 case 1: return 0;
6262 case 2: return 1;
6363 case 4: return 2;
64 case 8: return 3;
64 case 8: return 3;
6565 }
6666 } else if (RC == PPC64::FPRCRegisterClass) {
6767 switch (RC->getSize()) {
7474 abort();
7575 }
7676
77 void
77 void
7878 PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
7979 MachineBasicBlock::iterator MI,
8080 unsigned SrcReg, int FrameIdx) const {
81 static const unsigned Opcode[] = {
82 PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
81 static const unsigned Opcode[] = {
82 PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
8383 };
8484 unsigned OC = Opcode[getIdx(getClass(SrcReg))];
8585 if (SrcReg == PPC::LR) {
9696 PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
9797 MachineBasicBlock::iterator MI,
9898 unsigned DestReg, int FrameIdx) const{
99 static const unsigned Opcode[] = {
100 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
99 static const unsigned Opcode[] = {
100 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
101101 };
102102 unsigned OC = Opcode[getIdx(getClass(DestReg))];
103103 if (DestReg == PPC::LR) {
120120 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
121121 } else if (RC == PPC64::FPRCRegisterClass) {
122122 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
123 } else {
123 } else {
124124 std::cerr << "Attempt to copy register that is not GPR or FPR";
125125 abort();
126126 }
154154 // alignment boundary.
155155 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
156156 Amount = (Amount+Align-1)/Align*Align;
157
157
158158 // Replace the pseudo instruction with a new instruction...
159159 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
160160 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
175175 MachineInstr &MI = *II;
176176 MachineBasicBlock &MBB = *MI.getParent();
177177 MachineFunction &MF = *MBB.getParent();
178
178
179179 while (!MI.getOperand(i).isFrameIndex()) {
180180 ++i;
181181 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
197197 // SP before having the stack size subtracted from it, then add the stack size
198198 // to Offset to get the correct offset.
199199 Offset += MF.getFrameInfo()->getStackSize();
200
200
201201 if (Offset > 32767 || Offset < -32768) {
202202 // Insert a set of r0 with the full offset value before the ld, st, or add
203203 MachineBasicBlock *MBB = MI.getParent();
207207 // convert into indexed form of the instruction
208208 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
209209 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
210 unsigned NewOpcode =
210 unsigned NewOpcode =
211211 const_cast& >(ImmToIdxMap)[MI.getOpcode()];
212212 assert(NewOpcode && "No indexed form of load or store available!");
213213 MI.setOpcode(NewOpcode);
225225 MachineBasicBlock::iterator MBBI = MBB.begin();
226226 MachineFrameInfo *MFI = MF.getFrameInfo();
227227 MachineInstr *MI;
228
228
229229 // Get the number of bytes to allocate from the FrameInfo
230230 unsigned NumBytes = MFI->getStackSize();
231231
232232 // If we have calls, we cannot use the red zone to store callee save registers
233233 // and we must set up a stack frame, so calculate the necessary size here.
234234 if (MFI->hasCalls()) {
235 // We reserve argument space for call sites in the function immediately on
236 // entry to the current function. This eliminates the need for add/sub
235 // We reserve argument space for call sites in the function immediately on
236 // entry to the current function. This eliminates the need for add/sub
237237 // brackets around call sites.
238238 NumBytes += MFI->getMaxCallFrameSize();
239239 }
241241 // Do we need to allocate space on the stack?
242242 if (NumBytes == 0) return;
243243
244 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
244 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
245245 // of the stack and round the size to a multiple of the alignment.
246246 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
247247 unsigned GPRSize = getSpillSize(PPC::R1)/8;
265265 MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
266266 MBB.insert(MBBI, MI);
267267 }
268
268
269269 if (hasFP(MF)) {
270270 MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
271271 MBB.insert(MBBI, MI);
281281 MachineInstr *MI;
282282 assert(MBBI->getOpcode() == PPC::BLR &&
283283 "Can only insert epilog into returning blocks");
284
284
285285 // Get the number of bytes allocated from the FrameInfo...
286286 unsigned NumBytes = MFI->getStackSize();
287287
313313 case Type::PointerTyID:
314314 case Type::LongTyID:
315315 case Type::ULongTyID: return &GPRCInstance;
316
316
317317 case Type::FloatTyID:
318318 case Type::DoubleTyID: return &FPRCInstance;
319319 }
0 //===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the PowerPC implementation of the MRegisterInfo class.
3535 void loadRegFromStackSlot(MachineBasicBlock &MBB,
3636 MachineBasicBlock::iterator MBBI,
3737 unsigned DestReg, int FrameIndex) const;
38
38
3939 void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
4040 unsigned DestReg, unsigned SrcReg,
4141 const TargetRegisterClass *RC) const;
0 //===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
8 //
8 //
99 // This file declares the PowerPC specific subclass of TargetMachine.
1010 //
1111 //===----------------------------------------------------------------------===//
0 //===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains a printer that converts from our internal representation
4444 struct PowerPCAsmPrinter : public AsmPrinter {
4545 std::set FnStubs, GVStubs, LinkOnceStubs;
4646 std::set Strings;
47
47
4848 PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
4949 : AsmPrinter(O, TM), LabelNumber(0) {}
5050
5151 /// Unique incrementer for label values for referencing Global values.
5252 ///
5353 unsigned LabelNumber;
54
54
5555 virtual const char *getPassName() const {
5656 return "PowerPC Assembly Printer";
5757 }
108108 if (MI->getOperand(OpNo).isImmediate()) {
109109 O << "$+" << MI->getOperand(OpNo).getImmedValue();
110110 } else {
111 printOp(MI->getOperand(OpNo),
111 printOp(MI->getOperand(OpNo),
112112 TM.getInstrInfo()->isCall(MI->getOpcode()));
113113 }
114114 }
157157 }
158158 O << 4 * RegNo + value;
159159 }
160
160
161161 virtual void printConstantPool(MachineConstantPool *MCP) = 0;
162 virtual bool runOnMachineFunction(MachineFunction &F) = 0;
162 virtual bool runOnMachineFunction(MachineFunction &F) = 0;
163163 virtual bool doFinalization(Module &M) = 0;
164164 };
165
165
166166 /// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
167167 /// X
168168 ///
182182 }
183183
184184 void printConstantPool(MachineConstantPool *MCP);
185 bool runOnMachineFunction(MachineFunction &F);
185 bool runOnMachineFunction(MachineFunction &F);
186186 bool doFinalization(Module &M);
187187 };
188
188
189189 /// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
190190 ///
191191 struct AIXAsmPrinter : public PowerPCAsmPrinter {
201201 Data64bitsDirective = 0; // we can't emit a 64-bit unit
202202 AlignmentIsInBytes = false; // Alignment is by power of 2.
203203 }
204
204
205205 virtual const char *getPassName() const {
206206 return "AIX PPC Assembly Printer";
207207 }
208208
209209 void printConstantPool(MachineConstantPool *MCP);
210 bool runOnMachineFunction(MachineFunction &F);
210 bool runOnMachineFunction(MachineFunction &F);
211211 bool doInitialization(Module &M);
212212 bool doFinalization(Module &M);
213213 };
257257
258258 /// SwitchStringSection - manage the changes required to output bytes as
259259 /// characters in a string vs. numeric decimal values
260 ///
260 ///
261261 static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
262262 StringSection &Current) {
263263 if (Current == None) {
268268 } else if (Current == Alpha) {
269269 if (NewSect == None)
270270 O << "\"";
271 else if (NewSect == Numeric)
271 else if (NewSect == Numeric)
272272 O << "\"\n"
273273 << "\t.byte ";
274274 } else if (Current == Numeric) {
309309 O << '\n';
310310 }
311311
312 /// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
313 /// code for a MachineFunction to the given output stream, in a format that the
312 /// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
313 /// code for a MachineFunction to the given output stream, in a format that the
314314 /// Darwin assembler can deal with.
315315 ///
316316 FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
318318 }
319319
320320 /// createAIXAsmPrinterPass - Returns a pass that prints the PPC assembly code
321 /// for a MachineFunction to the given output stream, in a format that the
321 /// for a MachineFunction to the given output stream, in a format that the
322322 /// AIX 5L assembler can deal with.
323323 ///
324324 FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
331331 void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
332332 const MRegisterInfo &RI = *TM.getRegisterInfo();
333333 int new_symbol;
334
334
335335 switch (MO.getType()) {
336336 case MachineOperand::MO_VirtualRegister:
337337 if (Value *V = MO.getVRegValueOrNull()) {
354354 std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
355355 abort();
356356 return;
357
357
358358 case MachineOperand::MO_MachineBasicBlock: {
359359 MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
360360 O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
390390 O << "L" << Name << "$stub";
391391 return;
392392 }
393
393
394394 // External or weakly linked global variables need non-lazily-resolved stubs
395395 if ((GV->isExternal() || GV->hasWeakLinkage() || GV->hasLinkOnceLinkage())){
396396 if (GV->hasLinkOnceLinkage())
404404 O << Mang->getValueName(GV);
405405 return;
406406 }
407
407
408408 default:
409409 O << "";
410410 return;
430430 SH = 32-SH;
431431 }
432432 if (FoundMnemonic) {
433 printOperand(MI, 0, MVT::i64);
434 O << ", ";
435 printOperand(MI, 1, MVT::i64);
433 printOperand(MI, 0, MVT::i64);
434 O << ", ";
435 printOperand(MI, 1, MVT::i64);
436436 O << ", " << (unsigned int)SH << "\n";
437437 return;
438438 }
439439 }
440
440
441441 if (printInstruction(MI))
442442 return; // Printer was automatically generated
443
443
444444 assert(0 && "Unhandled instruction in asm writer!");
445445 abort();
446446 return;
489489 void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
490490 const std::vector &CP = MCP->getConstants();
491491 const TargetData &TD = TM.getTargetData();
492
492
493493 if (CP.empty()) return;
494494
495495 for (unsigned i = 0, e = CP.size(); i != e; ++i) {
515515 unsigned Align = TD.getTypeAlignmentShift(C->getType());
516516
517517 if (C->isNullValue() && /* FIXME: Verify correct */
518 (I->hasInternalLinkage() || I->hasWeakLinkage() ||
518 (I->hasInternalLinkage() || I->hasWeakLinkage() ||
519519 I->hasLinkOnceLinkage())) {
520520 SwitchSection(O, CurSection, ".data");
521521 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
522522 if (I->hasInternalLinkage())
523523 O << ".lcomm " << name << "," << Size << "," << Align;
524 else
524 else
525525 O << ".comm " << name << "," << Size;
526526 O << "\t\t; ";
527527 WriteAsOperand(O, I, true, true, &M);
534534 << ".private_extern " << name << '\n'
535535 << ".section __DATA,__datacoal_nt,coalesced,no_toc\n";
536536 LinkOnceStubs.insert(name);
537 break;
537 break;
538538 case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
539539 // Nonnull linkonce -> weak
540540 O << "\t.weak " << name << "\n";
567567 }
568568
569569 // Output stubs for dynamically-linked functions
570 for (std::set::iterator i = FnStubs.begin(), e = FnStubs.end();
570 for (std::set::iterator i = FnStubs.begin(), e = FnStubs.end();
571571 i != e; ++i)
572572 {
573573 O << ".data\n";
596596 // Output stubs for external global variables
597597 if (GVStubs.begin() != GVStubs.end())
598598 O << ".data\n.non_lazy_symbol_pointer\n";
599 for (std::set::iterator i = GVStubs.begin(), e = GVStubs.end();
599 for (std::set::iterator i = GVStubs.begin(), e = GVStubs.end();
600600 i != e; ++i) {
601601 O << "L" << *i << "$non_lazy_ptr:\n";
602602 O << "\t.indirect_symbol " << *i << "\n";
603603 O << "\t.long\t0\n";
604604 }
605
605
606606 // Output stubs for link-once variables
607607 if (LinkOnceStubs.begin() != LinkOnceStubs.end())
608608 O << ".data\n.align 2\n";
609 for (std::set::iterator i = LinkOnceStubs.begin(),
609 for (std::set::iterator i = LinkOnceStubs.begin(),
610610 e = LinkOnceStubs.end(); i != e; ++i) {
611611 O << "L" << *i << "$non_lazy_ptr:\n"
612612 << "\t.long\t" << *i << '\n';
613613 }
614
614
615615 AsmPrinter::doFinalization(M);
616616 return false; // success
617617 }
671671 void AIXAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
672672 const std::vector &CP = MCP->getConstants();
673673 const TargetData &TD = TM.getTargetData();
674
674
675675 if (CP.empty()) return;
676676
677677 for (unsigned i = 0, e = CP.size(); i != e; ++i) {
688688 const TargetData &TD = TM.getTargetData();
689689 std::string CurSection;
690690
691 O << "\t.machine \"ppc64\"\n"
691 O << "\t.machine \"ppc64\"\n"
692692 << "\t.toc\n"
693693 << "\t.csect .text[PR]\n";
694694
696696 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) {
697697 if (!I->hasInitializer())
698698 continue;
699
699
700700 std::string Name = I->getName();
701701 Constant *C = I->getInitializer();
702702 // N.B.: We are defaulting to writable strings
703 if (I->hasExternalLinkage()) {
703 if (I->hasExternalLinkage()) {
704704 O << "\t.globl " << Name << '\n'
705705 << "\t.csect .data[RW],3\n";
706706 } else {
0 //===-- PowerPCBranchSelector.cpp - Emit long conditional branches-*- C++ -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by Nate Baegeman and is distributed under the
55 // University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains a pass that scans a machine function to determine which
9 // This file contains a pass that scans a machine function to determine which
1010 // conditional branches need more than 16 bits of displacement to reach their
1111 // target basic block. It does this in two passes; a calculation of basic block
1212 // positions pass, and a branch psuedo op to machine branch opcode pass. This
2929 // OffsetMap - Mapping between BB and byte offset from start of function
3030 std::map OffsetMap;
3131
32 /// bytesForOpcode - A convenience function for totalling up the number of
32 /// bytesForOpcode - A convenience function for totalling up the number of
3333 /// bytes in a basic block.
3434 ///
3535 static unsigned bytesForOpcode(unsigned opcode) {
3636 switch (opcode) {
3737 case PPC::COND_BRANCH:
3838 // while this will be 4 most of the time, if we emit 12 it is just a
39 // minor pessimization that saves us from having to worry about
39 // minor pessimization that saves us from having to worry about
4040 // keeping the offsets up to date later when we emit long branch glue.
4141 return 12;
4242 case PPC::IMPLICIT_DEF: // no asm emitted
4343 return 0;
4444 break;
45 default:
45 default:
4646 return 4; // PowerPC instructions are all 4 bytes
4747 break;
4848 }
4949 }
50
50
5151 virtual bool runOnMachineFunction(MachineFunction &Fn) {
5252 // Running total of instructions encountered since beginning of function
5353 unsigned ByteCount = 0;
5454
5555 // For each MBB, add its offset to the offset map, and count up its
5656 // instructions
57 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
57 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
5858 ++MFI) {
5959 MachineBasicBlock *MBB = MFI;
6060 OffsetMap[MBB] = ByteCount;
7979 // b .L_TARGET_MBB
8080 // b .L_FALLTHROUGH_MBB
8181
82 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
82 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
8383 ++MFI) {
8484 MachineBasicBlock *MBB = MFI;
85
85
8686 for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
8787 MBBI != EE; ++MBBI) {
8888 if (MBBI->getOpcode() == PPC::COND_BRANCH) {
9191 // 1. bc opcode
9292 // 2. target MBB
9393 // 3. fallthrough MBB
94 MachineBasicBlock *trueMBB =
94 MachineBasicBlock *trueMBB =
9595 MBBI->getOperand(2).getMachineBasicBlock();
96 MachineBasicBlock *falseMBB =
96 MachineBasicBlock *falseMBB =
9797 MBBI->getOperand(3).getMachineBasicBlock();
98
98
9999 int Displacement = OffsetMap[trueMBB] - ByteCount;
100100 unsigned Opcode = MBBI->getOperand(1).getImmedValue();
101101 unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
0 //===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
8 //
8 //
99 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
1010 // JIT-compile bytecode to native PowerPC.
1111 //
4141 int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
4242
4343 public:
44 PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
44 PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
4545 : TM(T), MCE(M) {}
4646
4747 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
5757 /// emitWord - write a 32-bit word to memory at the current PC
5858 ///
5959 void emitWord(unsigned w) { MCE.emitWord(w); }
60
60
6161 /// getValueBit - return the particular bit of Val
6262 ///
6363 unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
7979 bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
8080 MachineCodeEmitter &MCE) {
8181 // Machine code emitter pass for PowerPC
82 PM.add(new PPC32CodeEmitter(*this, MCE));
82 PM.add(new PPC32CodeEmitter(*this, MCE));
8383 // Delete machine code for this function after emitting it
8484 PM.add(createMachineCodeDeleter());
8585 return false;
101101 << "\n");
102102 unsigned Instr = *Ref;
103103 intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
104
104
105105 switch (Instr >> 26) {
106106 default: assert(0 && "Unknown branch user!");
107107 case 18: // This is B or BL
141141
142142 static unsigned enumRegToMachineReg(unsigned enumReg) {
143143 switch (enumReg) {
144 case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
145 case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
144 case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
145 case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
146146 case PPC::R2 : case PPC::F2 : case PPC::CR2: return 2;
147 case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
148 case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
147 case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
148 case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
149149 case PPC::R5 : case PPC::F5 : case PPC::CR5: return 5;
150 case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
151 case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
150 case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
151 case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
152152 case PPC::R8 : case PPC::F8 : return 8;
153 case PPC::R9 : case PPC::F9 : return 9;
154 case PPC::R10: case PPC::F10: return 10;
153 case PPC::R9 : case PPC::F9 : return 9;
154 case PPC::R10: case PPC::F10: return 10;
155155 case PPC::R11: case PPC::F11: return 11;
156 case PPC::R12: case PPC::F12: return 12;
157 case PPC::R13: case PPC::F13: return 13;
156 case PPC::R12: case PPC::F12: return 12;
157 case PPC::R13: case PPC::F13: return 13;
158158 case PPC::R14: case PPC::F14: return 14;
159 case PPC::R15: case PPC::F15: return 15;
160 case PPC::R16: case PPC::F16: return 16;
159 case PPC::R15: case PPC::F15: return 15;
160 case PPC::R16: case PPC::F16: return 16;
161161 case PPC::R17: case PPC::F17: return 17;
162 case PPC::R18: case PPC::F18: return 18;
163 case PPC::R19: case PPC::F19: return 19;
162 case PPC::R18: case PPC::F18: return 18;
163 case PPC::R19: case PPC::F19: return 19;
164164 case PPC::R20: case PPC::F20: return 20;
165165 case PPC::R21: case PPC::F21: return 21;
166 case PPC::R22: case PPC::F22: return 22;
167 case PPC::R23: case PPC::F23: return 23;
166 case PPC::R22: case PPC::F22: return 22;
167 case PPC::R23: case PPC::F23: return 23;
168168 case PPC::R24: case PPC::F24: return 24;
169 case PPC::R25: case PPC::F25: return 25;
170 case PPC::R26: case PPC::F26: return 26;
169 case PPC::R25: case PPC::F25: return 25;
170 case PPC::R26: case PPC::F26: return 26;
171171 case PPC::R27: case PPC::F27: return 27;
172 case PPC::R28: case PPC::F28: return 28;
173 case PPC::R29: case PPC::F29: return 29;
172 case PPC::R28: case PPC::F28: return 28;
173 case PPC::R29: case PPC::F29: return 29;
174174 case PPC::R30: case PPC::F30: return 30;
175175 case PPC::R31: case PPC::F31: return 31;
176176 default:
180180 }
181181
182182 int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
183
183
184184 int rv = 0; // Return value; defaults to 0 for unhandled cases
185185 // or things that get fixed up later by the JIT.
186186 if (MO.isRegister()) {
0 //===-- PowerPCFrameInfo.h - Define TargetFrameInfo for PowerPC -*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file was developed by the LLVM research group and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 //
2121 class PowerPCFrameInfo: public TargetFrameInfo {
2222 const TargetMachine &TM;
2323 std::pair LR[1];
24
24
2525 public:
2626 PowerPCFrameInfo(const TargetMachine &tm, bool LP64)
2727 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
33 //
44 // This file was developed by Nate Begeman and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
4646 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
4747 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
4848 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
49
49
5050 // PowerPC has no intrinsics for these particular operations
5151 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
5252 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
5555 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
5656 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
5757 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58
58
5959 // PowerPC has no SREM/UREM instructions
6060 setOperationAction(ISD::SREM, MVT::i32, Expand);
6161 setOperationAction(ISD::UREM, MVT::i32, Expand);
6262
6363 setSetCCResultContents(ZeroOrOneSetCCResult);
6464 addLegalFPImmediate(+0.0); // Necessary for FSEL
65 addLegalFPImmediate(-0.0); //
65 addLegalFPImmediate(-0.0); //
6666
6767 computeRegisterProperties();
6868 }
7171 /// lower the arguments for the specified function, into the specified DAG.
7272 virtual std::vector
7373 LowerArguments(Function &F, SelectionDAG &DAG);
74
74
7575 /// LowerCallTo - This hook lowers an abstract call to a function into an
7676 /// actual call.
7777 virtual std::pair
7878 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
7979 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
80
80
8181 virtual std::pair
8282 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
83
83
8484 virtual std::pair
8585 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
8686 const Type *ArgTy, SelectionDAG &DAG);
101101 MachineFrameInfo *MFI = MF.getFrameInfo();
102102 MachineBasicBlock& BB = MF.front();
103103 std::vector ArgValues;
104
105 // Due to the rather complicated nature of the PowerPC ABI, rather than a
104
105 // Due to the rather complicated nature of the PowerPC ABI, rather than a
106106 // fixed size array of physical args, for the sake of simplicity let the STL
107107 // handle tracking them for us.
108108 std::vector argVR, argPR, argOp;
110110 unsigned GPR_remaining = 8;
111111 unsigned FPR_remaining = 13;
112112 unsigned GPR_idx = 0, FPR_idx = 0;
113 static const unsigned GPR[] = {
113 static const unsigned GPR[] = {
114114 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
115115 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
116116 };
128128 bool needsLoad = false;
129129 bool ArgLive = !I->use_empty();
130130 MVT::ValueType ObjectVT = getValueType(I->getType());
131
131
132132 switch (ObjectVT) {
133133 default: assert(0 && "Unhandled argument type!");
134134 case MVT::i1:
135135 case MVT::i8:
136136 case MVT::i16:
137 case MVT::i32:
137 case MVT::i32:
138138 ObjSize = 4;
139139 if (!ArgLive) break;
140140 if (GPR_remaining > 0) {
169169 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
170170 newroot = argLo;
171171 } else {
172 needsLoad = true;
172 needsLoad = true;
173173 }
174174 break;
175175 case MVT::f32:
178178 if (!ArgLive) break;
179179 if (FPR_remaining > 0) {
180180 MF.addLiveIn(FPR[FPR_idx]);
181 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
181 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
182182 DAG.getRoot());
183183 --FPR_remaining;
184184 ++FPR_idx;
187187 }
188188 break;
189189 }
190
190
191191 // We need to load the argument to a virtual register if we determined above
192 // that we ran out of physical registers of the appropriate type
192 // that we ran out of physical registers of the appropriate type
193193 if (needsLoad) {
194194 unsigned SubregOffset = 0;
195195 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
196196 if (ObjectVT == MVT::i16) SubregOffset = 2;
197197 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
198198 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
199 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
199 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
200200 DAG.getConstant(SubregOffset, MVT::i32));
201201 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
202202 }
203
203
204204 // Every 4 bytes of argument space consumes one of the GPRs available for
205205 // argument passing.
206206 if (GPR_remaining > 0) {
211211 ArgOffset += ObjSize;
212212 if (newroot.Val)
213213 DAG.setRoot(newroot.getValue(1));
214
214
215215 ArgValues.push_back(argt);
216216 }
217217
227227 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
228228 MF.addLiveIn(GPR[GPR_idx]);
229229 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
230 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
230 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
231231 Val, FIN);
232232 MemOps.push_back(Store);
233233 // Increment the address by four for the next argument to store
291291 NumBytes += 8;
292292 break;
293293 }
294
295 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
294
295 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
296296 // plus 32 bytes of argument space in case any called code gets funky on us.
297297 if (NumBytes < 56) NumBytes = 56;
298298
306306 // passing.
307307 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
308308 DAG.getEntryNode());
309
309
310310 // Figure out which arguments are going to go in registers, and which in
311311 // memory. Also, if this is a vararg function, floating point operations
312312 // must be stored to our stack, and loaded into integer regs as well, if
314314 unsigned ArgOffset = 24;
315315 unsigned GPR_remaining = 8;
316316 unsigned FPR_remaining = 13;
317
317
318318 std::vector MemOps;
319319 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
320320 // PtrOff will be used to store the current argument to the stack if a
322322 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
323323 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
324324 MVT::ValueType ArgVT = getValueType(Args[i].second);
325
325
326326 switch (ArgVT) {
327327 default: assert(0 && "Unexpected ValueType for argument!");
328328 case MVT::i1:
350350 // in it, and store the other half to the stack. If we have two or more
351351 // free GPRs, then we can pass both halves of the i64 in registers.
352352 if (GPR_remaining > 0) {
353 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
353 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
354354 Args[i].first, DAG.getConstant(1, MVT::i32));
355 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
355 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
356356 Args[i].first, DAG.getConstant(0, MVT::i32));
357357 args_to_use.push_back(Hi);
358358 --GPR_remaining;
419419 if (!MemOps.empty())
420420 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
421421 }
422
422
423423 std::vector RetVals;
424424 MVT::ValueType RetTyVT = getValueType(RetTy);
425425 if (RetTyVT != MVT::isVoid)
426426 RetVals.push_back(RetTyVT);
427427 RetVals.push_back(MVT::Other);
428428
429 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
429 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
430430 Chain, Callee, args_to_use), 0);
431431 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
432432 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
461461 }
462462 return std::make_pair(Result, Chain);
463463 }
464
464
465465
466466 std::pair PPC32TargetLowering::
467467 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
483483 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
484484 // for sdiv and udiv until it is put into the future
485485 // dag combiner.
486
486
487487 /// ExprMap - As shared expressions are codegen'd, we keep track of which
488488 /// vreg the value is produced in, so we only emit one copy of each compiled
489489 /// tree.
495495 public:
496496 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
497497 ISelDAG(0) {}
498
498
499499 /// runOnFunction - Override this function in order to reset our per-function
500500 /// variables.
501501 virtual bool runOnFunction(Function &Fn) {
502502 // Make sure we re-emit a set of the global base reg if necessary
503503 GlobalBaseInitialized = false;
504504 return SelectionDAGISel::runOnFunction(Fn);
505 }
506
505 }
506
507507 /// InstructionSelectBasicBlock - This callback is invoked by
508508 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
509509 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
511511 // Codegen the basic block.
512512 ISelDAG = &DAG;
513513 Select(DAG.getRoot());
514
514
515515 // Clear state used for selection.
516516 ExprMap.clear();
517517 ISelDAG = 0;
520520 // dag -> dag expanders for integer divide by constant
521521 SDOperand BuildSDIVSequence(SDOperand N);
522522 SDOperand BuildUDIVSequence(SDOperand N);
523
523
524524 unsigned getGlobalBaseReg();
525525 unsigned getConstDouble(double floatVal, unsigned Result);
526526 void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
531531 unsigned SelectExpr(SDOperand N, bool Recording=false);
532532 unsigned SelectExprFP(SDOperand N, unsigned Result);
533533 void Select(SDOperand N);
534
534
535535 bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
536536 void SelectBranchCC(SDOperand N);
537537 };
554554 // not, since all 1's are not contiguous.
555555 static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
556556 bool isRun = true;
557 MB = 0;
557 MB = 0;
558558 ME = 0;
559559
560560 // look for first set bit
566566 break;
567567 }
568568 }
569
569
570570 // look for last set bit
571571 for (; i < 32; i++) {
572572 if ((Val & (1 << (31 - i))) == 0)
579579 if ((Val & (1 << (31 - i))) != 0)
580580 break;
581581 }
582
582
583583 // if we exhausted all the bits, we found a match at this point for 0*1*0*
584584 if (i == 32)
585585 return true;
595595 if ((Val & (1 << (31 - i))) == 0)
596596 break;
597597 }
598
598
599599 // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
600600 // the value is not a run of ones.
601601 if (i == 32)
619619 if (N.getOpcode() != ISD::Constant) return 0;
620620
621621 int v = (int)cast(N)->getSignExtended();
622
622
623623 switch(Opcode) {
624624 default: return 0;
625625 case ISD::ADD:
665665 switch(NodeOpcode) {
666666 default: return false;
667667 case ISD::AND:
668 case ISD::OR:
668 case ISD::OR:
669669 return true;
670670 }
671671 }
714714 static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
715715 switch (Condition) {
716716 default: assert(0 && "Unknown condition!"); abort();
717 case ISD::SETULT:
717 case ISD::SETULT:
718718 case ISD::SETLT: Inv = false; return 0;
719719 case ISD::SETUGE:
720720 case ISD::SETGE: Inv = true; return 0;
743743 return 0;
744744 }
745745
746 // Structure used to return the necessary information to codegen an SDIV as
746 // Structure used to return the necessary information to codegen an SDIV as
747747 // a multiply.
748748 struct ms {
749749 int m; // magic number
757757 };
758758
759759 /// magic - calculate the magic numbers required to codegen an integer sdiv as
760 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
760 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
761761 /// or -1.
762762 static struct ms magic(int d) {
763763 int p;
764764 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
765765 const unsigned int two31 = 2147483648U; // 2^31
766766 struct ms mag;
767
767
768768 ad = abs(d);
769769 t = two31 + ((unsigned int)d >> 31);
770770 anc = t - 1 - t%ad; // absolute value of nc
846846 int d = (int)cast(N.getOperand(1))->getSignExtended();
847847 ms magics = magic(d);
848848 // Multiply the numerator (operand 0) by the magic value
849 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
849 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
850850 ISelDAG->getConstant(magics.m, MVT::i32));
851851 // If d > 0 and m < 0, add the numerator
852852 if (d > 0 && magics.m < 0)
856856 Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
857857 // Shift right algebraic if shift value is nonzero
858858 if (magics.s > 0)
859 Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
859 Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
860860 ISelDAG->getConstant(magics.s, MVT::i32));
861861 // Extract the sign bit and add it to the quotient
862 SDOperand T =
862 SDOperand T =
863863 ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
864864 return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
865865 }
869869 /// multiplying by a magic number. See:
870870 ///
871871 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
872 unsigned d =
872 unsigned d =
873873 (unsigned)cast(N.getOperand(1))->getSignExtended();
874874 mu magics = magicu(d);
875875 // Multiply the numerator (operand 0) by the magic value
876 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
876 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
877877 ISelDAG->getConstant(magics.m, MVT::i32));
878878 if (magics.a == 0) {
879 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
879 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
880880 ISelDAG->getConstant(magics.s, MVT::i32));
881881 } else {
882882 SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
883 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
883 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
884884 ISelDAG->getConstant(1, MVT::i32));
885885 NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
886 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
886 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
887887 ISelDAG->getConstant(magics.s-1, MVT::i32));
888888 }
889889 return Q;
905905 return GlobalBaseReg;
906906 }
907907
908 /// getConstDouble - Loads a floating point value into a register, via the
908 /// getConstDouble - Loads a floating point value into a register, via the
909909 /// Constant Pool. Optionally takes a register in which to load the value.
910910 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
911911 unsigned Tmp1 = MakeReg(MVT::i32);
919919 return Result;
920920 }
921921
922 /// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
922 /// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
923923 /// Inv is true, then invert the result.
924924 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
925925 unsigned IntCR = MakeReg(MVT::i32);
936936 }
937937 }
938938
939 /// SelectBitfieldInsert - turn an or of two masked values into
939 /// SelectBitfieldInsert - turn an or of two masked values into
940940 /// the rotate left word immediate then mask insert (rlwimi) instruction.
941941 /// Returns true on success, false if the caller still needs to select OR.
942942 ///
950950 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
951951 unsigned Op0Opc = OR.getOperand(0).getOpcode();
952952 unsigned Op1Opc = OR.getOperand(1).getOpcode();
953
953
954954 // Verify that we have the correct opcodes
955955 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
956956 return false;
957957 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
958958 return false;
959
959
960960 // Generate Mask value for Target
961 if (ConstantSDNode *CN =
961 if (ConstantSDNode *CN =
962962 dyn_cast(OR.getOperand(0).getOperand(1).Val)) {
963963 switch(Op0Opc) {
964964 case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
968968 } else {
969969 return false;
970970 }
971
971
972972 // Generate Mask value for Insert
973 if (ConstantSDNode *CN =
973 if (ConstantSDNode *CN =
974974 dyn_cast(OR.getOperand(1).getOperand(1).Val)) {
975975 switch(Op1Opc) {
976 case ISD::SHL:
977 Amount = CN->getValue();
976 case ISD::SHL:
977 Amount = CN->getValue();
978978 InsMask <<= Amount;
979979 if (Op0Opc == ISD::SRL) IsRotate = true;
980980 break;
981 case ISD::SRL:
982 Amount = CN->getValue();
983 InsMask >>= Amount;
981 case ISD::SRL:
982 Amount = CN->getValue();
983 InsMask >>= Amount;
984984 Amount = 32-Amount;
985985 if (Op0Opc == ISD::SHL) IsRotate = true;
986986 break;
987 case ISD::AND:
987 case ISD::AND:
988988 InsMask &= (unsigned)CN->getValue();
989989 break;
990990 }
991991 } else {
992992 return false;
993993 }
994
994
995995 // Verify that the Target mask and Insert mask together form a full word mask
996996 // and that the Insert mask is a run of set bits (which implies both are runs
997997 // of set bits). Given that, Select the arguments and generate the rlwimi
10011001 unsigned Tmp1, Tmp2;
10021002 // Check for rotlwi / rotrwi here, a special case of bitfield insert
10031003 // where both bitfield halves are sourced from the same value.
1004 if (IsRotate &&
1004 if (IsRotate &&
10051005 OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
10061006 Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
10071007 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
10381038 unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
10391039 unsigned Result, Tmp1, Tmp2;
10401040 bool AlreadySelected = false;
1041 static const unsigned CompareOpcodes[] =
1041 static const unsigned CompareOpcodes[] =
10421042 { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
1043
1043
10441044 // Allocate a condition register for this expression
10451045 Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
1046
1046
10471047 // If the first operand to the select is a SETCC node, then we can fold it
10481048 // into the branch that selects which value to return.
10491049 if (SetCCSDNode* SetCC = dyn_cast(CC.Val)) {
10531053
10541054 // Pass the optional argument U to getImmediateForOpcode for SETCC,
10551055 // so that it knows whether the SETCC immediate range is signed or not.
1056 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
1056 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
10571057 Tmp2, U)) {
1058 // For comparisons against zero, we can implicity set CR0 if a recording
1058