llvm.org GIT mirror llvm / b58f498
Add register-reuse to frame-index register scavenging. When a target uses a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 10 years ago
31 changed file(s) with 263 addition(s) and 101 deletion(s). Raw diff Collapse all Expand all
116116 return scavengeRegister(RegClass, MBBI, SPAdj);
117117 }
118118
119 /// setUsed - Tell the scavenger a register is used.
120 ///
121 void setUsed(unsigned Reg);
119122 private:
120123 /// isReserved - Returns true if a register is reserved. It is never "unused".
121124 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
130133
131134 /// setUsed / setUnused - Mark the state of one or a number of registers.
132135 ///
133 void setUsed(unsigned Reg);
134136 void setUsed(BitVector &Regs) {
135137 RegsAvailable &= ~Regs;
136138 }
659659 /// specified instruction, as long as it keeps the iterator pointing the the
660660 /// finished product. SPAdj is the SP adjustment due to call frame setup
661661 /// instruction.
662 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
663 int SPAdj, RegScavenger *RS=NULL) const = 0;
662 ///
663 /// When -enable-frame-index-scavenging is enabled, the virtual register
664 /// allocated for this frame index is returned and its value is stored in
665 /// *Value.
666 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
667 int SPAdj, int *Value = NULL,
668 RegScavenger *RS=NULL) const = 0;
664669
665670 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
666671 /// the function.
654654 int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
655655 int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
656656
657 // Pre-allocate space for frame index mappings. If more space is needed,
658 // the map will be grown later.
659 if (FrameIndexVirtualScavenging)
660 FrameConstantRegMap.grow(Fn.getRegInfo().getLastVirtReg() + 128);
661
657662 for (MachineFunction::iterator BB = Fn.begin(),
658663 E = Fn.end(); BB != E; ++BB) {
659664 int SPAdj = 0; // SP offset due to call frame setup / destroy.
702707 // If this instruction has a FrameIndex operand, we need to
703708 // use that target machine register info object to eliminate
704709 // it.
705
706 TRI.eliminateFrameIndex(MI, SPAdj, FrameIndexVirtualScavenging ?
707 NULL : RS);
710 int Value;
711 unsigned VReg =
712 TRI.eliminateFrameIndex(MI, SPAdj, &Value,
713 FrameIndexVirtualScavenging ? NULL : RS);
714 if (VReg) {
715 assert (FrameIndexVirtualScavenging &&
716 "Not scavenging, but virtual returned from "
717 "eliminateFrameIndex()!");
718 FrameConstantRegMap.grow(VReg);
719 FrameConstantRegMap[VReg] = FrameConstantEntry(Value, SPAdj);
720 }
708721
709722 // Reset the iterator if we were at the beginning of the BB.
710723 if (AtBeginning) {
724737
725738 assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
726739 }
740 }
741
742 /// findLastUseReg - find the killing use of the specified register within
743 /// the instruciton range. Return the operand number of the kill in Operand.
744 static MachineBasicBlock::iterator
745 findLastUseReg(MachineBasicBlock::iterator I, MachineBasicBlock::iterator ME,
746 unsigned Reg, unsigned *Operand) {
747 // Scan forward to find the last use of this virtual register
748 for (++I; I != ME; ++I) {
749 MachineInstr *MI = I;
750 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
751 if (MI->getOperand(i).isReg()) {
752 unsigned OpReg = MI->getOperand(i).getReg();
753 if (OpReg == 0 || !TargetRegisterInfo::isVirtualRegister(OpReg))
754 continue;
755 assert (OpReg == Reg
756 && "overlapping use of scavenged index register!");
757 // If this is the killing use, we're done
758 if (MI->getOperand(i).isKill()) {
759 if (Operand)
760 *Operand = i;
761 return I;
762 }
763 }
764 }
765 // If we hit the end of the basic block, there was no kill of
766 // the virtual register, which is wrong.
767 assert (0 && "scavenged index register never killed!");
768 return ME;
727769 }
728770
729771 /// scavengeFrameVirtualRegs - Replace all frame index virtual registers
737779
738780 unsigned CurrentVirtReg = 0;
739781 unsigned CurrentScratchReg = 0;
740
782 unsigned PrevScratchReg = 0;
783 int PrevValue;
784 MachineInstr *PrevLastUseMI;
785 unsigned PrevLastUseOp;
786
787 // The instruction stream may change in the loop, so check BB->end()
788 // directly.
741789 for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
742790 MachineInstr *MI = I;
743 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
791 // Likewise, call getNumOperands() each iteration, as the MI may change
792 // inside the loop (with 'i' updated accordingly).
793 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
744794 if (MI->getOperand(i).isReg()) {
745 unsigned Reg = MI->getOperand(i).getReg();
795 MachineOperand &MO = MI->getOperand(i);
796 unsigned Reg = MO.getReg();
746797 if (Reg == 0)
747798 continue;
748799 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
750801 // seeing any references to it.
751802 assert (Reg != CurrentScratchReg
752803 && "overlapping use of scavenged frame index register!");
804
805 // If we have a previous scratch reg, check and see if anything
806 // here kills whatever value is in there.
807 if (Reg == PrevScratchReg) {
808 if (MO.isUse()) {
809 // Two-address operands implicitly kill
810 if (MO.isKill() || MI->isRegTiedToDefOperand(i))
811 PrevScratchReg = 0;
812 } else {
813 assert (MO.isDef());
814 PrevScratchReg = 0;
815 }
816 }
753817 continue;
754818 }
755819
756820 // If we already have a scratch for this virtual register, use it
757821 if (Reg != CurrentVirtReg) {
758 // When we first encounter a new virtual register, it
759 // must be a definition.
760 assert(MI->getOperand(i).isDef() &&
761 "frame index virtual missing def!");
762 // We can't have nested virtual register live ranges because
763 // there's only a guarantee of one scavenged register at a time.
764 assert (CurrentVirtReg == 0 &&
765 "overlapping frame index virtual registers!");
766 CurrentVirtReg = Reg;
767 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
768 CurrentScratchReg = RS->FindUnusedReg(RC);
769 if (CurrentScratchReg == 0)
770 // No register is "free". Scavenge a register.
771 // FIXME: Track SPAdj. Zero won't always be right
772 CurrentScratchReg = RS->scavengeRegister(RC, I, 0);
822 int Value = FrameConstantRegMap[Reg].first;
823 int SPAdj = FrameConstantRegMap[Reg].second;
824
825 // If the scratch register from the last allocation is still
826 // available, see if the value matches. If it does, just re-use it.
827 if (PrevScratchReg && Value == PrevValue) {
828 // FIXME: This assumes that the instructions in the live range
829 // for the virtual register are exclusively for the purpose
830 // of populating the value in the register. That reasonable
831 // for these frame index registers, but it's still a very, very
832 // strong assumption. Perhaps this implies that the frame index
833 // elimination should be before register allocation, with
834 // conservative heuristics since we'll know less then, and
835 // the reuse calculations done directly when doing the code-gen?
836
837 // Find the last use of the new virtual register. Remove all
838 // instruction between here and there, and update the current
839 // instruction to reference the last use insn instead.
840 MachineBasicBlock::iterator LastUseMI =
841 findLastUseReg(I, BB->end(), Reg, &i);
842 // Remove all instructions up 'til the last use, since they're
843 // just calculating the value we already have.
844 BB->erase(I, LastUseMI);
845 MI = I = LastUseMI;
846
847 CurrentScratchReg = PrevScratchReg;
848 // Extend the live range of the register
849 PrevLastUseMI->getOperand(PrevLastUseOp).setIsKill(false);
850 RS->setUsed(CurrentScratchReg);
851 } else {
852 // When we first encounter a new virtual register, it
853 // must be a definition.
854 assert(MI->getOperand(i).isDef() &&
855 "frame index virtual missing def!");
856 // We can't have nested virtual register live ranges because
857 // there's only a guarantee of one scavenged register at a time.
858 assert (CurrentVirtReg == 0 &&
859 "overlapping frame index virtual registers!");
860 CurrentVirtReg = Reg;
861 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
862 CurrentScratchReg = RS->FindUnusedReg(RC);
863 if (CurrentScratchReg == 0)
864 // No register is "free". Scavenge a register.
865 CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
866
867 PrevValue = Value;
868 }
773869 }
774870 assert (CurrentScratchReg && "Missing scratch register!");
775871 MI->getOperand(i).setReg(CurrentScratchReg);
776872
777873 // If this is the last use of the register, stop tracking it.
778 if (MI->getOperand(i).isKill())
874 if (MI->getOperand(i).isKill()) {
875 PrevScratchReg = CurrentScratchReg;
876 PrevLastUseMI = MI;
779877 CurrentScratchReg = CurrentVirtReg = 0;
878 }
780879 }
781880 RS->forward(MI);
782881 }
2626 #include "llvm/CodeGen/MachineLoopInfo.h"
2727 #include "llvm/ADT/SparseBitVector.h"
2828 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/IndexedMap.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
2931
3032 namespace llvm {
3133 class RegScavenger;
9193 // may choose to skip shrink wrapping for certain
9294 // functions.
9395 bool ShrinkWrapThisFunction;
96
97 // When using the scavenger post-pass to resolve frame reference
98 // materialization registers, maintain a map of the registers to
99 // the constant value and SP adjustment associated with it.
100 typedef std::pair FrameConstantEntry;
101 IndexedMap FrameConstantRegMap;
94102
95103 #ifndef NDEBUG
96104 // Machine function handle.
305305 "Cannot scavenge register without an emergency spill slot!");
306306 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
307307 MachineBasicBlock::iterator II = prior(I);
308 TRI->eliminateFrameIndex(II, SPAdj, this);
308 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
309309
310310 // Restore the scavenged register before its use (or first terminator).
311311 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
10221022 return Reg;
10231023 }
10241024
1025 void
1025 unsigned
10261026 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1027 int SPAdj, RegScavenger *RS) const {
1027 int SPAdj, int *Value,
1028 RegScavenger *RS) const {
10281029 unsigned i = 0;
10291030 MachineInstr &MI = *II;
10301031 MachineBasicBlock &MBB = *MI.getParent();
10661067 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
10671068 }
10681069 if (Done)
1069 return;
1070 return 0;
10701071
10711072 // If we get here, the immediate doesn't fit into the instruction. We folded
10721073 // as much as possible above, handle the rest, providing a register that is
11011102 }
11021103 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
11031104 }
1105 return 0;
11041106 }
11051107
11061108 /// Move iterator pass the next bunch of callee save load / store ops for
127127 MachineBasicBlock &MBB,
128128 MachineBasicBlock::iterator I) const;
129129
130 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
131 int SPAdj, RegScavenger *RS = NULL) const;
130 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
131 int SPAdj, int *Value = NULL,
132 RegScavenger *RS = NULL) const;
132133
133134 virtual void emitPrologue(MachineFunction &MF) const;
134135 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
426426 TII.copyRegToReg(MBB, I, Reg, ARM::R12, RC, ARM::GPRRegisterClass);
427427 }
428428
429 void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
430 int SPAdj, RegScavenger *RS) const{
429 unsigned
430 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
431 int SPAdj, int *Value,
432 RegScavenger *RS) const{
433 unsigned VReg = 0;
431434 unsigned i = 0;
432435 MachineInstr &MI = *II;
433436 MachineBasicBlock &MBB = *MI.getParent();
483486 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
484487 MI.getOperand(i).ChangeToRegister(FrameReg, false);
485488 MI.RemoveOperand(i+1);
486 return;
489 return 0;
487490 }
488491
489492 // Common case: small offset, fits into instruction.
499502 MI.getOperand(i).ChangeToRegister(FrameReg, false);
500503 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
501504 }
502 return;
505 return 0;
503506 }
504507
505508 unsigned DestReg = MI.getOperand(0).getReg();
511514 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
512515 *this, dl);
513516 MBB.erase(II);
514 return;
517 return 0;
515518 }
516519
517520 if (Offset > 0) {
544547 AddDefaultPred(MIB);
545548 }
546549 }
547 return;
550 return 0;
548551 } else {
549552 unsigned ImmIdx = 0;
550553 int InstrOffs = 0;
574577 // Replace the FrameIndex with sp
575578 MI.getOperand(i).ChangeToRegister(FrameReg, false);
576579 ImmOp.ChangeToImmediate(ImmedOffset);
577 return;
580 return 0;
578581 }
579582
580583 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
632635 MI.addOperand(MachineOperand::CreateReg(0, false));
633636 } else if (Desc.mayStore()) {
634637 if (FrameIndexVirtualScavenging) {
635 unsigned TmpReg =
636 MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
638 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
639 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
640 *Value = Offset;
637641 bool UseRR = false;
642
638643 if (Opcode == ARM::tSpill) {
639644 if (FrameReg == ARM::SP)
640 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
645 emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
641646 Offset, false, TII, *this, dl);
642647 else {
643 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
648 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
644649 UseRR = true;
645650 }
646651 } else
647 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
652 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
648653 *this, dl);
649654 MI.setDesc(TII.get(ARM::tSTR));
650 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
655 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
651656 if (UseRR) // Use [reg, reg] addrmode.
652657 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
653658 else // tSTR has an extra register operand.
706711 MachineInstrBuilder MIB(&MI);
707712 AddDefaultPred(MIB);
708713 }
714 return VReg;
709715 }
710716
711717 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
6161 MachineBasicBlock::iterator I,
6262 const TargetRegisterClass *RC,
6363 unsigned Reg) const;
64 void eliminateFrameIndex(MachineBasicBlock::iterator II,
65 int SPAdj, RegScavenger *RS = NULL) const;
64 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
65 int SPAdj, int *Value = NULL,
66 RegScavenger *RS = NULL) const;
6667
6768 void emitPrologue(MachineFunction &MF) const;
6869 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
150150 //variable locals
151151 //<- SP
152152
153 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
154 int SPAdj, RegScavenger *RS) const {
153 unsigned
154 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
155 int SPAdj, int *Value,
156 RegScavenger *RS) const {
155157 assert(SPAdj == 0 && "Unexpected");
156158
157159 unsigned i = 0;
196198 } else {
197199 MI.getOperand(i).ChangeToImmediate(Offset);
198200 }
201 return 0;
199202 }
200203
201204
4040 MachineBasicBlock &MBB,
4141 MachineBasicBlock::iterator I) const;
4242
43 void eliminateFrameIndex(MachineBasicBlock::iterator II,
44 int SPAdj, RegScavenger *RS = NULL) const;
43 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
44 int SPAdj, int *Value = NULL,
45 RegScavenger *RS = NULL) const;
4546
4647 //void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4748
218218 return Reg;
219219 }
220220
221 void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
222 int SPAdj,
223 RegScavenger *RS) const {
221 unsigned
222 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
223 int SPAdj, int *Value,
224 RegScavenger *RS) const {
224225 MachineInstr &MI = *II;
225226 MachineBasicBlock &MBB = *MI.getParent();
226227 MachineFunction &MF = *MBB.getParent();
257258 MI.setDesc(TII.get(isStore
258259 ? BF::STORE32p_uimm6m4
259260 : BF::LOAD32p_uimm6m4));
260 return;
261 return 0;
261262 }
262263 if (BaseReg == BF::FP && isUint<7>(-Offset)) {
263264 MI.setDesc(TII.get(isStore
264265 ? BF::STORE32fp_nimm7m4
265266 : BF::LOAD32fp_nimm7m4));
266267 MI.getOperand(FIPos+1).setImm(-Offset);
267 return;
268 return 0;
268269 }
269270 if (isInt<18>(Offset)) {
270271 MI.setDesc(TII.get(isStore
271272 ? BF::STORE32p_imm18m4
272273 : BF::LOAD32p_imm18m4));
273 return;
274 return 0;
274275 }
275276 // Use RegScavenger to calculate proper offset...
276277 MI.dump();
355356 llvm_unreachable("Cannot eliminate frame index");
356357 break;
357358 }
359 return 0;
358360 }
359361
360362 void BlackfinRegisterInfo::
6363 MachineBasicBlock &MBB,
6464 MachineBasicBlock::iterator I) const;
6565
66 void eliminateFrameIndex(MachineBasicBlock::iterator II,
67 int SPAdj, RegScavenger *RS = NULL) const;
66 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
67 int SPAdj, int *Value = NULL,
68 RegScavenger *RS = NULL) const;
6869
6970 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
7071 RegScavenger *RS) const;
325325 MBB.erase(I);
326326 }
327327
328 void
328 unsigned
329329 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
330 RegScavenger *RS) const
330 int *Value, RegScavenger *RS) const
331331 {
332332 unsigned i = 0;
333333 MachineInstr &MI = *II;
370370 } else {
371371 MO.ChangeToImmediate(Offset);
372372 }
373 return 0;
373374 }
374375
375376 /// determineFrameLayout - Determine the size of the frame and maximum call
6262 MachineBasicBlock &MBB,
6363 MachineBasicBlock::iterator I) const;
6464 //! Convert frame indicies into machine operands
65 void eliminateFrameIndex(MachineBasicBlock::iterator II, int,
66 RegScavenger *RS) const;
65 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
66 int *Value = NULL,
67 RegScavenger *RS = NULL) const;
6768 //! Determine the frame's layour
6869 void determineFrameLayout(MachineFunction &MF) const;
6970
146146 MBB.erase(I);
147147 }
148148
149 void
149 unsigned
150150 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
151 int SPAdj, RegScavenger *RS) const {
151 int SPAdj, int *Value,
152 RegScavenger *RS) const {
152153 assert(SPAdj == 0 && "Unexpected");
153154
154155 unsigned i = 0;
186187 MI.getOperand(i).ChangeToRegister(BasePtr, false);
187188
188189 if (Offset == 0)
189 return;
190 return 0;
190191
191192 // We need to materialize the offset via add instruction.
192193 unsigned DstReg = MI.getOperand(0).getReg();
197198 BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
198199 .addReg(DstReg).addImm(Offset);
199200
200 return;
201 return 0;
201202 }
202203
203204 MI.getOperand(i).ChangeToRegister(BasePtr, false);
204205 MI.getOperand(i+1).ChangeToImmediate(Offset);
206 return 0;
205207 }
206208
207209 void
4848 MachineBasicBlock &MBB,
4949 MachineBasicBlock::iterator I) const;
5050
51 void eliminateFrameIndex(MachineBasicBlock::iterator II,
52 int SPAdj, RegScavenger *RS = NULL) const;
51 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
52 int SPAdj, int *Value = NULL,
53 RegScavenger *RS = NULL) const;
5354
5455 void emitPrologue(MachineFunction &MF) const;
5556 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
347347 // FrameIndex represent objects inside a abstract stack.
348348 // We must replace FrameIndex with an stack/frame pointer
349349 // direct reference.
350 void MipsRegisterInfo::
351 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
352 RegScavenger *RS) const
350 unsigned MipsRegisterInfo::
351 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
352 int *Value, RegScavenger *RS) const
353353 {
354354 MachineInstr &MI = *II;
355355 MachineFunction &MF = *MI.getParent()->getParent();
381381
382382 MI.getOperand(i-1).ChangeToImmediate(Offset);
383383 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
384 return 0;
384385 }
385386
386387 void MipsRegisterInfo::
5353 MachineBasicBlock::iterator I) const;
5454
5555 /// Stack Frame Processing Methods
56 void eliminateFrameIndex(MachineBasicBlock::iterator II,
57 int SPAdj, RegScavenger *RS = NULL) const;
56 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
57 int SPAdj, int *Value = NULL,
58 RegScavenger *RS = NULL) const;
5859
5960 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
6061
5050 return false;
5151 }
5252
53 void PIC16RegisterInfo::
53 unsigned PIC16RegisterInfo::
5454 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
55 RegScavenger *RS) const
56 { /* NOT YET IMPLEMENTED */ }
55 int *Value, RegScavenger *RS) const
56 {
57 /* NOT YET IMPLEMENTED */
58 return 0;
59 }
5760
5861 void PIC16RegisterInfo::emitPrologue(MachineFunction &MF) const
5962 { /* NOT YET IMPLEMENTED */ }
4747 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
4848 virtual bool hasFP(const MachineFunction &MF) const;
4949
50 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
51 int SPAdj, RegScavenger *RS=NULL) const;
50 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
51 int SPAdj, int *Value = NULL,
52 RegScavenger *RS=NULL) const;
5253
5354 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5455 MachineBasicBlock &MBB,
698698 MBB.erase(II);
699699 }
700700
701 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
702 int SPAdj, RegScavenger *RS) const {
701 unsigned
702 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
703 int SPAdj, int *Value,
704 RegScavenger *RS) const {
703705 assert(SPAdj == 0 && "Unexpected");
704706
705707 // Get the instruction.
738740 if (FPSI && FrameIndex == FPSI &&
739741 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
740742 lowerDynamicAlloc(II, SPAdj, RS);
741 return;
743 return 0;
742744 }
743745
744746 // Special case for pseudo-op SPILL_CR.
745747 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
746748 if (OpC == PPC::SPILL_CR) {
747749 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
748 return;
750 return 0;
749751 }
750752
751753 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
787789 if (isIXAddr)
788790 Offset >>= 2; // The actual encoded value has the low two bits zero.
789791 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
790 return;
792 return 0;
791793 }
792794
793795 // The offset doesn't fit into a single register, scavenge one to build the
827829 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
828830 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
829831 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
832 return 0;
830833 }
831834
832835 /// VRRegNo - Map from a numbered VR register to its enum value.
6565 int SPAdj, RegScavenger *RS) const;
6666 void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex,
6767 int SPAdj, RegScavenger *RS) const;
68 void eliminateFrameIndex(MachineBasicBlock::iterator II,
69 int SPAdj, RegScavenger *RS = NULL) const;
68 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
69 int SPAdj, int *Value = NULL,
70 RegScavenger *RS = NULL) const;
7071
7172 /// determineFrameLayout - Determine the size of the frame and maximum call
7273 /// frame size.
7575 MBB.erase(I);
7676 }
7777
78 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
79 int SPAdj, RegScavenger *RS) const {
78 unsigned
79 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
80 int SPAdj, int *Value,
81 RegScavenger *RS) const {
8082 assert(SPAdj == 0 && "Unexpected");
8183
8284 unsigned i = 0;
112114 MI.getOperand(i).ChangeToRegister(SP::G1, false);
113115 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
114116 }
117 return 0;
115118 }
116119
117120 void SparcRegisterInfo::
4242 MachineBasicBlock &MBB,
4343 MachineBasicBlock::iterator I) const;
4444
45 void eliminateFrameIndex(MachineBasicBlock::iterator II,
46 int SPAdj, RegScavenger *RS = NULL) const;
45 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
46 int SPAdj, int *Value = NULL,
47 RegScavenger *RS = NULL) const;
4748
4849 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4950
106106 return Offset;
107107 }
108108
109 void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
110 int SPAdj, RegScavenger *RS) const {
109 unsigned
110 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
111 int SPAdj, int *Value,
112 RegScavenger *RS) const {
111113 assert(SPAdj == 0 && "Unxpected");
112114
113115 unsigned i = 0;
135137 MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
136138
137139 MI.getOperand(i+1).ChangeToImmediate(Offset);
140 return 0;
138141 }
139142
140143 void
5454 MachineBasicBlock &MBB,
5555 MachineBasicBlock::iterator I) const;
5656
57 void eliminateFrameIndex(MachineBasicBlock::iterator II,
58 int SPAdj, RegScavenger *RS = NULL) const;
57 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
58 int SPAdj, int *Value = NULL,
59 RegScavenger *RS = NULL) const;
5960
6061
6162 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
578578 MBB.erase(I);
579579 }
580580
581 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
582 int SPAdj, RegScavenger *RS) const{
581 unsigned
582 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
583 int SPAdj, int *Value,
584 RegScavenger *RS) const{
583585 assert(SPAdj == 0 && "Unexpected");
584586
585587 unsigned i = 0;
616618 (uint64_t)MI.getOperand(i+3).getOffset();
617619 MI.getOperand(i+3).setOffset(Offset);
618620 }
621 return 0;
619622 }
620623
621624 void
138138 MachineBasicBlock &MBB,
139139 MachineBasicBlock::iterator MI) const;
140140
141 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
142 int SPAdj, RegScavenger *RS = NULL) const;
141 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
142 int SPAdj, int *Value = NULL,
143 RegScavenger *RS = NULL) const;
143144
144145 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
145146 RegScavenger *RS = NULL) const;
170170 MBB.erase(I);
171171 }
172172
173 void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
174 int SPAdj, RegScavenger *RS) const {
173 unsigned
174 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
175 int SPAdj, int *Value,
176 RegScavenger *RS) const {
175177 assert(SPAdj == 0 && "Unexpected");
176178 MachineInstr &MI = *II;
177179 DebugLoc dl = MI.getDebugLoc();
310312 }
311313 // Erase old instruction.
312314 MBB.erase(II);
315 return 0;
313316 }
314317
315318 void
5656 MachineBasicBlock &MBB,
5757 MachineBasicBlock::iterator I) const;
5858
59 void eliminateFrameIndex(MachineBasicBlock::iterator II,
60 int SPAdj, RegScavenger *RS = NULL) const;
59 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
60 int SPAdj, int *Value = NULL,
61 RegScavenger *RS = NULL) const;
6162
6263 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
6364 RegScavenger *RS = NULL) const;