llvm.org GIT mirror llvm / b58d7d0
Add stack spill / reload instructions for DTriple and DQuad register classes, which were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 7 years ago
2 changed file(s) with 217 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
794794 } else
795795 llvm_unreachable("Unknown reg class!");
796796 break;
797 case 24:
798 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
799 // Use aligned spills if the stack can be realigned.
800 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
801 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
802 .addFrameIndex(FI).addImm(16)
803 .addReg(SrcReg, getKillRegState(isKill))
804 .addMemOperand(MMO));
805 } else {
806 MachineInstrBuilder MIB =
807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
808 .addFrameIndex(FI))
809 .addMemOperand(MMO);
810 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
812 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
813 }
814 } else
815 llvm_unreachable("Unknown reg class!");
816 break;
797817 case 32:
798 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
818 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
799819 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
800820 // FIXME: It's possible to only store part of the QQ register if the
801821 // spilled def has a sub-register index.
941961 } else
942962 llvm_unreachable("Unknown reg class!");
943963 break;
944 case 32:
945 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
964 case 24:
965 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
966 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
967 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
968 .addFrameIndex(FI).addImm(16)
969 .addMemOperand(MMO));
970 } else {
971 MachineInstrBuilder MIB =
972 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
973 .addFrameIndex(FI)
974 .addMemOperand(MMO));
975 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
976 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
977 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
978 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
979 MIB.addReg(DestReg, RegState::ImplicitDefine);
980 }
981 } else
982 llvm_unreachable("Unknown reg class!");
983 break;
984 case 32:
985 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
946986 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
947987 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
948988 .addFrameIndex(FI).addImm(16)
0 ; RUN: llc < %s
1 ; PR13377
2
3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
4 target triple = "armv7-none-linux-gnueabi"
5
6 %0 = type { <4 x float> }
7
8 define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable {
9 br i1 undef, label %4, label %5
10
11 ;
12 unreachable
13
14 ;
15 br i1 undef, label %7, label %6
16
17 ;
18 unreachable
19
20 ;
21 br i1 undef, label %8, label %10
22
23 ;
24 br i1 undef, label %9, label %10
25
26 ;
27 br i1 undef, label %11, label %10
28
29 ;
30 unreachable
31
32 ;
33 br i1 undef, label %13, label %12
34
35 ;
36 unreachable
37
38 ;
39 br i1 undef, label %15, label %14
40
41 ;
42 unreachable
43
44 ;
45 br i1 undef, label %18, label %16
46
47 ;
48 br i1 undef, label %17, label %18
49
50 ;
51 unreachable
52
53 ;
54 br i1 undef, label %68, label %19
55
56 ;
57 br label %20
58
59 ;
60 br i1 undef, label %21, label %20
61
62 ;
63 br i1 undef, label %22, label %68
64
65 ;
66 br i1 undef, label %23, label %24
67
68 ;
69 unreachable
70
71 ;
72 br i1 undef, label %26, label %25
73
74 ;
75 unreachable
76
77 ;
78 br i1 undef, label %28, label %27
79
80 ;
81 unreachable
82
83 ;
84 br i1 undef, label %29, label %30, !prof !0
85
86 ;
87 br label %30
88
89 ;
90 br i1 undef, label %31, label %32, !prof !0
91
92 ;
93 br label %32
94
95 ;
96 br i1 undef, label %34, label %33
97
98 ;
99 unreachable
100
101 ;
102 br i1 undef, label %35, label %36, !prof !0
103
104 ;
105 br label %36
106
107 ;
108 br i1 undef, label %37, label %38, !prof !0
109
110 ;
111 br label %38
112
113 ;
114 br i1 undef, label %39, label %67
115
116 ;
117 br i1 undef, label %40, label %41
118
119 ;
120 br i1 undef, label %64, label %41
121
122 ;
123 br i1 undef, label %64, label %42
124
125 ;
126 %43 = fadd <4 x float> undef, undef
127 %44 = fadd <4 x float> undef, undef
128 %45 = fmul <4 x float> undef, undef
129 %46 = fmul <4 x float> %45, %43
130 %47 = fmul <4 x float> undef, %44
131 %48 = load <4 x float>* undef, align 8, !tbaa !1
132 %49 = bitcast <4 x float> %48 to <2 x i64>
133 %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32>
134 %51 = bitcast <1 x i64> %50 to <2 x float>
135 %52 = shufflevector <2 x float> %51, <2 x float> undef, <4 x i32> zeroinitializer
136 %53 = bitcast <4 x float> %52 to <2 x i64>
137 %54 = shufflevector <2 x i64> %53, <2 x i64> undef, <1 x i32> zeroinitializer
138 %55 = bitcast <1 x i64> %54 to <2 x float>
139 %56 = extractelement <2 x float> %55, i32 0
140 %57 = insertelement <4 x float> undef, float %56, i32 2
141 %58 = insertelement <4 x float> %57, float 1.000000e+00, i32 3
142 %59 = fsub <4 x float> %47, %58
143 %60 = fmul <4 x float> undef, undef
144 %61 = fmul <4 x float> %59, %60
145 %62 = fmul <4 x float> %61,
146 %63 = fadd <4 x float> %47, %62
147 store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1
148 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
149 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
150 store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1
151 unreachable
152
153 ;
154 br i1 undef, label %65, label %66
155
156 ;
157 unreachable
158
159 ;
160 unreachable
161
162 ;
163 unreachable
164
165 ;
166 ret void
167 }
168
169 declare arm_aapcs_vfpcc void @bar(%0*, float)
170
171 !0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
172 !1 = metadata !{metadata !"omnipotent char", metadata !2}
173 !2 = metadata !{metadata !"Simple C/C++ TBAA"}