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[ARM] Reverse PostRASched subtarget feature logic Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312226 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Parker 2 years ago
4 changed file(s) with 17 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
322322 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
323323 "Use the MachineScheduler">;
324324
325 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
326 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
325 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
326 "DisablePostRAScheduler", "true",
327 "Don't schedule again after register allocation">;
327328
328329 //===----------------------------------------------------------------------===//
329330 // ARM architecture class
828829 FeatureSlowLoadDSubreg,
829830 FeatureSlowVGETLNi32,
830831 FeatureSlowVDUP32,
831 FeatureUseMISched]>;
832 FeatureUseMISched,
833 FeatureNoPostRASched]>;
832834
833835 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
834836 FeatureHasRetAddrStack,
875877
876878 def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m,
877879 ProcM3,
878 FeatureHasNoBranchPredictor,
879 FeaturePostRAScheduler]>;
880 FeatureHasNoBranchPredictor]>;
880881
881882 def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m,
882883 ProcM3,
886887 FeatureVFP4,
887888 FeatureVFPOnlySP,
888889 FeatureD16,
889 FeatureHasNoBranchPredictor,
890 FeaturePostRAScheduler]>;
890 FeatureHasNoBranchPredictor]>;
891891
892892 def : ProcNoItin<"cortex-m7", [ARMv7em,
893893 FeatureFPARMv8,
894 FeatureD16,
895 FeaturePostRAScheduler]>;
894 FeatureD16]>;
896895
897896 def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
898897 FeatureNoMovt]>;
902901 FeatureFPARMv8,
903902 FeatureD16,
904903 FeatureVFPOnlySP,
905 FeatureHasNoBranchPredictor,
906 FeaturePostRAScheduler]>;
904 FeatureHasNoBranchPredictor]>;
907905
908906 def : ProcNoItin<"cortex-a32", [ARMv8a,
909907 FeatureHWDivThumb,
967965 FeatureHasSlowFPVMLx,
968966 FeatureCrypto,
969967 FeatureUseMISched,
970 FeatureZCZeroing]>;
968 FeatureZCZeroing,
969 FeatureNoPostRASched]>;
971970
972971 def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
973972 FeatureHWDivThumb,
2323 let IssueWidth = 2; // 2 micro-ops dispatched per cycle
2424 let LoadLatency = 1; // Optimistic, assuming no misses
2525 let MispredictPenalty = 8; // A branch direction mispredict, including PFU
26 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
2726 let CompleteModel = 0; // Covers instructions applicable to cortex-r52.
2827 }
2928
365365
366366 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
367367 bool ARMSubtarget::enablePostRAScheduler() const {
368 if (usePostRAScheduler())
369 return true;
370 if (SchedModel.PostRAScheduler)
371 return true;
372 // No need for PostRA scheduling on subtargets where we use the
373 // MachineScheduler.
374 if (useMachineScheduler())
368 if (disablePostRAScheduler())
375369 return false;
376 return (!isThumb() || hasThumb2());
370 // Don't reschedule potential IT blocks.
371 return !isThumb1Only();
377372 }
378373
379374 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
193193 /// UseMISched - True if MachineScheduler should be used for this subtarget.
194194 bool UseMISched = false;
195195
196 /// UsePostRAScheduler - True if scheduling should happen again after
196 /// DisablePostRAScheduler - False if scheduling should happen again after
197197 /// register allocation.
198 bool UsePostRAScheduler = false;
198 bool DisablePostRAScheduler = false;
199199
200200 /// HasThumb2 - True if Thumb2 instructions are supported.
201201 bool HasThumb2 = false;
666666 bool isRWPI() const;
667667
668668 bool useMachineScheduler() const { return UseMISched; }
669 bool usePostRAScheduler() const { return UsePostRAScheduler; }
669 bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
670670 bool useSoftFloat() const { return UseSoftFloat; }
671671 bool isThumb() const { return InThumbMode; }
672672 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }