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Merging r236307: ------------------------------------------------------------------------ r236307 | thomas.stellard | 2015-04-30 23:44:09 -0400 (Thu, 30 Apr 2015) | 4 lines R600/SI: Add VCC as an implict def of SI_KILL When SI_KILL has a register operand, its lowered form writes to vcc. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236452 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
2 changed file(s) with 22 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
18221822 // SI pseudo instructions. These are used by the CFG structurizer pass
18231823 // and should be lowered to ISA instructions prior to codegen.
18241824
1825 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1826 Uses = [EXEC], Defs = [EXEC] in {
1825 let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
1826 let Uses = [EXEC], Defs = [EXEC] in {
18271827
18281828 let isBranch = 1, isTerminator = 1 in {
18291829
18801880 [(int_SI_end_cf i64:$saved)]
18811881 >;
18821882
1883 } // End Uses = [EXEC], Defs = [EXEC]
1884
1885 let Uses = [EXEC], Defs = [EXEC,VCC] in {
18831886 def SI_KILL : InstSI <
18841887 (outs),
18851888 (ins VSrc_32:$src),
18861889 "si_kill $src",
18871890 [(int_AMDGPU_kill f32:$src)]
18881891 >;
1892 } // End Uses = [EXEC], Defs = [EXEC,VCC]
18891893
18901894 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1891 // Uses = [EXEC], Defs = [EXEC]
18921895
18931896 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
18941897
1515 ret void
1616 }
1717
18 ; SI-LABEL: {{^}}kill_vcc_implicit_def:
19 ; SI-NOT: v_cmp_gt_f32_e32 vcc,
20 ; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
21 ; SI: v_cmp_lt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0
22 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
23 define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
24 entry:
25 %tmp0 = fcmp olt float %13, 0.0
26 call void @llvm.AMDGPU.kill(float %14)
27 %tmp1 = select i1 %tmp0, float 1.0, float 0.0
28 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
29 ret void
30 }
31
1832 declare void @llvm.AMDGPU.kill(float)
33 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
1934
2035 attributes #0 = { "ShaderType"="2" }
36 attributes #1 = { "ShaderType"="0" }
2137
2238 !0 = !{!"const", null, i32 1}