llvm.org GIT mirror llvm / b4f68ed
Convert backend to use passes, implement X86TargetMachine git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4421 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 17 years ago
7 changed file(s) with 173 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
99 #include "llvm/iTerminators.h"
1010 #include "llvm/Type.h"
1111 #include "llvm/Constants.h"
12 #include "llvm/Pass.h"
1213 #include "llvm/CodeGen/MachineFunction.h"
1314 #include "llvm/CodeGen/MachineInstrBuilder.h"
1415 #include "llvm/Support/InstVisitor.h"
1516 #include
1617
1718 namespace {
18 struct ISel : public InstVisitor { // eventually will be a FunctionPass
19 struct ISel : public FunctionPass, InstVisitor {
20 TargetMachine &TM;
1921 MachineFunction *F; // The function we are compiling into
2022 MachineBasicBlock *BB; // The current MBB we are compiling
2123
2224 unsigned CurReg;
2325 std::map RegMap; // Mapping between Val's and SSA Regs
2426
25 ISel(MachineFunction *f)
26 : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
27 ISel(TargetMachine &tm)
28 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
2729
2830 /// runOnFunction - Top level implementation of instruction selection for
2931 /// the entire function.
3032 ///
31 bool runOnFunction(Function &F) {
32 visit(F);
33 bool runOnFunction(Function &Fn) {
34 F = new MachineFunction(&Fn, TM);
35 visit(Fn);
3336 RegMap.clear();
37 F = 0;
3438 return false; // We never modify the LLVM itself.
3539 }
3640
160164 }
161165 }
162166
163
164
165 /// X86SimpleInstructionSelection - This function converts an LLVM function into
166 /// a machine code representation is a very simple peep-hole fashion. The
167 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
168 /// into a machine code representation is a very simple peep-hole fashion. The
167169 /// generated code sucks but the implementation is nice and simple.
168170 ///
169 MachineFunction *X86SimpleInstructionSelection(Function &F, TargetMachine &TM) {
170 MachineFunction *Result = new MachineFunction(&F, TM);
171 ISel(Result).runOnFunction(F);
172 return Result;
171 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
172 return new ISel(TM);
173173 }
55 //===----------------------------------------------------------------------===//
66
77 #include "X86.h"
8 #include "llvm/Pass.h"
9 #include "llvm/CodeGen/MachineFunction.h"
810 #include
911
10 /// X86PrintCode - Print out the specified machine code function to the
11 /// specified stream. This function should work regardless of whether or not
12 /// the function is in SSA form or not, although when in SSA form, we obviously
13 /// don't care about being consumable by an assembler.
12 namespace {
13 struct Printer : public FunctionPass {
14 TargetMachine &TM;
15 std::ostream &O;
16
17 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
18
19 bool runOnFunction(Function &F);
20 };
21 }
22
23 bool Printer::runOnFunction(Function &F) {
24 MachineFunction &MF = MachineFunction::get(&F);
25 O << "x86 printing not implemented yet!\n";
26
27 // This should use the X86InstructionInfo::print method to print assembly
28 // for each instruction
29 return false;
30 }
31
32
33
34
35 /// createX86CodePrinterPass - Print out the specified machine code function to
36 /// the specified stream. This function should work regardless of whether or
37 /// not the function is in SSA form or not.
1438 ///
15 void X86PrintCode(const MachineFunction *MF, std::ostream &O) {
16 O << "x86 printing not implemented yet!\n";
17
18 // This should use the X86InstructionInfo::print method to print assembly for
19 // each instruction
39 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
40 return new Printer(TM, O);
2041 }
1010 #define TARGET_X86_H
1111
1212 #include
13 class MachineFunction;
14 class Function;
1513 class TargetMachine;
14 class Pass;
1615
17 /// X86PrintCode - Print out the specified machine code function to the
18 /// specified stream. This function should work regardless of whether or not
19 /// the function is in SSA form or not.
20 ///
21 void X86PrintCode(const MachineFunction *MF, std::ostream &O);
22
23 /// X86SimpleInstructionSelection - This function converts an LLVM function into
24 /// a machine code representation is a very simple peep-hole fashion. The
16 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
17 /// into a machine code representation is a very simple peep-hole fashion. The
2518 /// generated code sucks but the implementation is nice and simple.
2619 ///
27 MachineFunction *X86SimpleInstructionSelection(Function &F, TargetMachine &TM);
20 Pass *createSimpleX86InstructionSelector(TargetMachine &TM);
2821
2922 /// X86SimpleRegisterAllocation - This function converts the specified machine
3023 /// code function from SSA form to use explicit registers by spilling every
3124 /// register. Wow, great policy huh?
3225 ///
33 inline void X86SimpleRegisterAllocation(MachineFunction *MF) {}
26 Pass *createSimpleX86RegisterAllocator(TargetMachine &TM);
27
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
31 ///
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O);
3433
3534 /// X86EmitCodeToMemory - This function converts a register allocated function
3635 /// into raw machine code in a dynamically allocated chunk of memory. A pointer
3736 /// to the start of the function is returned.
3837 ///
39 inline void *X86EmitCodeToMemory(MachineFunction *MF) { return 0; }
40
38 Pass *createEmitX86CodeToMemory(TargetMachine &TM);
4139
4240 // Put symbolic names in a namespace to avoid causing these to clash with all
4341 // kinds of other things...
55 //===----------------------------------------------------------------------===//
66
77 #include "X86.h"
8 #include "llvm/Pass.h"
9 #include "llvm/CodeGen/MachineFunction.h"
810 #include
911
10 /// X86PrintCode - Print out the specified machine code function to the
11 /// specified stream. This function should work regardless of whether or not
12 /// the function is in SSA form or not, although when in SSA form, we obviously
13 /// don't care about being consumable by an assembler.
12 namespace {
13 struct Printer : public FunctionPass {
14 TargetMachine &TM;
15 std::ostream &O;
16
17 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
18
19 bool runOnFunction(Function &F);
20 };
21 }
22
23 bool Printer::runOnFunction(Function &F) {
24 MachineFunction &MF = MachineFunction::get(&F);
25 O << "x86 printing not implemented yet!\n";
26
27 // This should use the X86InstructionInfo::print method to print assembly
28 // for each instruction
29 return false;
30 }
31
32
33
34
35 /// createX86CodePrinterPass - Print out the specified machine code function to
36 /// the specified stream. This function should work regardless of whether or
37 /// not the function is in SSA form or not.
1438 ///
15 void X86PrintCode(const MachineFunction *MF, std::ostream &O) {
16 O << "x86 printing not implemented yet!\n";
17
18 // This should use the X86InstructionInfo::print method to print assembly for
19 // each instruction
39 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
40 return new Printer(TM, O);
2041 }
99 #include "llvm/iTerminators.h"
1010 #include "llvm/Type.h"
1111 #include "llvm/Constants.h"
12 #include "llvm/Pass.h"
1213 #include "llvm/CodeGen/MachineFunction.h"
1314 #include "llvm/CodeGen/MachineInstrBuilder.h"
1415 #include "llvm/Support/InstVisitor.h"
1516 #include
1617
1718 namespace {
18 struct ISel : public InstVisitor { // eventually will be a FunctionPass
19 struct ISel : public FunctionPass, InstVisitor {
20 TargetMachine &TM;
1921 MachineFunction *F; // The function we are compiling into
2022 MachineBasicBlock *BB; // The current MBB we are compiling
2123
2224 unsigned CurReg;
2325 std::map RegMap; // Mapping between Val's and SSA Regs
2426
25 ISel(MachineFunction *f)
26 : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
27 ISel(TargetMachine &tm)
28 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
2729
2830 /// runOnFunction - Top level implementation of instruction selection for
2931 /// the entire function.
3032 ///
31 bool runOnFunction(Function &F) {
32 visit(F);
33 bool runOnFunction(Function &Fn) {
34 F = new MachineFunction(&Fn, TM);
35 visit(Fn);
3336 RegMap.clear();
37 F = 0;
3438 return false; // We never modify the LLVM itself.
3539 }
3640
160164 }
161165 }
162166
163
164
165 /// X86SimpleInstructionSelection - This function converts an LLVM function into
166 /// a machine code representation is a very simple peep-hole fashion. The
167 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
168 /// into a machine code representation is a very simple peep-hole fashion. The
167169 /// generated code sucks but the implementation is nice and simple.
168170 ///
169 MachineFunction *X86SimpleInstructionSelection(Function &F, TargetMachine &TM) {
170 MachineFunction *Result = new MachineFunction(&F, TM);
171 ISel(Result).runOnFunction(F);
172 return Result;
171 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
172 return new ISel(TM);
173173 }
0 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
1 //
2 // This file defines the X86 specific subclass of TargetMachine.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #include "X86TargetMachine.h"
7 #include "llvm/Target/TargetMachineImpls.h"
8 #include "llvm/PassManager.h"
9 #include "X86.h"
10 #include
11
12 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
13 // that implements the X86 backend.
14 //
15 TargetMachine *allocateX86TargetMachine() { return new X86TargetMachine(); }
16
17
18 /// X86TargetMachine ctor - Create an ILP32 architecture model
19 ///
20 X86TargetMachine::X86TargetMachine() : TargetMachine("X86", 1, 4, 4, 4) {
21 }
22
23
24 /// addPassesToJITCompile - Add passes to the specified pass manager to
25 /// implement a fast dynamic compiler for this target. Return true if this is
26 /// not supported for this target.
27 ///
28 bool X86TargetMachine::addPassesToJITCompile(PassManager &PM) {
29 PM.add(createSimpleX86InstructionSelector(*this));
30
31 // TODO: optional optimizations go here
32
33 // Perform register allocation to convert to a concrete x86 representation
34 //PM.add(createSimpleX86RegisterAllocator(*this));
35
36 PM.add(createX86CodePrinterPass(*this, std::cerr));
37
38 //PM.add(createEmitX86CodeToMemory(*this));
39
40 return false; // success!
41 }
42
0 //===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
1 //
2 // This file declares the X86 specific subclass of TargetMachine.
3 //
4 //===----------------------------------------------------------------------===//
5
6 #ifndef X86TARGETMACHINE_H
7 #define X86TARGETMACHINE_H
8
9 #include "llvm/Target/TargetMachine.h"
10 #include "X86InstrInfo.h"
11
12 class X86TargetMachine : public TargetMachine {
13 X86InstrInfo instrInfo;
14 public:
15 X86TargetMachine();
16
17 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
18 virtual const MachineSchedInfo &getSchedInfo() const { abort(); }
19 virtual const MachineRegInfo &getRegInfo() const { abort(); }
20 virtual const MachineFrameInfo &getFrameInfo() const { abort(); }
21 virtual const MachineCacheInfo &getCacheInfo() const { abort(); }
22 virtual const MachineOptInfo &getOptInfo() const { abort(); }
23
24 /// addPassesToJITCompile - Add passes to the specified pass manager to
25 /// implement a fast dynamic compiler for this target. Return true if this is
26 /// not supported for this target.
27 ///
28 virtual bool addPassesToJITCompile(PassManager &PM);
29 };
30
31 #endif