llvm.org GIT mirror llvm / b4dded6
[ARM GlobalISel] Select extensions to < 32 bits Select G_SEXT and G_ZEXT with destination types smaller than 32 bits in the exact same way as 32 bits. This overwrites the higher bits, but that should be ok since all legal users of types smaller than 32 bits ignore those bits anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359768 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 8 months ago
3 changed file(s) with 648 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
861861 LLVM_FALLTHROUGH;
862862 case G_ZEXT: {
863863 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
864 // FIXME: Smaller destination sizes coming soon!
865 if (DstTy.getSizeInBits() != 32) {
866 LLVM_DEBUG(dbgs() << "Unsupported destination size for extension");
867 return false;
868 }
864 assert(DstTy.getSizeInBits() <= 32 &&
865 "Unsupported destination size for extension");
869866
870867 LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
871868 unsigned SrcSize = SrcTy.getSizeInBits();
66 define void @test_trunc_and_anyext_s8_to_s32() { ret void }
77 define void @test_trunc_and_anyext_s16_to_s32() { ret void }
88
9 define void @test_trunc_and_zext_s1_to_s16() { ret void }
10 define void @test_trunc_and_sext_s1_to_s16() { ret void }
11 define void @test_trunc_and_anyext_s1_to_s16() { ret void }
12
13 define void @test_trunc_and_zext_s8_to_s16() { ret void }
14 define void @test_trunc_and_sext_s8_to_s16() { ret void }
15 define void @test_trunc_and_anyext_s8_to_s16() { ret void }
16
17 define void @test_trunc_and_zext_s1_to_s8() { ret void }
18 define void @test_trunc_and_sext_s1_to_s8() { ret void }
19 define void @test_trunc_and_anyext_s1_to_s8() { ret void }
20
921 define void @test_add_s32() { ret void }
1022 define void @test_add_fold_imm_s32() { ret void }
1123 define void @test_add_no_fold_imm_s32() #2 { ret void }
226238
227239 BX_RET 14, $noreg, implicit $r0
228240 ; CHECK: BX_RET 14, $noreg, implicit $r0
241 ...
242 ---
243 name: test_trunc_and_zext_s1_to_s16
244 # CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
245 legalized: true
246 regBankSelected: true
247 selected: false
248 # CHECK: selected: true
249 tracksRegLiveness: true
250 registers:
251 - { id: 0, class: gprb }
252 - { id: 1, class: gprb }
253 - { id: 2, class: gprb }
254 - { id: 3, class: gprb }
255 body: |
256 bb.0:
257 liveins: $r0, $r1
258
259 %0(p0) = COPY $r0
260 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
261
262 %1(s32) = COPY $r1
263 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
264
265 %2(s1) = G_TRUNC %1(s32)
266
267 %3(s16) = G_ZEXT %2(s1)
268 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
269
270 G_STORE %3(s16), %0(p0) :: (store 2)
271 ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
272
273 BX_RET 14, $noreg
274 ; CHECK: BX_RET 14, $noreg
275 ...
276 ---
277 name: test_trunc_and_sext_s1_to_s16
278 # CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
279 legalized: true
280 regBankSelected: true
281 selected: false
282 # CHECK: selected: true
283 tracksRegLiveness: true
284 registers:
285 - { id: 0, class: gprb }
286 - { id: 1, class: gprb }
287 - { id: 2, class: gprb }
288 - { id: 3, class: gprb }
289 body: |
290 bb.0:
291 liveins: $r0, $r1
292
293 %0(p0) = COPY $r0
294 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
295
296 %1(s32) = COPY $r1
297 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
298
299 %2(s1) = G_TRUNC %1(s32)
300
301 %3(s16) = G_SEXT %2(s1)
302 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
303 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
304
305 G_STORE %3(s16), %0(p0) :: (store 2)
306 ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
307
308 BX_RET 14, $noreg
309 ; CHECK: BX_RET 14, $noreg
310 ...
311 ---
312 name: test_trunc_and_anyext_s1_to_s16
313 # CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
314 legalized: true
315 regBankSelected: true
316 selected: false
317 # CHECK: selected: true
318 tracksRegLiveness: true
319 registers:
320 - { id: 0, class: gprb }
321 - { id: 1, class: gprb }
322 - { id: 2, class: gprb }
323 - { id: 3, class: gprb }
324 body: |
325 bb.0:
326 liveins: $r0, $r1
327
328 %0(p0) = COPY $r0
329 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
330
331 %1(s32) = COPY $r1
332 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
333
334 %2(s1) = G_TRUNC %1(s32)
335
336 %3(s16) = G_ANYEXT %2(s1)
337
338 G_STORE %3(s16), %0(p0) :: (store 2)
339 ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
340
341 BX_RET 14, $noreg
342 ; CHECK: BX_RET 14, $noreg
343 ...
344 ---
345 name: test_trunc_and_zext_s8_to_s16
346 # CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
347 legalized: true
348 regBankSelected: true
349 selected: false
350 # CHECK: selected: true
351 tracksRegLiveness: true
352 registers:
353 - { id: 0, class: gprb }
354 - { id: 1, class: gprb }
355 - { id: 2, class: gprb }
356 - { id: 3, class: gprb }
357 body: |
358 bb.0:
359 liveins: $r0, $r1
360
361 %0(p0) = COPY $r0
362 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
363
364 %1(s32) = COPY $r1
365 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
366
367 %2(s8) = G_TRUNC %1(s32)
368 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
369
370 %3(s16) = G_ZEXT %2(s8)
371 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTB [[VREGTRUNC]], 0, 14, $noreg
372
373 G_STORE %3(s16), %0(p0) :: (store 2)
374 ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
375
376 BX_RET 14, $noreg
377 ; CHECK: BX_RET 14, $noreg
378 ...
379 ---
380 name: test_trunc_and_sext_s8_to_s16
381 # CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
382 legalized: true
383 regBankSelected: true
384 selected: false
385 # CHECK: selected: true
386 tracksRegLiveness: true
387 registers:
388 - { id: 0, class: gprb }
389 - { id: 1, class: gprb }
390 - { id: 2, class: gprb }
391 - { id: 3, class: gprb }
392 body: |
393 bb.0:
394 liveins: $r0, $r1
395
396 %0(p0) = COPY $r0
397 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
398
399 %1(s32) = COPY $r1
400 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
401
402 %2(s8) = G_TRUNC %1(s32)
403 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
404
405 %3(s16) = G_SEXT %2(s8)
406 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
407
408 G_STORE %3(s16), %0(p0) :: (store 2)
409 ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
410
411 BX_RET 14, $noreg
412 ; CHECK: BX_RET 14, $noreg
413 ...
414 ---
415 name: test_trunc_and_anyext_s8_to_s16
416 # CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
417 legalized: true
418 regBankSelected: true
419 selected: false
420 # CHECK: selected: true
421 tracksRegLiveness: true
422 registers:
423 - { id: 0, class: gprb }
424 - { id: 1, class: gprb }
425 - { id: 2, class: gprb }
426 - { id: 3, class: gprb }
427 body: |
428 bb.0:
429 liveins: $r0, $r1
430
431 %0(p0) = COPY $r0
432 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
433
434 %1(s32) = COPY $r1
435 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
436
437 %2(s8) = G_TRUNC %1(s32)
438
439 %3(s16) = G_ANYEXT %2(s8)
440
441 G_STORE %3(s16), %0(p0) :: (store 2)
442 ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2)
443
444 BX_RET 14, $noreg
445 ; CHECK: BX_RET 14, $noreg
446 ...
447 ---
448 name: test_trunc_and_zext_s1_to_s8
449 # CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
450 legalized: true
451 regBankSelected: true
452 selected: false
453 # CHECK: selected: true
454 tracksRegLiveness: true
455 registers:
456 - { id: 0, class: gprb }
457 - { id: 1, class: gprb }
458 - { id: 2, class: gprb }
459 - { id: 3, class: gprb }
460 body: |
461 bb.0:
462 liveins: $r0, $r1
463
464 %0(p0) = COPY $r0
465 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
466
467 %1(s32) = COPY $r1
468 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
469
470 %2(s1) = G_TRUNC %1(s32)
471
472 %3(s8) = G_ZEXT %2(s1)
473 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = ANDri [[VREG]], 1, 14, $noreg, $noreg
474
475 G_STORE %3(s8), %0(p0) :: (store 1)
476 ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
477
478 BX_RET 14, $noreg
479 ; CHECK: BX_RET 14, $noreg
480 ...
481 ---
482 name: test_trunc_and_sext_s1_to_s8
483 # CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
484 legalized: true
485 regBankSelected: true
486 selected: false
487 # CHECK: selected: true
488 tracksRegLiveness: true
489 registers:
490 - { id: 0, class: gprb }
491 - { id: 1, class: gprb }
492 - { id: 2, class: gprb }
493 - { id: 3, class: gprb }
494 body: |
495 bb.0:
496 liveins: $r0, $r1
497
498 %0(p0) = COPY $r0
499 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
500
501 %1(s32) = COPY $r1
502 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
503
504 %2(s1) = G_TRUNC %1(s32)
505
506 %3(s8) = G_SEXT %2(s1)
507 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
508 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
509
510 G_STORE %3(s8), %0(p0) :: (store 1)
511 ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
512
513 BX_RET 14, $noreg
514 ; CHECK: BX_RET 14, $noreg
515 ...
516 ---
517 name: test_trunc_and_anyext_s1_to_s8
518 # CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
519 legalized: true
520 regBankSelected: true
521 selected: false
522 # CHECK: selected: true
523 tracksRegLiveness: true
524 registers:
525 - { id: 0, class: gprb }
526 - { id: 1, class: gprb }
527 - { id: 2, class: gprb }
528 - { id: 3, class: gprb }
529 body: |
530 bb.0:
531 liveins: $r0, $r1
532
533 %0(p0) = COPY $r0
534 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
535
536 %1(s32) = COPY $r1
537 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
538
539 %2(s1) = G_TRUNC %1(s32)
540
541 %3(s8) = G_ANYEXT %2(s1)
542
543 G_STORE %3(s8), %0(p0) :: (store 1)
544 ; CHECK: [[RVREG:%[0-9]+]]:gprnopc = COPY [[VREG]]
545 ; CHECK: STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
546
547 BX_RET 14, $noreg
548 ; CHECK: BX_RET 14, $noreg
229549 ...
230550 ---
231551 name: test_add_s32
1010 define void @test_trunc_and_zext_s16_to_s32() { ret void }
1111 define void @test_trunc_and_sext_s16_to_s32() { ret void }
1212 define void @test_trunc_and_anyext_s16_to_s32() { ret void }
13
14 define void @test_trunc_and_zext_s1_to_s16() { ret void }
15 define void @test_trunc_and_sext_s1_to_s16() { ret void }
16 define void @test_trunc_and_anyext_s1_to_s16() { ret void }
17
18 define void @test_trunc_and_zext_s8_to_s16() { ret void }
19 define void @test_trunc_and_sext_s8_to_s16() { ret void }
20 define void @test_trunc_and_anyext_s8_to_s16() { ret void }
21
22 define void @test_trunc_and_zext_s1_to_s8() { ret void }
23 define void @test_trunc_and_sext_s1_to_s8() { ret void }
24 define void @test_trunc_and_anyext_s1_to_s8() { ret void }
1325 ...
1426 ---
1527 name: test_trunc_and_zext_s1_to_s32
285297 BX_RET 14, $noreg, implicit $r0
286298 ; CHECK: BX_RET 14, $noreg, implicit $r0
287299 ...
300 ---
301 name: test_trunc_and_zext_s1_to_s16
302 # CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
303 legalized: true
304 regBankSelected: true
305 selected: false
306 # CHECK: selected: true
307 tracksRegLiveness: true
308 registers:
309 - { id: 0, class: gprb }
310 - { id: 1, class: gprb }
311 - { id: 2, class: gprb }
312 - { id: 3, class: gprb }
313 body: |
314 bb.0:
315 liveins: $r0, $r1
316
317 %0(p0) = COPY $r0
318 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
319
320 %1(s32) = COPY $r1
321 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
322
323 %2(s1) = G_TRUNC %1(s32)
324
325 %3(s16) = G_ZEXT %2(s1)
326 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
327 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
328
329 G_STORE %3(s16), %0(p0) :: (store 2)
330 ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
331
332 BX_RET 14, $noreg
333 ; CHECK: BX_RET 14, $noreg
334 ...
335 ---
336 name: test_trunc_and_sext_s1_to_s16
337 # CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
338 legalized: true
339 regBankSelected: true
340 selected: false
341 # CHECK: selected: true
342 tracksRegLiveness: true
343 registers:
344 - { id: 0, class: gprb }
345 - { id: 1, class: gprb }
346 - { id: 2, class: gprb }
347 - { id: 3, class: gprb }
348 body: |
349 bb.0:
350 liveins: $r0, $r1
351
352 %0(p0) = COPY $r0
353 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
354
355 %1(s32) = COPY $r1
356 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
357
358 %2(s1) = G_TRUNC %1(s32)
359
360 %3(s16) = G_SEXT %2(s1)
361 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
362 ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
363 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
364
365 G_STORE %3(s16), %0(p0) :: (store 2)
366 ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
367
368 BX_RET 14, $noreg
369 ; CHECK: BX_RET 14, $noreg
370 ...
371 ---
372 name: test_trunc_and_anyext_s1_to_s16
373 # CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
374 legalized: true
375 regBankSelected: true
376 selected: false
377 # CHECK: selected: true
378 tracksRegLiveness: true
379 registers:
380 - { id: 0, class: gprb }
381 - { id: 1, class: gprb }
382 - { id: 2, class: gprb }
383 - { id: 3, class: gprb }
384 body: |
385 bb.0:
386 liveins: $r0, $r1
387
388 %0(p0) = COPY $r0
389 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
390
391 %1(s32) = COPY $r1
392 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
393
394 %2(s1) = G_TRUNC %1(s32)
395
396 %3(s16) = G_ANYEXT %2(s1)
397
398 G_STORE %3(s16), %0(p0) :: (store 2)
399 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
400 ; CHECK: t2STRHi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 2)
401
402 BX_RET 14, $noreg
403 ; CHECK: BX_RET 14, $noreg
404 ...
405 ---
406 name: test_trunc_and_zext_s8_to_s16
407 # CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
408 legalized: true
409 regBankSelected: true
410 selected: false
411 # CHECK: selected: true
412 tracksRegLiveness: true
413 registers:
414 - { id: 0, class: gprb }
415 - { id: 1, class: gprb }
416 - { id: 2, class: gprb }
417 - { id: 3, class: gprb }
418 body: |
419 bb.0:
420 liveins: $r0, $r1
421
422 %0(p0) = COPY $r0
423 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
424
425 %1(s32) = COPY $r1
426 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
427
428 %2(s8) = G_TRUNC %1(s32)
429 ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
430
431 %3(s16) = G_ZEXT %2(s8)
432 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg
433
434 G_STORE %3(s16), %0(p0) :: (store 2)
435 ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
436
437 BX_RET 14, $noreg
438 ; CHECK: BX_RET 14, $noreg
439 ...
440 ---
441 name: test_trunc_and_sext_s8_to_s16
442 # CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
443 legalized: true
444 regBankSelected: true
445 selected: false
446 # CHECK: selected: true
447 tracksRegLiveness: true
448 registers:
449 - { id: 0, class: gprb }
450 - { id: 1, class: gprb }
451 - { id: 2, class: gprb }
452 - { id: 3, class: gprb }
453 body: |
454 bb.0:
455 liveins: $r0, $r1
456
457 %0(p0) = COPY $r0
458 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
459
460 %1(s32) = COPY $r1
461 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
462
463 %2(s8) = G_TRUNC %1(s32)
464 ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]]
465
466 %3(s16) = G_SEXT %2(s8)
467 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg
468
469 G_STORE %3(s16), %0(p0) :: (store 2)
470 ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2)
471
472 BX_RET 14, $noreg
473 ; CHECK: BX_RET 14, $noreg
474 ...
475 ---
476 name: test_trunc_and_anyext_s8_to_s16
477 # CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
478 legalized: true
479 regBankSelected: true
480 selected: false
481 # CHECK: selected: true
482 tracksRegLiveness: true
483 registers:
484 - { id: 0, class: gprb }
485 - { id: 1, class: gprb }
486 - { id: 2, class: gprb }
487 - { id: 3, class: gprb }
488 body: |
489 bb.0:
490 liveins: $r0, $r1
491
492 %0(p0) = COPY $r0
493 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
494
495 %1(s32) = COPY $r1
496 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
497
498 %2(s8) = G_TRUNC %1(s32)
499
500 %3(s16) = G_ANYEXT %2(s8)
501
502 G_STORE %3(s16), %0(p0) :: (store 2)
503 ; CHECK: [[VREGR:%[0-9]+]]:rgpr = COPY [[VREG]]
504 ; CHECK: t2STRHi12 [[VREGR]], [[PTR]], 0, 14, $noreg :: (store 2)
505
506 BX_RET 14, $noreg
507 ; CHECK: BX_RET 14, $noreg
508 ...
509 ---
510 name: test_trunc_and_zext_s1_to_s8
511 # CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
512 legalized: true
513 regBankSelected: true
514 selected: false
515 # CHECK: selected: true
516 tracksRegLiveness: true
517 registers:
518 - { id: 0, class: gprb }
519 - { id: 1, class: gprb }
520 - { id: 2, class: gprb }
521 - { id: 3, class: gprb }
522 body: |
523 bb.0:
524 liveins: $r0, $r1
525
526 %0(p0) = COPY $r0
527 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
528
529 %1(s32) = COPY $r1
530 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
531
532 %2(s1) = G_TRUNC %1(s32)
533
534 %3(s8) = G_ZEXT %2(s1)
535 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
536 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
537
538 G_STORE %3(s8), %0(p0) :: (store 1)
539 ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
540
541 BX_RET 14, $noreg
542 ; CHECK: BX_RET 14, $noreg
543 ...
544 ---
545 name: test_trunc_and_sext_s1_to_s8
546 # CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
547 legalized: true
548 regBankSelected: true
549 selected: false
550 # CHECK: selected: true
551 tracksRegLiveness: true
552 registers:
553 - { id: 0, class: gprb }
554 - { id: 1, class: gprb }
555 - { id: 2, class: gprb }
556 - { id: 3, class: gprb }
557 body: |
558 bb.0:
559 liveins: $r0, $r1
560
561 %0(p0) = COPY $r0
562 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
563
564 %1(s32) = COPY $r1
565 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
566
567 %2(s1) = G_TRUNC %1(s32)
568
569 %3(s8) = G_SEXT %2(s1)
570 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
571 ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg
572 ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg
573
574 G_STORE %3(s8), %0(p0) :: (store 1)
575 ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1)
576
577 BX_RET 14, $noreg
578 ; CHECK: BX_RET 14, $noreg
579 ...
580 ---
581 name: test_trunc_and_anyext_s1_to_s8
582 # CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
583 legalized: true
584 regBankSelected: true
585 selected: false
586 # CHECK: selected: true
587 tracksRegLiveness: true
588 registers:
589 - { id: 0, class: gprb }
590 - { id: 1, class: gprb }
591 - { id: 2, class: gprb }
592 - { id: 3, class: gprb }
593 body: |
594 bb.0:
595 liveins: $r0, $r1
596
597 %0(p0) = COPY $r0
598 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
599
600 %1(s32) = COPY $r1
601 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1
602
603 %2(s1) = G_TRUNC %1(s32)
604
605 %3(s8) = G_ANYEXT %2(s1)
606
607 G_STORE %3(s8), %0(p0) :: (store 1)
608 ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]]
609 ; CHECK: t2STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1)
610
611 BX_RET 14, $noreg
612 ; CHECK: BX_RET 14, $noreg
613 ...