llvm.org GIT mirror llvm / b4bf68e
[X86] Remove the HLE feature flag. We only implemented it for one of the 3 HLE instructions and that instruction is also under the RTM flag. Clang only implements the RTM flag from its command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294562 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
6 changed file(s) with 5 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
13651365 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
13661366 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
13671367 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1368 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
13691368 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
13701369 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
13711370 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
186186 "Support BMI2 instructions">;
187187 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
188188 "Support RTM instructions">;
189 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
190 "Support HLE">;
191189 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
192190 "Support ADX instructions">;
193191 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
492490 FeatureLZCNT,
493491 FeatureMOVBE,
494492 FeatureRTM,
495 FeatureHLE,
496493 FeatureSlowIncDec
497494 ]>;
498495
849849 def HasIFMA : Predicate<"Subtarget->hasIFMA()">,
850850 AssemblerPredicate<"FeatureIFMA", "AVX-512 IFMA ISA">;
851851 def HasRTM : Predicate<"Subtarget->hasRTM()">;
852 def HasHLE : Predicate<"Subtarget->hasHLE()">;
853 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
854852 def HasADX : Predicate<"Subtarget->hasADX()">;
855853 def HasSHA : Predicate<"Subtarget->hasSHA()">;
856854 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
2424
2525 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
2626 def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst),
27 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>;
27 "xbegin\t$dst", []>, OpSize16;
2828 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst),
29 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
29 "xbegin\t$dst", []>, OpSize32;
3030 }
3131
3232 def XEND : I<0x01, MRM_D5, (outs), (ins),
3434
3535 let Defs = [EFLAGS] in
3636 def XTEST : I<0x01, MRM_D6, (outs), (ins),
37 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
37 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>;
3838
3939 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
4040 "xabort\t$imm",
4343 // HLE prefixes
4444
4545 let isAsmParserOnly = 1 in {
46 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
47 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;
46 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>;
47 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>;
4848 }
4949
274274 HasVBMI = false;
275275 HasIFMA = false;
276276 HasRTM = false;
277 HasHLE = false;
278277 HasERI = false;
279278 HasCDI = false;
280279 HasPFI = false;
152152
153153 /// Processor has RTM instructions.
154154 bool HasRTM;
155
156 /// Processor has HLE.
157 bool HasHLE;
158155
159156 /// Processor has ADX instructions.
160157 bool HasADX;
449446 bool hasVBMI() const { return HasVBMI; }
450447 bool hasIFMA() const { return HasIFMA; }
451448 bool hasRTM() const { return HasRTM; }
452 bool hasHLE() const { return HasHLE; }
453449 bool hasADX() const { return HasADX; }
454450 bool hasSHA() const { return HasSHA; }
455451 bool hasPRFCHW() const { return HasPRFCHW; }