llvm.org GIT mirror llvm / b461d37
Make code layout more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9418 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 16 years ago
1 changed file(s) with 54 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
15401540 // Let's check for chain rules outside the switch so that we don't have
15411541 // to duplicate the list of chain rule production numbers here again
15421542 //
1543 if (ThisIsAChainRule(ruleForNode))
1544 {
1545 // Chain rules have a single nonterminal on the RHS.
1546 // Get the rule that matches the RHS non-terminal and use that instead.
1547 //
1548 assert(nts[0] && ! nts[1]
1549 && "A chain rule should have only one RHS non-terminal!");
1550 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1551 nts = burm_nts[nextRule];
1552 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1553 }
1554 else
1555 {
1556 switch(ruleForNode) {
1557 case 1: // stmt: Ret
1558 case 2: // stmt: RetValue(reg)
1543 if (ThisIsAChainRule(ruleForNode)) {
1544 // Chain rules have a single nonterminal on the RHS.
1545 // Get the rule that matches the RHS non-terminal and use that instead.
1546 //
1547 assert(nts[0] && ! nts[1]
1548 && "A chain rule should have only one RHS non-terminal!");
1549 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1550 nts = burm_nts[nextRule];
1551 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1552 } else {
1553 switch(ruleForNode) {
1554 case 1: // stmt: Ret
1555 case 2: // stmt: RetValue(reg)
15591556 { // NOTE: Prepass of register allocation is responsible
15601557 // for moving return value to appropriate register.
15611558 // Copy the return value to the required return register.
21912188 mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
21922189 .addReg(dest, MOTy::Def));
21932190
2194 if (notArg->getType() == Type::BoolTy)
2195 { // set 1 in result register if result of above is non-zero
2196 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2197 .addReg(dest, MOTy::UseAndDef));
2198 }
2191 if (notArg->getType() == Type::BoolTy) {
2192 // set 1 in result register if result of above is non-zero
2193 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2194 .addReg(dest, MOTy::UseAndDef));
2195 }
21992196
22002197 break;
22012198 }
22222219 mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
22232220 .addReg(dest, MOTy::Def));
22242221
2225 if (notArg->getType() == Type::BoolTy)
2226 { // set 1 in result register if result of above is non-zero
2227 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2228 .addReg(dest, MOTy::UseAndDef));
2229 }
2222 if (notArg->getType() == Type::BoolTy) {
2223 // set 1 in result register if result of above is non-zero
2224 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2225 .addReg(dest, MOTy::UseAndDef));
2226 }
22302227
22312228 break;
22322229 }
22522249 mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
22532250 .addReg(dest, MOTy::Def));
22542251
2255 if (notArg->getType() == Type::BoolTy)
2256 { // set 1 in result register if result of above is non-zero
2257 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2258 .addReg(dest, MOTy::UseAndDef));
2259 }
2252 if (notArg->getType() == Type::BoolTy) {
2253 // set 1 in result register if result of above is non-zero
2254 mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
2255 .addReg(dest, MOTy::UseAndDef));
2256 }
22602257 break;
22612258 }
22622259
22772274 bool computeBoolVal = (subtreeRoot->parent() == NULL ||
22782275 ! AllUsesAreBranches(setCCInstr));
22792276
2280 if (computeBoolVal)
2277 if (computeBoolVal) {
2278 InstrTreeNode* constNode = subtreeRoot->rightChild();
2279 assert(constNode &&
2280 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
2281 Constant *constVal = cast(constNode->getValue());
2282 bool isValidConst;
2283
2284 if ((constVal->getType()->isInteger()
2285 || isa(constVal->getType()))
2286 && target.getInstrInfo().ConvertConstantToIntType(target,
2287 constVal, constVal->getType(), isValidConst) == 0
2288 && isValidConst)
22812289 {
2282 InstrTreeNode* constNode = subtreeRoot->rightChild();
2283 assert(constNode &&
2284 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
2285 Constant *constVal = cast(constNode->getValue());
2286 bool isValidConst;
2287
2288 if ((constVal->getType()->isInteger()
2289 || isa(constVal->getType()))
2290 && target.getInstrInfo().ConvertConstantToIntType(target,
2291 constVal, constVal->getType(), isValidConst) == 0
2292 && isValidConst)
2293 {
2294 // That constant is an integer zero after all...
2295 // Use a MOVR[op] to compute the boolean result
2296 // Unconditionally set register to 0
2297 mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
2298 .addRegDef(setCCInstr));
2290 // That constant is an integer zero after all...
2291 // Use a MOVR[op] to compute the boolean result
2292 // Unconditionally set register to 0
2293 mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
2294 .addRegDef(setCCInstr));
22992295
2300 // Now conditionally move 1 into the register.
2301 // Mark the register as a use (as well as a def) because the old
2302 // value will be retained if the condition is false.
2303 MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
2304 mvec.push_back(BuildMI(movOpCode, 3)
2305 .addReg(subtreeRoot->leftChild()->getValue())
2306 .addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
2296 // Now conditionally move 1 into the register.
2297 // Mark the register as a use (as well as a def) because the old
2298 // value will be retained if the condition is false.
2299 MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
2300 mvec.push_back(BuildMI(movOpCode, 3)
2301 .addReg(subtreeRoot->leftChild()->getValue())
2302 .addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
23072303
2308 break;
2309 }
2304 break;
23102305 }
2306 }
23112307 // ELSE FALL THROUGH
23122308 }
23132309