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Merging r248858: ------------------------------------------------------------------------ r248858 | marek.olsak | 2015-09-29 19:37:32 -0400 (Tue, 29 Sep 2015) | 9 lines AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is set to prevent setting a huge stride, because DATA_FORMAT has a different meaning if ADD_TID_ENABLE is set. This is a candidate for stable llvm 3.7. Tested-and-Reviewed-by: Christian König <christian.koenig@amd.com> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@253236 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
4 changed file(s) with 19 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
22522252 SDValue Ptr) const {
22532253 const SIInstrInfo *TII =
22542254 static_cast(Subtarget->getInstrInfo());
2255 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
2256 0xffffffff; // Size
2257
2258 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2255
2256 return buildRSRC(DAG, DL, Ptr, 0, TII->getScratchRsrcWords23());
22592257 }
22602258
22612259 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
27772777
27782778 return RsrcDataFormat;
27792779 }
2780
2781 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
2782 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
2783 AMDGPU::RSRC_TID_ENABLE |
2784 0xffffffff; // Size;
2785
2786 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
2787 // Clear them unless we want a huge stride.
2788 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2789 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
2790
2791 return Rsrc23;
2792 }
352352 }
353353
354354 uint64_t getDefaultRsrcDataFormat() const;
355
355 uint64_t getScratchRsrcWords23() const;
356356 };
357357
358358 namespace AMDGPU {
134134 unsigned ScratchRsrcReg =
135135 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
136136
137 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
138 0xffffffff; // Size
137 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
139138
140139 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
141140 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
151150 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
152151
153152 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
154 .addImm(Rsrc & 0xffffffff)
153 .addImm(Rsrc23 & 0xffffffff)
155154 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
156155
157156 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
158 .addImm(Rsrc >> 32)
157 .addImm(Rsrc23 >> 32)
159158 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
160159
161160 // Scratch Offset