llvm.org GIT mirror llvm / b3f5bfe
Some of GR8_NOREX registers are only available in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
2 changed file(s) with 83 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
483483 // of registers which do not by themselves require a REX prefix.
484484 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
485485 [AL, CL, DL, SIL, DIL, BL, BPL, SPL]> {
486 let MethodProtos = [{
487 iterator allocation_order_begin(const MachineFunction &MF) const;
488 iterator allocation_order_end(const MachineFunction &MF) const;
489 }];
490 let MethodBodies = [{
491 // Does the function dedicate RBP / EBP to being a frame ptr?
492 // If so, don't allocate SPL or BPL.
493 static const unsigned X86_GR8_NOREX_AO_64_fp[] = {
494 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL
495 };
496 // If not, just don't allocate SPL.
497 static const unsigned X86_GR8_NOREX_AO_64[] = {
498 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
499 };
500 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
501 static const unsigned X86_GR8_NOREX_AO_32[] = {
502 X86::AL, X86::CL, X86::DL, X86::BL
503 };
504
505 GR8_NOREXClass::iterator
506 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
507 const TargetMachine &TM = MF.getTarget();
508 const TargetRegisterInfo *RI = TM.getRegisterInfo();
509 const X86Subtarget &Subtarget = TM.getSubtarget();
510 if (!Subtarget.is64Bit())
511 return X86_GR8_NOREX_AO_32;
512 else if (RI->hasFP(MF))
513 return X86_GR8_NOREX_AO_64_fp;
514 else
515 return X86_GR8_NOREX_AO_64;
516 }
517
518 GR8_NOREXClass::iterator
519 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
520 const TargetMachine &TM = MF.getTarget();
521 const TargetRegisterInfo *RI = TM.getRegisterInfo();
522 const X86Subtarget &Subtarget = TM.getSubtarget();
523 if (!Subtarget.is64Bit())
524 return X86_GR8_NOREX_AO_32 +
525 (sizeof(X86_GR8_NOREX_AO_32) / sizeof(unsigned));
526 else if (RI->hasFP(MF))
527 return X86_GR8_NOREX_AO_64_fp +
528 (sizeof(X86_GR8_NOREX_AO_64_fp) / sizeof(unsigned));
529 else
530 return X86_GR8_NOREX_AO_64 +
531 (sizeof(X86_GR8_NOREX_AO_64) / sizeof(unsigned));
532 }
533 }];
486534 }
487535 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
488536 [AX, CX, DX, SI, DI, BX, BP, SP]> {
0 ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
1 ; rdar://6787136
2
3 %struct.X = type { i8, [32 x i8] }
4 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @z to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
5
6 define i32 @z() nounwind ssp {
7 entry:
8 %retval = alloca i32 ; [#uses=2]
9 %xxx = alloca %struct.X ; <%struct.X*> [#uses=6]
10 %0 = alloca i32 ; [#uses=2]
11 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
12 %1 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
13 %2 = getelementptr [32 x i8]* %1, i32 0, i32 31 ; [#uses=1]
14 store i8 48, i8* %2, align 1
15 %3 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
16 %4 = getelementptr [32 x i8]* %3, i32 0, i32 31 ; [#uses=1]
17 %5 = load i8* %4, align 1 ; [#uses=1]
18 %6 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
19 %7 = getelementptr [32 x i8]* %6, i32 0, i32 0 ; [#uses=1]
20 store i8 %5, i8* %7, align 1
21 %8 = getelementptr %struct.X* %xxx, i32 0, i32 0 ; [#uses=1]
22 store i8 15, i8* %8, align 1
23 %9 = call i32 (...)* bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind ; [#uses=1]
24 store i32 %9, i32* %0, align 4
25 %10 = load i32* %0, align 4 ; [#uses=1]
26 store i32 %10, i32* %retval, align 4
27 br label %return
28
29 return: ; preds = %entry
30 %retval1 = load i32* %retval ; [#uses=1]
31 ret i32 %retval1
32 }
33
34 declare i32 @f(%struct.X* byval align 4, %struct.X* byval align 4) nounwind ssp