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R600/SI: add some more instruction flags Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176102 91177308-0d34-0410-b5e6-96231b3b80d8 Christian Konig 7 years ago
3 changed file(s) with 92 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
6363 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
6464 .addReg(SrcReg, getKillRegState(KillSrc));
6565 }
66 }
67
68 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
69 bool NewMI) const {
70
71 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg() ||
72 !MI->getOperand(2).isReg())
73 return 0;
74
75 return TargetInstrInfo::commuteInstruction(MI, NewMI);
6676 }
6777
6878 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
3333 MachineBasicBlock::iterator MI, DebugLoc DL,
3434 unsigned DestReg, unsigned SrcReg,
3535 bool KillSrc) const;
36
37 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
38 bool NewMI=false) const;
3639
3740 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
3841 int64_t Imm) const;
2727 let Predicates = [isSI] in {
2828
2929 let neverHasSideEffects = 1 in {
30
31 let isMoveImm = 1 in {
3032 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
3133 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
3234 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
3335 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
36 } // End isMoveImm = 1
37
3438 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
3539 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
3640 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
3842 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
3943 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
4044 } // End neverHasSideEffects = 1
45
4146 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
4247 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
4348 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
106111 >;
107112 */
108113
114 let isCompare = 1 in {
109115 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
110116 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
111117 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
117123 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
118124 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
119125 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
126 } // End isCompare = 1
127
120128 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
121129 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
122130 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
125133 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
126134 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
127135 //def EXP : EXP_ <0x00000000, "EXP", []>;
136
137 let isCompare = 1 in {
128138
129139 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
130140 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>;
143153 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
144154 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
145155
146 //Side effect is writing to EXEC
147 let hasSideEffects = 1 in {
156 let hasSideEffects = 1, Defs = [EXEC] in {
148157
149158 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
150159 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
163172 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
164173 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
165174
166 } // End hasSideEffects = 1
175 } // End hasSideEffects = 1, Defs = [EXEC]
167176
168177 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
169178 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64">;
182191 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
183192 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
184193
185 //Side effect is writing to EXEC
186 let hasSideEffects = 1 in {
194 let hasSideEffects = 1, Defs = [EXEC] in {
187195
188196 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
189197 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
202210 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
203211 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
204212
205 } // End hasSideEffects = 1
213 } // End hasSideEffects = 1, Defs = [EXEC]
206214
207215 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
208216 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
220228 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
221229 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
222230 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
231
232 let hasSideEffects = 1, Defs = [EXEC] in {
233
223234 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
224235 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
225236 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
236247 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
237248 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
238249 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
250
251 } // End hasSideEffects = 1, Defs = [EXEC]
252
239253 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
240254 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
241255 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
252266 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
253267 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
254268 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
269
270 let hasSideEffects = 1, Defs = [EXEC] in {
271
255272 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
256273 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
257274 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
268285 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
269286 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
270287 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
288
289 } // End hasSideEffects = 1, Defs = [EXEC]
290
271291 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
272292 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>;
273293 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
277297 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>;
278298 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
279299
280 let hasSideEffects = 1 in {
300 let hasSideEffects = 1, Defs = [EXEC] in {
281301
282302 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
283303 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
288308 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
289309 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
290310
291 } // End hasSideEffects
311 } // End hasSideEffects = 1, Defs = [EXEC]
292312
293313 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
294314 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">;
299319 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">;
300320 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
301321
302 let hasSideEffects = 1 in {
322 let hasSideEffects = 1, Defs = [EXEC] in {
303323
304324 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
305325 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
310330 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
311331 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
312332
313 } // End hasSideEffects
333 } // End hasSideEffects = 1, Defs = [EXEC]
314334
315335 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
316336 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">;
321341 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">;
322342 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
323343
324 let hasSideEffects = 1 in {
344 let hasSideEffects = 1, Defs = [EXEC] in {
325345
326346 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
327347 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
332352 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
333353 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
334354
335 } // End hasSideEffects
355 } // End hasSideEffects = 1, Defs = [EXEC]
336356
337357 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
338358 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">;
342362 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">;
343363 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">;
344364 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
365
366 let hasSideEffects = 1, Defs = [EXEC] in {
367
345368 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
346369 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
347370 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
350373 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
351374 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
352375 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
376
377 } // End hasSideEffects = 1, Defs = [EXEC]
378
353379 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
380
381 let hasSideEffects = 1, Defs = [EXEC] in {
354382 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
383 } // End hasSideEffects = 1, Defs = [EXEC]
384
355385 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
386
387 let hasSideEffects = 1, Defs = [EXEC] in {
356388 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
389 } // End hasSideEffects = 1, Defs = [EXEC]
390
391 } // End isCompare = 1
392
357393 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
358394 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
359395 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
534570 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
535571 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
536572
537 let neverHasSideEffects = 1 in {
573
574 let neverHasSideEffects = 1, isMoveImm = 1 in {
538575 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
539 } // End neverHasSideEffects
576 } // End neverHasSideEffects = 1, isMoveImm = 1
577
540578 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
541579 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
542580 //defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>;
747785 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
748786 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
749787
788 let isCommutable = 1 in {
750789 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
751790 [(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))]
752791 >;
792 } // End isCommutable = 1
793
753794 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
754795 [(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))]
755796 >;
756797
757798 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>;
758799 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
800
801 let isCommutable = 1 in {
802
759803 defm V_MUL_LEGACY_F32 : VOP2_32 <
760804 0x00000007, "V_MUL_LEGACY_F32",
761805 [(set VReg_32:$dst, (int_AMDGPU_mul VSrc_32:$src0, VReg_32:$src1))]
764808 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
765809 [(set VReg_32:$dst, (fmul VSrc_32:$src0, VReg_32:$src1))]
766810 >;
811
812 } // End isCommutable = 1
813
767814 //defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>;
768815 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
769816 //defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>;
770817 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
818
819 let isCommutable = 1 in {
820
771821 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
772822 [(set VReg_32:$dst, (AMDGPUfmin VSrc_32:$src0, VReg_32:$src1))]
773823 >;
775825 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
776826 [(set VReg_32:$dst, (AMDGPUfmax VSrc_32:$src0, VReg_32:$src1))]
777827 >;
828
778829 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
779830 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
780831 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>;
781832 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>;
782833 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>;
783834 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
835
836 } // End isCommutable = 1
837
784838 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>;
785839 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>;
786840 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>;
787841 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>;
788842 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>;
789843 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>;
844
845 let isCommutable = 1 in {
846
790847 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
791848 [(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))]
792849 >;
796853 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
797854 [(set VReg_32:$dst, (xor VSrc_32:$src0, VReg_32:$src1))]
798855 >;
856
857 } // End isCommutable = 1
858
799859 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>;
800860 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
801861 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
804864 //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
805865 //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
806866 let Defs = [VCC] in { // Carry-out goes to VCC
867
868 let isCommutable = 1 in {
807869 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
808870 [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
809871 >;
872 } // End isCommutable = 1
873
810874 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
811875 [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
812876 >;
877
813878 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
814879 let Uses = [VCC] in { // Carry-out comes from VCC
815880 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;