llvm.org GIT mirror llvm / b3cabb4
[SystemZ] Use zeroing form of RISBG for some AND sequences RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Sandiford 7 years ago
27 changed file(s) with 531 addition(s) and 300 deletion(s). Raw diff Collapse all Expand all
198198 SystemZAddressingMode::Disp20Pair,
199199 Addr, Base, Disp, Index);
200200 }
201
202 // Return an undefined i64 value.
203 SDValue getUNDEF64(SDLoc DL);
204
205 // Convert N to VT, if it isn't already.
206 SDValue convertTo(SDLoc DL, EVT VT, SDValue N);
207
208 // Try to use RISBG to implement ISD::AND node N. Return the selected
209 // node on success, otherwise return null.
210 SDNode *tryRISBGForAND(SDNode *N);
201211
202212 // If Op0 is null, then Node is a constant that can be loaded using:
203213 //
520530 return true;
521531 }
522532
533 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
534 // have already been filtered out. Store the first set bit in LSB and
535 // the number of set bits in Length if so.
536 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
537 unsigned First = findFirstSet(Mask);
538 uint64_t Top = (Mask >> First) + 1;
539 if ((Top & -Top) == Top)
540 {
541 LSB = First;
542 Length = findFirstSet(Top);
543 return true;
544 }
545 return false;
546 }
547
548 // Return a mask with Count low bits set.
549 static uint64_t allOnes(unsigned int Count) {
550 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
551 }
552
553 // Return true if RISBG can be used to extract the bits in Mask from
554 // a value that has BitSize bits. Store the start and end operands
555 // (I3 and I4) in Start and End if so.
556 static bool isRISBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start,
557 unsigned &End) {
558 // Reject trivial all-zero and all-one masks.
559 uint64_t Used = allOnes(BitSize);
560 if (Mask == 0 || Mask == Used)
561 return false;
562
563 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
564 // the msb and End specifies the index of the lsb.
565 unsigned LSB, Length;
566 if (isStringOfOnes(Mask, LSB, Length))
567 {
568 Start = 63 - (LSB + Length - 1);
569 End = 63 - LSB;
570 return true;
571 }
572
573 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
574 // of the low 1s and End specifies the lsb of the high 1s.
575 if (isStringOfOnes(Mask ^ Used, LSB, Length))
576 {
577 assert(LSB > 0 && "Bottom bit must be set");
578 assert(LSB + Length < BitSize && "Top bit must be set");
579 Start = 63 - (LSB - 1);
580 End = 63 - (LSB + Length);
581 return true;
582 }
583
584 return false;
585 }
586
587 SDValue SystemZDAGToDAGISel::getUNDEF64(SDLoc DL) {
588 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64);
589 return SDValue(N, 0);
590 }
591
592 SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) {
593 if (N.getValueType() == MVT::i32 && VT == MVT::i64) {
594 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
595 SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG,
596 DL, VT, getUNDEF64(DL), N, Index);
597 return SDValue(Insert, 0);
598 }
599 if (N.getValueType() == MVT::i64 && VT == MVT::i32) {
600 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
601 SDNode *Extract = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
602 DL, VT, N, Index);
603 return SDValue(Extract, 0);
604 }
605 assert(N.getValueType() == VT && "Unexpected value types");
606 return N;
607 }
608
609 SDNode *SystemZDAGToDAGISel::tryRISBGForAND(SDNode *N) {
610 EVT VT = N->getValueType(0);
611 unsigned BitSize = VT.getSizeInBits();
612 unsigned Start, End;
613 ConstantSDNode *MaskNode =
614 dyn_cast(N->getOperand(1).getNode());
615 if (!MaskNode
616 || !isRISBGMask(MaskNode->getZExtValue(), BitSize, Start, End))
617 return 0;
618
619 // Prefer register extensions like LLC over RSIBG.
620 if ((Start == 32 || Start == 48 || Start == 56) && End == 63)
621 return 0;
622
623 SDValue Ops[5] = {
624 getUNDEF64(SDLoc(N)),
625 convertTo(SDLoc(N), MVT::i64, N->getOperand(0)),
626 CurDAG->getTargetConstant(Start, MVT::i32),
627 CurDAG->getTargetConstant(End | 128, MVT::i32),
628 CurDAG->getTargetConstant(0, MVT::i32)
629 };
630 N = CurDAG->getMachineNode(SystemZ::RISBG, SDLoc(N), MVT::i64, Ops);
631 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
632 }
633
523634 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
524635 SDValue Op0, uint64_t UpperVal,
525636 uint64_t LowerVal) {
589700 }
590701
591702 unsigned Opcode = Node->getOpcode();
703 SDNode *ResNode = 0;
592704 switch (Opcode) {
593705 case ISD::OR:
594706 case ISD::XOR:
603715 }
604716 break;
605717
718 case ISD::AND:
719 ResNode = tryRISBGForAND(Node);
720 break;
721
606722 case ISD::Constant:
607723 // If this is a 64-bit constant that is out of the range of LLILF,
608724 // LLIHF and LGFI, split it into two 32-bit pieces.
630746 }
631747
632748 // Select the default instruction
633 SDNode *ResNode = SelectCode(Node);
749 if (!ResNode)
750 ResNode = SelectCode(Node);
634751
635752 DEBUG(errs() << "=> ";
636753 if (ResNode == NULL || ResNode == Node)
6464 ; An address with an index and a displacement added using OR.
6565 define void @f6(i64 %addr, i64 %index) {
6666 ; CHECK: f6:
67 ; CHECK: nill %r2, 65528
68 ; CHECK: lb %r0, 6(%r3,%r2)
67 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
68 ; CHECK: lb %r0, 6(%r3,[[BASE]])
6969 ; CHECK: br %r14
7070 %aligned = and i64 %addr, -8
7171 %or = or i64 %aligned, 6
9292 ; about the alignment of %add here.
9393 define void @f8(i64 %addr, i64 %index) {
9494 ; CHECK: f8:
95 ; CHECK: nill %r2, 65528
96 ; CHECK: agr %r2, %r3
97 ; CHECK: oill %r2, 6
98 ; CHECK: lb %r0, 0(%r2)
95 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
96 ; CHECK: agr [[BASE]], %r3
97 ; CHECK: oill [[BASE]], 6
98 ; CHECK: lb %r0, 0([[BASE]])
9999 ; CHECK: br %r14
100100 %aligned = and i64 %addr, -8
101101 %add = add i64 %aligned, %index
7070 ; An address with an index and a displacement added using OR.
7171 define void @f6(i64 %addr, i64 %index, i8 **%dst) {
7272 ; CHECK: f6:
73 ; CHECK: nill %r2, 65528
74 ; CHECK: lb %r0, 6(%r3,%r2)
73 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
74 ; CHECK: lb %r0, 6(%r3,[[BASE]])
7575 ; CHECK: br %r14
7676 %aligned = and i64 %addr, -8
7777 %or = or i64 %aligned, 6
100100 ; about the alignment of %add here.
101101 define void @f8(i64 %addr, i64 %index, i8 **%dst) {
102102 ; CHECK: f8:
103 ; CHECK: nill %r2, 65528
104 ; CHECK: agr %r2, %r3
105 ; CHECK: oill %r2, 6
106 ; CHECK: lb %r0, 0(%r2)
103 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
104 ; CHECK: agr [[BASE]], %r3
105 ; CHECK: oill [[BASE]], 6
106 ; CHECK: lb %r0, 0([[BASE]])
107107 ; CHECK: br %r14
108108 %aligned = and i64 %addr, -8
109109 %add = add i64 %aligned, %index
0 ; Test variable-sized allocas and addresses based on them in cases where
11 ; stack arguments are needed.
22 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK1
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK2
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
54 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
65 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
76 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
1413 ; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
1514 ; is added to the copy of %r15.
1615 define i64 @f1(i64 %length, i64 %index) {
17 ; The full allocation sequence is:
18 ;
19 ; la %r0, 7(%r2) 1
20 ; nill %r0, 0xfff8 1
21 ; lgr %r1, %r15 2
22 ; sgr %r1, %r0 1 2
23 ; lgr %r15, %r1 2
24 ;
25 ; The third instruction does not depend on the first two, so check for
26 ; two fully-ordered sequences.
27 ;
2816 ; FIXME: a better sequence would be:
2917 ;
3018 ; lgr %r1, %r15
3119 ; sgr %r1, %r2
32 ; nill %r1, 0xfff8
20 ; risbg %r1, %r1, 0, 188, 0
3321 ; lgr %r15, %r1
3422 ;
35 ; CHECK1: f1:
36 ; CHECK1: la %r0, 7(%r2)
37 ; CHECK1: nill %r0, 65528
38 ; CHECK1: sgr %r1, %r0
39 ; CHECK1: lgr %r15, %r1
40 ;
41 ; CHECK2: f1:
42 ; CHECK2: lgr %r1, %r15
43 ; CHECK2: sgr %r1, %r0
44 ; CHECK2: lgr %r15, %r1
23 ; CHECK: f1:
24 ; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
25 ; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
26 ; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
27 ; CHECK: sgr [[REG3]], [[REG2]]
28 ; CHECK: lgr %r15, [[REG3]]
4529 ;
4630 ; CHECK-A: f1:
4731 ; CHECK-A: lgr %r15, %r1
11 ;
22 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
33
4 ; Check the lowest useful NILF value.
4 ; ANDs with 1 should use RISBG
55 define i32 @f1(i32 %a) {
66 ; CHECK: f1:
7 ; CHECK: nilf %r2, 1
7 ; CHECK: risbg %r2, %r2, 63, 191, 0
88 ; CHECK: br %r14
99 %and = and i32 %a, 1
1010 ret i32 %and
1111 }
1212
13 ; Check the highest 16-bit constant that must be handled by NILF.
13 ; ...same for 2.
1414 define i32 @f2(i32 %a) {
1515 ; CHECK: f2:
16 ; CHECK: nilf %r2, 65534
17 ; CHECK: br %r14
18 %and = and i32 %a, 65534
19 ret i32 %and
20 }
21
22 ; ANDs of 0xffff are zero extensions from i16.
16 ; CHECK: risbg %r2, %r2, 62, 190, 0
17 ; CHECK: br %r14
18 %and = and i32 %a, 2
19 ret i32 %and
20 }
21
22 ; ...and 3.
2323 define i32 @f3(i32 %a) {
2424 ; CHECK: f3:
25 ; CHECK: llhr %r2, %r2
26 ; CHECK: br %r14
27 %and = and i32 %a, 65535
28 ret i32 %and
29 }
30
31 ; Check the next value up, which must again use NILF.
25 ; CHECK: risbg %r2, %r2, 62, 191, 0
26 ; CHECK: br %r14
27 %and = and i32 %a, 3
28 ret i32 %and
29 }
30
31 ; ...and 4.
3232 define i32 @f4(i32 %a) {
3333 ; CHECK: f4:
34 ; CHECK: nilf %r2, 65536
35 ; CHECK: br %r14
36 %and = and i32 %a, 65536
37 ret i32 %and
38 }
39
40 ; Check the lowest useful NILH value. (LLHR is used instead of NILH of 0.)
34 ; CHECK: risbg %r2, %r2, 61, 189, 0
35 ; CHECK: br %r14
36 %and = and i32 %a, 4
37 ret i32 %and
38 }
39
40 ; Check the lowest useful NILF value.
4141 define i32 @f5(i32 %a) {
4242 ; CHECK: f5:
43 ; CHECK: nilh %r2, 1
44 ; CHECK: br %r14
45 %and = and i32 %a, 131071
46 ret i32 %and
47 }
48
49 ; Check the highest useful NILF value.
43 ; CHECK: nilf %r2, 5
44 ; CHECK: br %r14
45 %and = and i32 %a, 5
46 ret i32 %and
47 }
48
49 ; Check the highest 16-bit constant that must be handled by NILF.
5050 define i32 @f6(i32 %a) {
5151 ; CHECK: f6:
52 ; CHECK: nilf %r2, 4294901758
53 ; CHECK: br %r14
54 %and = and i32 %a, -65538
55 ret i32 %and
56 }
57
58 ; Check the highest useful NILH value, which is one up from the above.
52 ; CHECK: nilf %r2, 65533
53 ; CHECK: br %r14
54 %and = and i32 %a, 65533
55 ret i32 %and
56 }
57
58 ; ANDs of 0xffff are zero extensions from i16.
5959 define i32 @f7(i32 %a) {
6060 ; CHECK: f7:
61 ; CHECK: nilh %r2, 65534
62 ; CHECK: br %r14
63 %and = and i32 %a, -65537
64 ret i32 %and
65 }
66
67 ; Check the low end of the NILL range, which is one up again.
61 ; CHECK: llhr %r2, %r2
62 ; CHECK: br %r14
63 %and = and i32 %a, 65535
64 ret i32 %and
65 }
66
67 ; Check the next value up, which can use RISBG.
6868 define i32 @f8(i32 %a) {
6969 ; CHECK: f8:
70 ; CHECK: nill %r2, 0
71 ; CHECK: br %r14
72 %and = and i32 %a, -65536
73 ret i32 %and
74 }
75
76 ; Check the next value up.
70 ; CHECK: risbg %r2, %r2, 47, 175, 0
71 ; CHECK: br %r14
72 %and = and i32 %a, 65536
73 ret i32 %and
74 }
75
76 ; Check the next value up, which must again use NILF.
7777 define i32 @f9(i32 %a) {
7878 ; CHECK: f9:
79 ; CHECK: nill %r2, 1
80 ; CHECK: br %r14
81 %and = and i32 %a, -65535
82 ret i32 %and
83 }
84
85 ; Check the highest useful NILL value.
79 ; CHECK: nilf %r2, 65537
80 ; CHECK: br %r14
81 %and = and i32 %a, 65537
82 ret i32 %and
83 }
84
85 ; This value is in range of NILH, but we use RISBG instead.
8686 define i32 @f10(i32 %a) {
8787 ; CHECK: f10:
88 ; CHECK: nill %r2, 65534
88 ; CHECK: risbg %r2, %r2, 47, 191, 0
89 ; CHECK: br %r14
90 %and = and i32 %a, 131071
91 ret i32 %and
92 }
93
94 ; Check the lowest useful NILH value.
95 define i32 @f11(i32 %a) {
96 ; CHECK: f11:
97 ; CHECK: nilh %r2, 2
98 ; CHECK: br %r14
99 %and = and i32 %a, 196607
100 ret i32 %and
101 }
102
103 ; Check the highest useful NILH value.
104 define i32 @f12(i32 %a) {
105 ; CHECK: f12:
106 ; CHECK: nilh %r2, 65530
107 ; CHECK: br %r14
108 %and = and i32 %a, -327681
109 ret i32 %and
110 }
111
112 ; Check the equivalent of NILH of 65531, which can use RISBG.
113 define i32 @f13(i32 %a) {
114 ; CHECK: f13:
115 ; CHECK: risbg %r2, %r2, 46, 172, 0
116 ; CHECK: br %r14
117 %and = and i32 %a, -262145
118 ret i32 %and
119 }
120
121 ; ...same for 65532.
122 define i32 @f14(i32 %a) {
123 ; CHECK: f14:
124 ; CHECK: risbg %r2, %r2, 48, 173, 0
125 ; CHECK: br %r14
126 %and = and i32 %a, -196609
127 ret i32 %and
128 }
129
130 ; ...and 65533.
131 define i32 @f15(i32 %a) {
132 ; CHECK: f15:
133 ; CHECK: risbg %r2, %r2, 47, 173, 0
134 ; CHECK: br %r14
135 %and = and i32 %a, -131073
136 ret i32 %and
137 }
138
139 ; Check the highest useful NILF value.
140 define i32 @f16(i32 %a) {
141 ; CHECK: f16:
142 ; CHECK: nilf %r2, 4294901758
143 ; CHECK: br %r14
144 %and = and i32 %a, -65538
145 ret i32 %and
146 }
147
148 ; Check the next value up, which is the equivalent of an NILH of 65534.
149 ; We use RISBG instead.
150 define i32 @f17(i32 %a) {
151 ; CHECK: f17:
152 ; CHECK: risbg %r2, %r2, 48, 174, 0
153 ; CHECK: br %r14
154 %and = and i32 %a, -65537
155 ret i32 %and
156 }
157
158 ; Check the next value up, which can also use RISBG.
159 define i32 @f18(i32 %a) {
160 ; CHECK: f18:
161 ; CHECK: risbg %r2, %r2, 32, 175, 0
162 ; CHECK: br %r14
163 %and = and i32 %a, -65536
164 ret i32 %and
165 }
166
167 ; ...and again.
168 define i32 @f19(i32 %a) {
169 ; CHECK: f19:
170 ; CHECK: risbg %r2, %r2, 63, 175, 0
171 ; CHECK: br %r14
172 %and = and i32 %a, -65535
173 ret i32 %and
174 }
175
176 ; Check the next value up again, which is the lowest useful NILL value.
177 define i32 @f20(i32 %a) {
178 ; CHECK: f20:
179 ; CHECK: nill %r2, 2
180 ; CHECK: br %r14
181 %and = and i32 %a, -65534
182 ret i32 %and
183 }
184
185 ; Check the highest useful NILL value.
186 define i32 @f21(i32 %a) {
187 ; CHECK: f21:
188 ; CHECK: nill %r2, 65530
189 ; CHECK: br %r14
190 %and = and i32 %a, -6
191 ret i32 %and
192 }
193
194 ; Check the next value up, which can use RISBG.
195 define i32 @f22(i32 %a) {
196 ; CHECK: f22:
197 ; CHECK: risbg %r2, %r2, 62, 188, 0
198 ; CHECK: br %r14
199 %and = and i32 %a, -5
200 ret i32 %and
201 }
202
203 ; ...and again.
204 define i32 @f23(i32 %a) {
205 ; CHECK: f23:
206 ; CHECK: risbg %r2, %r2, 32, 189, 0
207 ; CHECK: br %r14
208 %and = and i32 %a, -4
209 ret i32 %and
210 }
211
212 ; ...and again.
213 define i32 @f24(i32 %a) {
214 ; CHECK: f24:
215 ; CHECK: risbg %r2, %r2, 63, 189, 0
216 ; CHECK: br %r14
217 %and = and i32 %a, -3
218 ret i32 %and
219 }
220
221 ; Check the last useful mask.
222 define i32 @f25(i32 %a) {
223 ; CHECK: f25:
224 ; CHECK: risbg %r2, %r2, 32, 190, 0
89225 ; CHECK: br %r14
90226 %and = and i32 %a, -2
91227 ret i32 %and
11 ;
22 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
33
4 ; There is no 64-bit AND instruction for a mask of 1.
5 ; FIXME: we ought to be able to require "ngr %r2, %r0", but at the moment,
6 ; two-address optimisations force "ngr %r0, %r2; lgr %r2, %r0" instead.
4 ; Use RISBG for a single bit.
75 define i64 @f1(i64 %a) {
86 ; CHECK: f1:
9 ; CHECK: lghi %r0, 1
10 ; CHECK: ngr
7 ; CHECK: risbg %r2, %r2, 63, 191, 0
118 ; CHECK: br %r14
129 %and = and i64 %a, 1
1310 ret i64 %and
1613 ; Likewise 0xfffe.
1714 define i64 @f2(i64 %a) {
1815 ; CHECK: f2:
19 ; CHECK: llill %r0, 65534
20 ; CHECK: ngr
16 ; CHECK: risbg %r2, %r2, 48, 190, 0
2117 ; CHECK: br %r14
2218 %and = and i64 %a, 65534
2319 ret i64 %and
3228 ret i64 %and
3329 }
3430
35 ; Check the next value up, which again has no dedicated instruction.
31 ; Check the next value up, which can again use RISBG.
3632 define i64 @f4(i64 %a) {
3733 ; CHECK: f4:
38 ; CHECK: llilh %r0, 1
39 ; CHECK: ngr
34 ; CHECK: risbg %r2, %r2, 47, 175, 0
4035 ; CHECK: br %r14
4136 %and = and i64 %a, 65536
4237 ret i64 %and
4338 }
4439
45 ; Check 0xfffffffe.
40 ; Check 0xfffffffe, which can also use RISBG.
4641 define i64 @f5(i64 %a) {
4742 ; CHECK: f5:
48 ; CHECK: lilf %r0, 4294967294
49 ; CHECK: ngr
43 ; CHECK: risbg %r2, %r2, 32, 190, 0
5044 ; CHECK: br %r14
5145 %and = and i64 %a, 4294967294
5246 ret i64 %and
6155 ret i64 %and
6256 }
6357
64 ; Check the lowest useful NIHF value (0x00000001_ffffffff).
58 ; Check the lowest useful NIHF value (0x00000002_ffffffff).
6559 define i64 @f7(i64 %a) {
6660 ; CHECK: f7:
67 ; CHECK: nihf %r2, 1
61 ; CHECK: nihf %r2, 2
6862 ; CHECK: br %r14
69 %and = and i64 %a, 8589934591
63 %and = and i64 %a, 12884901887
7064 ret i64 %and
7165 }
7266
73 ; Check the low end of the NIHH range (0x0000ffff_ffffffff).
67 ; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
7468 define i64 @f8(i64 %a) {
7569 ; CHECK: f8:
76 ; CHECK: nihh %r2, 0
70 ; CHECK: nihh %r2, 2
7771 ; CHECK: br %r14
78 %and = and i64 %a, 281474976710655
72 %and = and i64 %a, 844424930131967
7973 ret i64 %and
8074 }
8175
82 ; Check the highest useful NIHH value (0xfffeffff_ffffffff).
76 ; Check the highest useful NIHH value (0xfffaffff_ffffffff).
8377 define i64 @f9(i64 %a) {
8478 ; CHECK: f9:
85 ; CHECK: nihh %r2, 65534
79 ; CHECK: nihh %r2, 65530
8680 ; CHECK: br %r14
87 %and = and i64 %a, -281474976710657
81 %and = and i64 %a, -1407374883553281
8882 ret i64 %and
8983 }
9084
9791 ret i64 %and
9892 }
9993
100 ; Check the low end of the NIHL range (0xffff0000_ffffffff).
94 ; Check the lowest useful NIHL value (0xffff0002_ffffffff).
10195 define i64 @f11(i64 %a) {
10296 ; CHECK: f11:
103 ; CHECK: nihl %r2, 0
97 ; CHECK: nihl %r2, 2
10498 ; CHECK: br %r14
105 %and = and i64 %a, -281470681743361
99 %and = and i64 %a, -281462091808769
106100 ret i64 %and
107101 }
108102
109 ; Check the highest useful NIHL value (0xfffffffe_ffffffff).
103 ; Check the highest useful NIHL value (0xfffffffa_ffffffff).
110104 define i64 @f12(i64 %a) {
111105 ; CHECK: f12:
112 ; CHECK: nihl %r2, 65534
106 ; CHECK: nihl %r2, 65530
113107 ; CHECK: br %r14
114 %and = and i64 %a, -4294967297
108 %and = and i64 %a, -21474836481
115109 ret i64 %and
116110 }
117111
118 ; Check the low end of the NILF range (0xffffffff_00000000).
112 ; Check the lowest useful NILF range (0xffffffff_00000002).
119113 define i64 @f13(i64 %a) {
120114 ; CHECK: f13:
121 ; CHECK: nilf %r2, 0
115 ; CHECK: nilf %r2, 2
122116 ; CHECK: br %r14
123 %and = and i64 %a, -4294967296
117 %and = and i64 %a, -4294967294
124118 ret i64 %and
125119 }
126120
127 ; Check the low end of the NILH range (0xffffffff_0000ffff).
121 ; Check the low end of the NILH range (0xffffffff_0002ffff).
128122 define i64 @f14(i64 %a) {
129123 ; CHECK: f14:
130 ; CHECK: nilh %r2, 0
124 ; CHECK: nilh %r2, 2
131125 ; CHECK: br %r14
132 %and = and i64 %a, -4294901761
126 %and = and i64 %a, -4294770689
133127 ret i64 %and
134128 }
135129
136130 ; Check the next value up, which must use NILF.
137131 define i64 @f15(i64 %a) {
138132 ; CHECK: f15:
139 ; CHECK: nilf %r2, 65536
133 ; CHECK: nilf %r2, 196608
140134 ; CHECK: br %r14
141 %and = and i64 %a, -4294901760
135 %and = and i64 %a, -4294770688
136 ret i64 %and
137 }
138
139 ; Check the highest useful NILH value (0xffffffff_fffaffff).
140 define i64 @f16(i64 %a) {
141 ; CHECK: f16:
142 ; CHECK: nilh %r2, 65530
143 ; CHECK: br %r14
144 %and = and i64 %a, -327681
142145 ret i64 %and
143146 }
144147
145148 ; Check the maximum useful NILF value (0xffffffff_fffefffe).
146 define i64 @f16(i64 %a) {
147 ; CHECK: f16:
149 define i64 @f17(i64 %a) {
150 ; CHECK: f17:
148151 ; CHECK: nilf %r2, 4294901758
149152 ; CHECK: br %r14
150153 %and = and i64 %a, -65538
151154 ret i64 %and
152155 }
153156
154 ; Check the highest useful NILH value, which is one greater than the above.
155 define i64 @f17(i64 %a) {
156 ; CHECK: f17:
157 ; CHECK: nilh %r2, 65534
158 ; CHECK: br %r14
159 %and = and i64 %a, -65537
160 ret i64 %and
161 }
162
163 ; Check the low end of the NILL range, which is one greater again.
157 ; Check the lowest useful NILL value (0xffffffff_ffff0002).
164158 define i64 @f18(i64 %a) {
165159 ; CHECK: f18:
166 ; CHECK: nill %r2, 0
160 ; CHECK: nill %r2, 2
167161 ; CHECK: br %r14
168 %and = and i64 %a, -65536
162 %and = and i64 %a, -65534
169163 ret i64 %and
170164 }
171165
172166 ; Check the highest useful NILL value.
173167 define i64 @f19(i64 %a) {
174168 ; CHECK: f19:
175 ; CHECK: nill %r2, 65534
169 ; CHECK: nill %r2, 65530
176170 ; CHECK: br %r14
177 %and = and i64 %a, -2
171 %and = and i64 %a, -6
178172 ret i64 %and
179173 }
1313 ; instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: ar [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We add 0x80000000 to the rotated word.
4848 define i8 @f2(i8 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: ar [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We add 0x80000000 to the rotated word.
4848 define i16 @f2(i16 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
4848 ; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
4949 define i8 @f2(i8 *%src) {
5050 ; CHECK: f2:
51 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
52 ; CHECK: nill %r2, 65532
53 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
51 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
52 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
53 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5454 ; CHECK: [[LABEL:\.[^:]*]]:
5555 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5656 ; CHECK: nilh [[ROT]], 33023
5757 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
58 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5959 ; CHECK: jlh [[LABEL]]
6060 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6161 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
4848 ; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
4949 define i16 @f2(i16 *%src) {
5050 ; CHECK: f2:
51 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
52 ; CHECK: nill %r2, 65532
53 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
51 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
52 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
53 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5454 ; CHECK: [[LABEL:\.[^:]*]]:
5555 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5656 ; CHECK: nilh [[ROT]], 32768
5757 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
58 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
58 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5959 ; CHECK: jlh [[LABEL]]
6060 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6161 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LOOP:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
2222 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
2323 ; CHECK: [[KEEP]]:
2424 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
25 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
25 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2626 ; CHECK: jlh [[LOOP]]
2727 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2828 ; CHECK: br %r14
4949 ; Check signed maximum.
5050 define i8 @f2(i8 *%src, i8 %b) {
5151 ; CHECK: f2:
52 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK: nill %r2, 65532
54 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
52 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
54 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5555 ; CHECK: [[LOOP:\.[^:]*]]:
5656 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5757 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
5858 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
5959 ; CHECK: [[KEEP]]:
6060 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
61 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
61 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
6262 ; CHECK: jlh [[LOOP]]
6363 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6464 ; CHECK: br %r14
8585 ; Check unsigned minimum.
8686 define i8 @f3(i8 *%src, i8 %b) {
8787 ; CHECK: f3:
88 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
89 ; CHECK: nill %r2, 65532
90 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
88 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
89 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
90 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
9191 ; CHECK: [[LOOP:\.[^:]*]]:
9292 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
9393 ; CHECK: clr [[ROT]], %r3
9595 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
9696 ; CHECK: [[KEEP]]:
9797 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
98 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
98 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
9999 ; CHECK: jlh [[LOOP]]
100100 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
101101 ; CHECK: br %r14
122122 ; Check unsigned maximum.
123123 define i8 @f4(i8 *%src, i8 %b) {
124124 ; CHECK: f4:
125 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
126 ; CHECK: nill %r2, 65532
127 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
125 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
126 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
127 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
128128 ; CHECK: [[LOOP:\.[^:]*]]:
129129 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
130130 ; CHECK: clr [[ROT]], %r3
132132 ; CHECK: risbg [[ROT]], %r3, 32, 39, 0
133133 ; CHECK: [[KEEP]]:
134134 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
135 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
135 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
136136 ; CHECK: jlh [[LOOP]]
137137 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
138138 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LOOP:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
2222 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
2323 ; CHECK: [[KEEP]]:
2424 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
25 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
25 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2626 ; CHECK: jlh [[LOOP]]
2727 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2828 ; CHECK: br %r14
4949 ; Check signed maximum.
5050 define i16 @f2(i16 *%src, i16 %b) {
5151 ; CHECK: f2:
52 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK: nill %r2, 65532
54 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
52 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
54 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5555 ; CHECK: [[LOOP:\.[^:]*]]:
5656 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5757 ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
5858 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
5959 ; CHECK: [[KEEP]]:
6060 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
61 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
61 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
6262 ; CHECK: jlh [[LOOP]]
6363 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6464 ; CHECK: br %r14
8585 ; Check unsigned minimum.
8686 define i16 @f3(i16 *%src, i16 %b) {
8787 ; CHECK: f3:
88 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
89 ; CHECK: nill %r2, 65532
90 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
88 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
89 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
90 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
9191 ; CHECK: [[LOOP:\.[^:]*]]:
9292 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
9393 ; CHECK: clr [[ROT]], %r3
9595 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
9696 ; CHECK: [[KEEP]]:
9797 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
98 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
98 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
9999 ; CHECK: jlh [[LOOP]]
100100 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
101101 ; CHECK: br %r14
122122 ; Check unsigned maximum.
123123 define i16 @f4(i16 *%src, i16 %b) {
124124 ; CHECK: f4:
125 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
126 ; CHECK: nill %r2, 65532
127 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
125 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
126 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
127 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
128128 ; CHECK: [[LOOP:\.[^:]*]]:
129129 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
130130 ; CHECK: clr [[ROT]], %r3
132132 ; CHECK: risbg [[ROT]], %r3, 32, 47, 0
133133 ; CHECK: [[KEEP]]:
134134 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
135 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
135 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
136136 ; CHECK: jlh [[LOOP]]
137137 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
138138 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: xilf [[ROT]], 4278190080
2323 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
24 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2525 ; CHECK: jlh [[LABEL]]
2626 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2727 ; CHECK: br %r14
4949 ; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
5050 define i8 @f2(i8 *%src) {
5151 ; CHECK: f2:
52 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK: nill %r2, 65532
54 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
52 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
54 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5555 ; CHECK: [[LABEL:\.[^:]*]]:
5656 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5757 ; CHECK: nilh [[ROT]], 33023
5858 ; CHECK: xilf [[ROT]], 4278190080
5959 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
60 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
60 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
6161 ; CHECK: jlh [[LABEL]]
6262 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6363 ; CHECK: br %r14
1313 ; independent of the other loop prologue instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: nr [[ROT]], %r3
2222 ; CHECK: xilf [[ROT]], 4294901760
2323 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
24 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
24 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2525 ; CHECK: jlh [[LABEL]]
2626 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2727 ; CHECK: br %r14
4949 ; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
5050 define i16 @f2(i16 *%src) {
5151 ; CHECK: f2:
52 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK: nill %r2, 65532
54 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
52 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
53 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
54 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5555 ; CHECK: [[LABEL:\.[^:]*]]:
5656 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5757 ; CHECK: nilh [[ROT]], 32768
5858 ; CHECK: xilf [[ROT]], 4294901760
5959 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
60 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
60 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
6161 ; CHECK: jlh [[LABEL]]
6262 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6363 ; CHECK: br %r14
1313 ; instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: or [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We OR the rotated word with 0x80000000.
4848 define i8 @f2(i8 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: oilh [[ROT]], 32768
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: or [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We OR the rotated word with 0x80000000.
4848 define i16 @f2(i16 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: oilh [[ROT]], 32768
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: sr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We add 0x80000000 to the rotated word.
4848 define i8 @f2(i8 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: sr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We add 0x80000000 to the rotated word.
4848 define i16 @f2(i16 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: afi [[ROT]], -2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
1111 ; which shift %r3 left so that %b is at the high end of the word).
1212 define i8 @f1(i8 *%src, i8 %b) {
1313 ; CHECK: f1:
14 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
15 ; CHECK: nill %r2, 65532
16 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
14 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
15 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
16 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1717 ; CHECK: [[LABEL:\.[^:]*]]:
1818 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
1919 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
2020 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
21 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
21 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2222 ; CHECK: jlh [[LABEL]]
2323 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2424 ; CHECK: br %r14
1111 ; which shift %r3 left so that %b is at the high end of the word).
1212 define i16 @f1(i16 *%src, i16 %b) {
1313 ; CHECK: f1:
14 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
15 ; CHECK: nill %r2, 65532
16 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
14 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
15 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
16 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1717 ; CHECK: [[LABEL:\.[^:]*]]:
1818 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
1919 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
2020 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
21 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
21 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2222 ; CHECK: jlh [[LABEL]]
2323 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2424 ; CHECK: br %r14
1313 ; instructions.
1414 define i8 @f1(i8 *%src, i8 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: xr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
4848 define i8 @f2(i8 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: xilf [[ROT]], 2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
6060 ; CHECK: br %r14
1313 ; instructions.
1414 define i16 @f1(i16 *%src, i16 %b) {
1515 ; CHECK: f1:
16 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK: nill %r2, 65532
18 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
16 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
17 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
18 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
1919 ; CHECK: [[LABEL:\.[^:]*]]:
2020 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
2121 ; CHECK: xr [[ROT]], %r3
2222 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
23 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
23 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK: jlh [[LABEL]]
2525 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
2626 ; CHECK: br %r14
4747 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
4848 define i16 @f2(i16 *%src) {
4949 ; CHECK: f2:
50 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK: nill %r2, 65532
52 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
50 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
51 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
52 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
5353 ; CHECK: [[LABEL:\.[^:]*]]:
5454 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
5555 ; CHECK: xilf [[ROT]], 2147483648
5656 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
57 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
57 ; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
5858 ; CHECK: jlh [[LABEL]]
5959 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
6060 ; CHECK: br %r14
1111 ; which shift %r3 left so that %b is at the high end of the word).
1212 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
1313 ; CHECK-MAIN: f1:
14 ; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
15 ; CHECK-MAIN: nill %r3, 65532
16 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
14 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
15 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
16 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
1717 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
1818 ; CHECK-MAIN: rll %r2, [[OLD]], 8([[SHIFT]])
1919 ; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0
2020 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
2121 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
2222 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
23 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
23 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK-MAIN: jlh [[LOOP]]
2525 ; CHECK-MAIN: [[EXIT]]:
2626 ; CHECK-MAIN-NOT: %r2
1111 ; which shift %r3 left so that %b is at the high end of the word).
1212 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
1313 ; CHECK-MAIN: f1:
14 ; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
15 ; CHECK-MAIN: nill %r3, 65532
16 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
14 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
15 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
16 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
1717 ; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
1818 ; CHECK-MAIN: rll %r2, [[OLD]], 16([[SHIFT]])
1919 ; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0
2020 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
2121 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
2222 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
23 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
23 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[BASE]])
2424 ; CHECK-MAIN: jlh [[LOOP]]
2525 ; CHECK-MAIN: [[EXIT]]:
2626 ; CHECK-MAIN-NOT: %r2
3838 define float @f4(i64 %big) {
3939 ; CHECK: f4:
4040 ; CHECK-NOT: %r2
41 ; CHECK: nilf %r2, 0
42 ; CHECK-NOT: %r2
43 ; CHECK: ldgr %f0, %r2
41 ; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
42 ; CHECK-NOT: [[REG]]
43 ; CHECK: ldgr %f0, [[REG]]
4444 %shift = ashr i64 %big, 32
4545 %a = trunc i64 %shift to i32
4646 %res = bitcast i32 %a to float
3232 ; register value. We can use IC but must keep the original mask.
3333 define i32 @f3(i32 %orig, i8 *%ptr) {
3434 ; CHECK: f3:
35 ; CHECK: nill %r2, 65024
35 ; CHECK: risbg %r2, %r2, 32, 182, 0
3636 ; CHECK: ic %r2, 0(%r3)
3737 ; CHECK: br %r14
3838 %val = load i8 *%ptr
4545 ; Like f3, but with the operands reversed.
4646 define i32 @f4(i32 %orig, i8 *%ptr) {
4747 ; CHECK: f4:
48 ; CHECK: nill %r2, 65024
48 ; CHECK: risbg %r2, %r2, 32, 182, 0
4949 ; CHECK: ic %r2, 0(%r3)
5050 ; CHECK: br %r14
5151 %val = load i8 *%ptr
3232 ; register value. We can use IC but must keep the original mask.
3333 define i64 @f3(i64 %orig, i8 *%ptr) {
3434 ; CHECK: f3:
35 ; CHECK: nill %r2, 65024
35 ; CHECK: risbg %r2, %r2, 0, 182, 0
3636 ; CHECK: ic %r2, 0(%r3)
3737 ; CHECK: br %r14
3838 %val = load i8 *%ptr
4545 ; Like f3, but with the operands reversed.
4646 define i64 @f4(i64 %orig, i8 *%ptr) {
4747 ; CHECK: f4:
48 ; CHECK: nill %r2, 65024
48 ; CHECK: risbg %r2, %r2, 0, 182, 0
4949 ; CHECK: ic %r2, 0(%r3)
5050 ; CHECK: br %r14
5151 %val = load i8 *%ptr