llvm.org GIT mirror llvm / b38a312
Merge 81310 from mainline. Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81639 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 10 years ago
1 changed file(s) with 21 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
903903
904904 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
905905 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
906 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
906 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
907 let Inst{25} = 1;
908 }
907909
908910 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
909911 "mov", " $dst, $src, rrx",
988990 // These don't define reg/reg forms, because they are handled above.
989991 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
990992 IIC_iALUi, "rsb", " $dst, $a, $b",
991 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
993 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
994 let Inst{25} = 1;
995 }
992996
993997 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
994998 IIC_iALUsr, "rsb", " $dst, $a, $b",
9981002 let Defs = [CPSR] in {
9991003 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
10001004 IIC_iALUi, "rsb", "s $dst, $a, $b",
1001 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
1005 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1006 let Inst{25} = 1;
1007 }
10021008 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
10031009 IIC_iALUsr, "rsb", "s $dst, $a, $b",
10041010 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
10081014 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
10091015 DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
10101016 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1011 Requires<[IsARM, CarryDefIsUnused]>;
1017 Requires<[IsARM, CarryDefIsUnused]> {
1018 let Inst{25} = 1;
1019 }
10121020 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
10131021 DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
10141022 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
10201028 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
10211029 DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
10221030 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1023 Requires<[IsARM, CarryDefIsUnused]>;
1031 Requires<[IsARM, CarryDefIsUnused]> {
1032 let Inst{25} = 1;
1033 }
10241034 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
10251035 DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
10261036 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
10741084 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
10751085 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
10761086 IIC_iMOVi, "mvn", " $dst, $imm",
1077 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
1087 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1088 let Inst{25} = 1;
1089 }
10781090
10791091 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
10801092 (BICri GPR:$src, so_imm_not:$imm)>;
13921404 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
13931405 "mov", " $dst, $true",
13941406 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1395 RegConstraint<"$false = $dst">, UnaryDP;
1407 RegConstraint<"$false = $dst">, UnaryDP {
1408 let Inst{25} = 1;
1409 }
13961410
13971411
13981412 //===----------------------------------------------------------------------===//