llvm.org GIT mirror llvm / b385e06
[release_36] Cherry-pick r231219. Original message: [DAGCombine] Fix a bug in a BUILD_VECTOR combine When trying to convert a BUILD_VECTOR into a shuffle, we try to split a single source vector that is twice as wide as the destination vector. We can not do this when we also need the zero vector to create a blend. This fixes PR22774. Differential Revision: http://reviews.llvm.org/D8040 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@232807 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 5 years ago
2 changed file(s) with 23 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
1104611046 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
1104711047 // If the input vector is too large, try to split it.
1104811048 // We don't support having two input vectors that are too large.
11049 if (VecIn2.getNode())
11049 // If the zero vector was used, we can not split the vector,
11050 // since we'd need 3 inputs.
11051 if (UsesZeroVector || VecIn2.getNode())
1105011052 return SDValue();
1105111053
1105211054 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
1105811060 DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy()));
1105911061 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
1106011062 DAG.getConstant(0, TLI.getVectorIdxTy()));
11061 UsesZeroVector = false;
1106211063 } else
1106311064 return SDValue();
1106411065 }
0 ; RUN: llc -mattr=avx %s -o - | FileCheck %s
1
2 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
3 target triple = "x86_64-pc-linux-gnu"
4
5 @in = global <4 x i64> , align 32
6 @out = global <2 x i64> zeroinitializer, align 16
7
8 define i32 @_Z3foov() {
9 entry:
10 ; CHECK: {{vmovdqa|vmovaps}} in(%rip), %ymm0
11 ; CHECK-NEXT: vmovq %xmm0, %xmm0
12 ; CHECK-NEXT: {{vmovdqa|vmovaps}} %xmm0, out(%rip)
13 %0 = load <4 x i64>* @in, align 32
14 %vecext = extractelement <4 x i64> %0, i32 0
15 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
16 %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
17 store <2 x i64> %vecinit1, <2 x i64>* @out, align 16
18 ret i32 0
19 }