llvm.org GIT mirror llvm / b371f45
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
23 changed file(s) with 346 addition(s) and 116 deletion(s). Raw diff Collapse all Expand all
117117 return I->second;
118118 }
119119
120 bool hasInterval(unsigned reg) const {
121 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
122 return I != r2iMap_.end();
123 }
124
120125 /// getMBBStartIdx - Return the base index of the first instruction in the
121126 /// specified MachineBasicBlock.
122127 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
188193 /// copies that cannot yet be coallesced into the "TryAgain" list.
189194 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
190195 std::vector &TryAgain);
196
191197 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
192198 /// which are the src/dst of the copy instruction CopyMI. This returns true
193199 /// if the copy was successfully coallesced away, or if it is never possible
232238 LiveInterval &interval,
233239 unsigned SrcReg);
234240
241 /// handleLiveInRegister - Create interval for a livein register.
242 void handleLiveInRegister(MachineBasicBlock* mbb, LiveInterval &interval);
243
235244 /// Return true if the two specified registers belong to different
236245 /// register classes. The registers may be either phys or virt regs.
237246 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
240249 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
241250 MachineInstr *CopyMI);
242251
243 bool overlapsAliases(const LiveInterval *lhs,
244 const LiveInterval *rhs) const;
252 /// hasRegisterUse - Returns true if there is any use of the specific
253 /// reg between indexes Start and End.
254 bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
245255
246256 static LiveInterval createInterval(unsigned Reg);
257
258 void removeInterval(unsigned Reg) {
259 r2iMap_.erase(Reg);
260 }
247261
248262 LiveInterval &getOrCreateInterval(unsigned reg) {
249263 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
3535 namespace llvm {
3636
3737 class MRegisterInfo;
38 class BitVector;
3839
3940 class LiveVariables : public MachineFunctionPass {
4041 public:
107108 ///
108109 std::vector VirtRegInfo;
109110
110 /// AllocatablePhysicalRegisters - This vector keeps track of which registers
111 /// are actually register allocatable by the target machine. We can not track
112 /// liveness for values that are not in this set.
113 ///
114 BitVector AllocatablePhysicalRegisters;
111 /// ReservedRegisters - This vector keeps track of which registers
112 /// are reserved register which are not allocatable by the target machine.
113 /// We can not track liveness for values that are in this set.
114 ///
115 BitVector ReservedRegisters;
115116
116117 private: // Intermediate data structures
117118 const MRegisterInfo *RegInfo;
137137 /// is an error to add the same register to the same set more than once.
138138 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
139139
140 /// removeLiveIn - Remove the specified register from the live in set.
141 ///
142 void removeLiveIn(unsigned Reg);
143
140144 // Iteration support for live in sets. These sets are kept in sorted
141145 // order by their register number.
142 typedef std::vector::const_iterator livein_iterator;
143 livein_iterator livein_begin() const { return LiveIns.begin(); }
144 livein_iterator livein_end() const { return LiveIns.end(); }
146 typedef std::vector::iterator livein_iterator;
147 typedef std::vector::const_iterator const_livein_iterator;
148 livein_iterator livein_begin() { return LiveIns.begin(); }
149 const_livein_iterator livein_begin() const { return LiveIns.begin(); }
150 livein_iterator livein_end() { return LiveIns.end(); }
151 const_livein_iterator livein_end() const { return LiveIns.end(); }
145152 bool livein_empty() const { return LiveIns.empty(); }
146153
147154 // Code Layout methods.
392392 /// the specific register or NULL if it is not found.
393393 MachineOperand *findRegisterUseOperand(unsigned Reg);
394394
395 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
396 /// the specific register or NULL if it is not found.
397 MachineOperand *findRegisterDefOperand(unsigned Reg);
398
395399 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
396400 ///
397401 void copyKillDeadInfo(const MachineInstr *MI);
283283 return false;
284284 }
285285
286 /// regsOverlap - Returns true if the two registers are equal or alias
287 /// each other. The registers may be virtual register.
288 bool regsOverlap(unsigned regA, unsigned regB) const {
289 if (regA == regB)
290 return true;
291
292 if (isVirtualRegister(regA) || isVirtualRegister(regB))
293 return false;
294 return areAliases(regA, regB);
295 }
296
286297 /// getCalleeSavedRegs - Return a null-terminated list of all of the
287298 /// callee saved registers on this target. The register should be in the
288299 /// order of desired callee-save stack frame offset. The first register is
293304 /// register classes to spill each callee saved register with. The order and
294305 /// length of this list match the getCalleeSaveRegs() list.
295306 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
307
308 /// getReservedRegs - Returns a bitset indexed by physical register number
309 /// indicating if a register is a special register that has particular uses and
310 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
311 /// register scavenger to determine what registers are free.
312 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
296313
297314 //===--------------------------------------------------------------------===//
298315 // Register Class Information
9797 // Set the MBB2IdxMap entry for this MBB.
9898 MBB2IdxMap[MBB->getNumber()] = MIIndex;
9999
100 // If this BB has any live ins, insert a dummy instruction at the
101 // beginning of the function that we will pretend "defines" the values. This
102 // is to make the interval analysis simpler by providing a number.
103 if (MBB->livein_begin() != MBB->livein_end()) {
104 unsigned FirstLiveIn = *MBB->livein_begin();
105
106 // Find a reg class that contains this live in.
107 const TargetRegisterClass *RC = 0;
108 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
109 RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
110 if ((*RCI)->contains(FirstLiveIn)) {
111 RC = *RCI;
112 break;
113 }
114
115 MachineInstr *OldFirstMI = MBB->begin();
116 mri_->copyRegToReg(*MBB, MBB->begin(),
117 FirstLiveIn, FirstLiveIn, RC);
118 assert(OldFirstMI != MBB->begin() &&
119 "copyRetToReg didn't insert anything!");
120 }
121
122100 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
123101 I != E; ++I) {
124102 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
160138 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
161139 (RegRep = rep(srcReg)) == rep(dstReg)) {
162140 // remove from def list
163 getOrCreateInterval(RegRep);
141 LiveInterval &RegInt = getOrCreateInterval(RegRep);
142 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
143 // If def of this move instruction is dead, remove its live range from
144 // the dstination register's live interval.
145 if (MO->isDead()) {
146 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
147 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
148 RegInt.removeRange(MLR->start, MoveIdx+1);
149 if (RegInt.empty())
150 removeInterval(RegRep);
151 }
164152 RemoveMachineInstrFromMaps(mii);
165153 mii = mbbi->erase(mii);
166154 ++numPeep;
184172 }
185173 }
186174
187
188175 for (iterator I = begin(), E = end(); I != E; ++I) {
189176 LiveInterval &LI = I->second;
190177 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
669656 }
670657 }
671658
659 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
660 LiveInterval &interval) {
661 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
662
663 // Look for kills, if it reaches a def before it's killed, then it shouldn't
664 // be considered a livein.
665 MachineBasicBlock::iterator mi = MBB->begin();
666 unsigned baseIndex = 0;
667 unsigned start = 0;
668 unsigned end = start;
669 while (mi != MBB->end()) {
670 if (lv_->KillsRegister(mi, interval.reg)) {
671 DOUT << " killed";
672 end = getUseIndex(baseIndex) + 1;
673 goto exit;
674 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
675 // Another instruction redefines the register before it is ever read.
676 // Then the register is essentially dead at the instruction that defines
677 // it. Hence its interval is:
678 // [defSlot(def), defSlot(def)+1)
679 DOUT << " dead";
680 end = getDefIndex(start) + 1;
681 goto exit;
682 }
683
684 baseIndex += InstrSlots::NUM;
685 ++mi;
686 }
687
688 exit:
689 assert(start < end && "did not find end of interval?");
690
691 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
692 interval.addRange(LR);
693 DOUT << " +" << LR << '\n';
694 }
695
672696 /// computeIntervals - computes the live intervals for virtual
673697 /// registers. for some ordering of the machine instructions [1,N] a
674698 /// live interval is an interval [i, j) where 1 <= i <= j < N for
687711 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
688712
689713 if (MBB->livein_begin() != MBB->livein_end()) {
690 // Process live-ins to this BB first.
691 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
714 // Create intervals for live-ins to this BB first.
715 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
692716 LE = MBB->livein_end(); LI != LE; ++LI) {
693 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
694 getOrCreateInterval(*LI), 0);
717 handleLiveInRegister(MBB, getOrCreateInterval(*LI));
695718 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
696 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
697 getOrCreateInterval(*AS), 0);
698 }
699 ++MI;
700 MIIndex += InstrSlots::NUM;
719 handleLiveInRegister(MBB, getOrCreateInterval(*AS));
720 }
701721 }
702722
703723 for (; MI != miEnd; ++MI) {
814834 return true;
815835 }
816836
817
818837 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
819838 /// which are the src/dst of the copy instruction CopyMI. This returns true
820839 /// if the copy was successfully coallesced away, or if it is never possible
824843 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
825844 unsigned SrcReg, unsigned DstReg) {
826845 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
827
846
828847 // Get representative registers.
829 SrcReg = rep(SrcReg);
830 DstReg = rep(DstReg);
848 unsigned repSrcReg = rep(SrcReg);
849 unsigned repDstReg = rep(DstReg);
831850
832851 // If they are already joined we continue.
833 if (SrcReg == DstReg) {
852 if (repSrcReg == repDstReg) {
834853 DOUT << "\tCopy already coallesced.\n";
835854 return true; // Not coallescable.
836855 }
837856
838857 // If they are both physical registers, we cannot join them.
839 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
840 MRegisterInfo::isPhysicalRegister(DstReg)) {
858 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
859 MRegisterInfo::isPhysicalRegister(repDstReg)) {
841860 DOUT << "\tCan not coallesce physregs.\n";
842861 return true; // Not coallescable.
843862 }
844863
845864 // We only join virtual registers with allocatable physical registers.
846 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
865 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
866 !allocatableRegs_[repSrcReg]) {
847867 DOUT << "\tSrc reg is unallocatable physreg.\n";
848868 return true; // Not coallescable.
849869 }
850 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
870 if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
871 !allocatableRegs_[repDstReg]) {
851872 DOUT << "\tDst reg is unallocatable physreg.\n";
852873 return true; // Not coallescable.
853874 }
854875
855876 // If they are not of the same register class, we cannot join them.
856 if (differingRegisterClasses(SrcReg, DstReg)) {
877 if (differingRegisterClasses(repSrcReg, repDstReg)) {
857878 DOUT << "\tSrc/Dest are different register classes.\n";
858879 return true; // Not coallescable.
859880 }
860881
861 LiveInterval &SrcInt = getInterval(SrcReg);
862 LiveInterval &DestInt = getInterval(DstReg);
863 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
882 LiveInterval &SrcInt = getInterval(repSrcReg);
883 LiveInterval &DestInt = getInterval(repDstReg);
884 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
864885 "Register mapping is horribly broken!");
865886
866887 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
867888 DOUT << " and "; DestInt.print(DOUT, mri_);
868889 DOUT << ": ";
869
890
891 // Check if it is necessary to propagate "isDead" property before intervals
892 // are joined.
893 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
894 bool isDead = mopd->isDead();
895 unsigned SrcStart = 0;
896 unsigned SrcEnd = 0;
897 if (isDead) {
898 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
899 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
900 SrcStart = SrcLR->start;
901 SrcEnd = SrcLR->end;
902 if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
903 isDead = false;
904 }
905
870906 // Okay, attempt to join these two intervals. On failure, this returns false.
871907 // Otherwise, if one of the intervals being joined is a physreg, this method
872908 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
873909 // been modified, so we can use this information below to update aliases.
874 if (!JoinIntervals(DestInt, SrcInt)) {
910 if (JoinIntervals(DestInt, SrcInt)) {
911 if (isDead) {
912 // Result of the copy is dead. Propagate this property.
913 if (SrcStart == 0) {
914 // Live-in to the function but dead. Remove it from MBB live-in set.
915 // JoinIntervals may end up swapping the two intervals.
916 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
917 LiveInInt.removeRange(SrcStart, SrcEnd);
918 MachineBasicBlock *MBB = CopyMI->getParent();
919 MBB->removeLiveIn(SrcReg);
920 } else {
921 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
922 if (SrcMI) {
923 // FIXME: SrcMI == NULL means the register is livein to a non-entry
924 // MBB. Remove the range from its live interval?
925 MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
926 if (mops)
927 // FIXME: mops == NULL means SrcMI defines a subregister?
928 mops->setIsDead();
929 }
930 }
931 }
932 } else {
875933 // Coallescing failed.
876934
877935 // If we can eliminate the copy without merging the live ranges, do so now.
883941 return false;
884942 }
885943
886 bool Swapped = SrcReg == DestInt.reg;
944 bool Swapped = repSrcReg == DestInt.reg;
887945 if (Swapped)
888 std::swap(SrcReg, DstReg);
889 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
946 std::swap(repSrcReg, repDstReg);
947 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
890948 "LiveInterval::join didn't work right!");
891949
892950 // If we're about to merge live ranges into a physical register live range,
893951 // we have to update any aliased register's live ranges to indicate that they
894952 // have clobbered values for this range.
895 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
896 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
953 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
954 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
897955 getInterval(*AS).MergeInClobberRanges(SrcInt);
898956 }
899957
903961 // If the intervals were swapped by Join, swap them back so that the register
904962 // mapping (in the r2i map) is correct.
905963 if (Swapped) SrcInt.swap(DestInt);
906 r2iMap_.erase(SrcReg);
907 r2rMap_[SrcReg] = DstReg;
964 removeInterval(repSrcReg);
965 r2rMap_[repSrcReg] = repDstReg;
908966
909967 // Finally, delete the copy instruction.
910968 RemoveMachineInstrFromMaps(CopyMI);
13881446 return !RegClass->contains(RegB);
13891447 }
13901448
1449 /// hasRegisterUse - Returns true if there is any use of the specific
1450 /// reg between indexes Start and End.
1451 bool
1452 LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
1453 for (unsigned Index = Start+InstrSlots::NUM; Index != End;
1454 Index += InstrSlots::NUM) {
1455 // Skip deleted instructions
1456 while (Index != End && !getInstructionFromIndex(Index))
1457 Index += InstrSlots::NUM;
1458 if (Index >= End) break;
1459
1460 MachineInstr *MI = getInstructionFromIndex(Index);
1461 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1462 MachineOperand &MO = MI->getOperand(i);
1463 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1464 mri_->regsOverlap(rep(MO.getReg()), Reg))
1465 return true;
1466 }
1467 }
1468
1469 return false;
1470 }
1471
13911472 LiveInterval LiveIntervals::createInterval(unsigned reg) {
13921473 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
13931474 HUGE_VALF : 0.0F;
7070 return VirtRegInfo[RegIdx];
7171 }
7272
73 /// registerOverlap - Returns true if register 1 is equal to register 2
74 /// or if register 1 is equal to any of alias of register 2.
75 static bool registerOverlap(unsigned Reg1, unsigned Reg2,
76 const MRegisterInfo *RegInfo) {
77 bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
78 bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
79 if (isVirt1 != isVirt2)
80 return false;
81 if (Reg1 == Reg2)
82 return true;
83 else if (isVirt1)
84 return false;
85 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
86 unsigned Alias = *AliasSet; ++AliasSet) {
87 if (Reg1 == Alias)
88 return true;
73 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
74 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
75 MachineOperand &MO = MI->getOperand(i);
76 if (MO.isReg() && MO.isKill()) {
77 if (RegInfo->regsOverlap(Reg, MO.getReg()))
78 return true;
79 }
8980 }
9081 return false;
9182 }
9283
93 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
94 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
95 MachineOperand &MO = MI->getOperand(i);
96 if (MO.isReg() && MO.isKill()) {
97 if (registerOverlap(Reg, MO.getReg(), RegInfo))
84 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
85 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
86 MachineOperand &MO = MI->getOperand(i);
87 if (MO.isReg() && MO.isDead())
88 if (RegInfo->regsOverlap(Reg, MO.getReg()))
9889 return true;
99 }
10090 }
10191 return false;
10292 }
10393
104 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
105 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
106 MachineOperand &MO = MI->getOperand(i);
107 if (MO.isReg() && MO.isDead())
108 if (registerOverlap(Reg, MO.getReg(), RegInfo))
109 return true;
110 }
111 return false;
112 }
113
11494 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
11595 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
11696 MachineOperand &MO = MI->getOperand(i);
11797 if (MO.isReg() && MO.isDef()) {
118 if (registerOverlap(Reg, MO.getReg(), RegInfo))
98 if (RegInfo->regsOverlap(Reg, MO.getReg()))
11999 return true;
120100 }
121101 }
239219 RegInfo = MF.getTarget().getRegisterInfo();
240220 assert(RegInfo && "Target doesn't have register information?");
241221
242 AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
222 ReservedRegisters = RegInfo->getReservedRegs(MF);
243223
244224 // PhysRegInfo - Keep track of which instruction was the last use of a
245225 // physical register. This is a purely local property, because all physical
266246 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
267247 MachineBasicBlock *MBB = *DFI;
268248
269 // Mark live-in registers as live-in.
270 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
249 // Mark live-in registers as live-in.
250 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
271251 EE = MBB->livein_end(); II != EE; ++II) {
272252 assert(MRegisterInfo::isPhysicalRegister(*II) &&
273253 "Cannot have a live-in virtual register!");
294274 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
295275 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
296276 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
297 AllocatablePhysicalRegisters[MO.getReg()]) {
277 !ReservedRegisters[MO.getReg()]) {
298278 HandlePhysRegUse(MO.getReg(), MI);
299279 }
300280 }
312292 // Defaults to dead
313293 VRInfo.Kills.push_back(MI);
314294 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
315 AllocatablePhysicalRegisters[MO.getReg()]) {
295 !ReservedRegisters[MO.getReg()]) {
316296 HandlePhysRegDef(MO.getReg(), MI);
317297 }
318298 }
117117 const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();
118118 if (livein_begin() != livein_end()) {
119119 OS << "Live Ins:";
120 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
120 for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
121121 OutputReg(OS, *I, MRI);
122122 OS << "\n";
123123 }
141141 OS << " " << *SI;
142142 OS << "\n";
143143 }
144 }
145
146 void MachineBasicBlock::removeLiveIn(unsigned Reg) {
147 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
148 assert(I != livein_end() && "Not a live in!");
149 LiveIns.erase(I);
144150 }
145151
146152 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
179179 return NULL;
180180 }
181181
182 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
183 /// the specific register or NULL if it is not found.
184 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
185 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
186 MachineOperand &MO = getOperand(i);
187 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
188 return &MO;
189 }
190 return NULL;
191 }
192
182193 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
183194 ///
184195 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
291291 }
292292
293293 // A brute force way of adding live-ins to every BB.
294 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
295 MBB != E; ++MBB) {
294 MachineFunction::iterator MBB = mf_->begin();
295 ++MBB; // Skip entry MBB.
296 for (MachineFunction::iterator E = mf_->end(); MBB != E; ++MBB) {
296297 unsigned StartIdx = li_->getMBBStartIdx(MBB->getNumber());
297298 for (IntervalPtrs::iterator i = fixed_.begin(), e = fixed_.end();
298299 i != e; ++i)
2727 #include "llvm/Target/TargetFrameInfo.h"
2828 #include "llvm/Target/TargetMachine.h"
2929 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/BitVector.h"
3031 #include "llvm/ADT/SmallVector.h"
3132 #include "llvm/ADT/STLExtras.h"
3233 #include
294295 0
295296 };
296297 return CalleeSavedRegClasses;
298 }
299
300 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
301 BitVector Reserved(getNumRegs());
302 Reserved.set(ARM::SP);
303 if (STI.isTargetDarwin() || hasFP(MF))
304 Reserved.set(FramePtr);
305 // Some targets reserve R9.
306 if (STI.isR9Reserved())
307 Reserved.set(ARM::R9);
308 // At PEI time, if LR is used, it will be spilled upon entry.
309 if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
310 Reserved.set(ARM::LR);
311 return Reserved;
297312 }
298313
299314 /// hasFP - Return true if the specified function should have a dedicated frame
6666
6767 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
6868
69 BitVector getReservedRegs(const MachineFunction &MF) const;
70
6971 bool hasFP(const MachineFunction &MF) const;
7072
7173 void eliminateCallFramePseudoInstr(MachineFunction &MF,
2727 #include "llvm/Target/TargetInstrInfo.h"
2828 #include "llvm/Support/CommandLine.h"
2929 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/BitVector.h"
3031 #include "llvm/ADT/STLExtras.h"
3132 #include
3233 using namespace llvm;
177178 return CalleeSavedRegClasses;
178179 }
179180
181 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
182 BitVector Reserved(getNumRegs());
183 Reserved.set(Alpha::R15);
184 Reserved.set(Alpha::R30);
185 Reserved.set(Alpha::R31);
186 return Reserved;
187 }
188
180189 //===----------------------------------------------------------------------===//
181190 // Stack Frame Processing methods
182191 //===----------------------------------------------------------------------===//
4848
4949 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5050
51 BitVector getReservedRegs(const MachineFunction &MF) const;
52
5153 bool hasFP(const MachineFunction &MF) const;
5254
5355 void eliminateCallFramePseudoInstr(MachineFunction &MF,
2727 #include "llvm/Target/TargetOptions.h"
2828 #include "llvm/Target/TargetInstrInfo.h"
2929 #include "llvm/Support/CommandLine.h"
30 #include "llvm/ADT/BitVector.h"
3031 #include "llvm/ADT/STLExtras.h"
3132 using namespace llvm;
3233
103104 &IA64::GRRegClass, 0
104105 };
105106 return CalleeSavedRegClasses;
107 }
108
109 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
110 BitVector Reserved(getNumRegs());
111 Reserved.set(IA64::r0);
112 Reserved.set(IA64::r1);
113 Reserved.set(IA64::r2);
114 Reserved.set(IA64::r5);
115 Reserved.set(IA64::r12);
116 Reserved.set(IA64::r13);
117 Reserved.set(IA64::r22);
118 Reserved.set(IA64::rp);
119 return Reserved;
106120 }
107121
108122 //===----------------------------------------------------------------------===//
4747
4848 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
4949
50 BitVector getReservedRegs(const MachineFunction &MF) const;
51
5052 bool hasFP(const MachineFunction &MF) const;
5153
5254 void eliminateCallFramePseudoInstr(MachineFunction &MF,
4040 const TargetRegisterClass *RC = *I;
4141 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4242 E = RC->allocation_order_end(MF); I != E; ++I)
43 Allocatable[*I] = true;
43 Allocatable.set(*I);
4444 }
4545 return Allocatable;
4646 }
3333 #include "llvm/Support/CommandLine.h"
3434 #include "llvm/Support/Debug.h"
3535 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/BitVector.h"
3637 #include "llvm/ADT/STLExtras.h"
3738 #include
3839 using namespace llvm;
337338 Darwin32_CalleeSavedRegClasses;
338339 }
339340
341 // needsFP - Return true if the specified function should have a dedicated frame
342 // pointer register. This is true if the function has variable sized allocas or
343 // if frame pointer elimination is disabled.
344 //
345 static bool needsFP(const MachineFunction &MF) {
346 const MachineFrameInfo *MFI = MF.getFrameInfo();
347 return NoFramePointerElim || MFI->hasVarSizedObjects();
348 }
349
350 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
351 BitVector Reserved(getNumRegs());
352 Reserved.set(PPC::R0);
353 Reserved.set(PPC::R1);
354 Reserved.set(PPC::LR);
355 // In Linux, r2 is reserved for the OS.
356 if (!Subtarget.isDarwin())
357 Reserved.set(PPC::R2);
358 // On PPC64, r13 is the thread pointer. Never allocate this register.
359 // Note that this is overconservative, as it also prevents allocation of
360 // R31 when the FP is not needed.
361 if (Subtarget.isPPC64()) {
362 Reserved.set(PPC::R13);
363 Reserved.set(PPC::R31);
364 }
365 if (needsFP(MF))
366 Reserved.set(PPC::R31);
367 return Reserved;
368 }
369
340370 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
341371 /// copy instructions, turning them into load/store instructions.
342372 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
396426 //===----------------------------------------------------------------------===//
397427 // Stack Frame Processing methods
398428 //===----------------------------------------------------------------------===//
399
400 // needsFP - Return true if the specified function should have a dedicated frame
401 // pointer register. This is true if the function has variable sized allocas or
402 // if frame pointer elimination is disabled.
403 //
404 static bool needsFP(const MachineFunction &MF) {
405 const MachineFrameInfo *MFI = MF.getFrameInfo();
406 return NoFramePointerElim || MFI->hasVarSizedObjects();
407 }
408429
409430 // hasFP - Return true if the specified function actually has a dedicated frame
410431 // pointer register. This is true if the function needs a frame pointer and has
5757
5858 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5959
60 BitVector getReservedRegs(const MachineFunction &MF) const;
61
6062 /// targetHandlesStackFrameRounding - Returns true if the target is
6163 /// responsible for rounding up the stack frame (probably at emitPrologue
6264 /// time).
1919 #include "llvm/CodeGen/MachineLocation.h"
2020 #include "llvm/Target/TargetInstrInfo.h"
2121 #include "llvm/Type.h"
22 #include "llvm/ADT/BitVector.h"
2223 #include "llvm/ADT/STLExtras.h"
2324 using namespace llvm;
2425
115116 return CalleeSavedRegs;
116117 }
117118
119 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
120 BitVector Reserved(getNumRegs());
121 Reserved.set(SP::G2);
122 Reserved.set(SP::G3);
123 Reserved.set(SP::G4);
124 Reserved.set(SP::O6);
125 Reserved.set(SP::I6);
126 Reserved.set(SP::I7);
127 Reserved.set(SP::G0);
128 Reserved.set(SP::G5);
129 Reserved.set(SP::G6);
130 Reserved.set(SP::G7);
131 return Reserved;
132 }
133
134
118135 const TargetRegisterClass* const*
119136 SparcRegisterInfo::getCalleeSavedRegClasses() const {
120137 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
5151
5252 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5353
54 BitVector getReservedRegs(const MachineFunction &MF) const;
55
5456 bool hasFP(const MachineFunction &MF) const;
5557
5658 void eliminateCallFramePseudoInstr(MachineFunction &MF,
3030 #include "llvm/Target/TargetMachine.h"
3131 #include "llvm/Target/TargetOptions.h"
3232 #include "llvm/Support/CommandLine.h"
33 #include "llvm/ADT/BitVector.h"
3334 #include "llvm/ADT/STLExtras.h"
3435 using namespace llvm;
3536
882883 return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
883884 }
884885
886 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
887 BitVector Reserved(getNumRegs());
888 Reserved.set(X86::RSP);
889 Reserved.set(X86::ESP);
890 Reserved.set(X86::SP);
891 Reserved.set(X86::SPL);
892 if (hasFP(MF)) {
893 Reserved.set(X86::RBP);
894 Reserved.set(X86::EBP);
895 Reserved.set(X86::BP);
896 Reserved.set(X86::BPL);
897 }
898 return Reserved;
899 }
900
885901 //===----------------------------------------------------------------------===//
886902 // Stack Frame Processing methods
887903 //===----------------------------------------------------------------------===//
7777 /// length of this list match the getCalleeSavedRegs() list.
7878 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
7979
80 /// getReservedRegs - Returns a bitset indexed by physical register number
81 /// indicating if a register is a special register that has particular uses and
82 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
83 /// register scavenger to determine what registers are free.
84 BitVector getReservedRegs(const MachineFunction &MF) const;
85
8086 bool hasFP(const MachineFunction &MF) const;
8187
8288 void eliminateCallFramePseudoInstr(MachineFunction &MF,