llvm.org GIT mirror llvm / b3325ff
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319434 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 2 years ago
91 changed file(s) with 1917 addition(s) and 304 deletion(s). Raw diff Collapse all Expand all
6868
6969 #define DEBUG_TYPE "ppc-codegen"
7070
71 STATISTIC(NumSextSetcc,
72 "Number of (sext(setcc)) nodes expanded into GPR sequence.");
73 STATISTIC(NumZextSetcc,
74 "Number of (zext(setcc)) nodes expanded into GPR sequence.");
75 STATISTIC(SignExtensionsAdded,
76 "Number of sign extensions for compare inputs added.");
77 STATISTIC(ZeroExtensionsAdded,
78 "Number of zero extensions for compare inputs added.");
79 STATISTIC(NumLogicOpsOnComparison,
80 "Number of logical ops on i1 values calculated in GPR.");
81 STATISTIC(OmittedForNonExtendUses,
82 "Number of compares not eliminated as they have non-extending uses.");
83
7184 // FIXME: Remove this once the bug has been fixed!
7285 cl::opt ANDIGlueBug("expose-ppc-andi-glue-bug",
7386 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
87100 cl::desc("Enable static hinting of branches on ppc"),
88101 cl::Hidden);
89102
103 enum ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,
104 ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,
105 ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 };
106
107 static cl::opt CmpInGPR(
108 "ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_None),
109 cl::desc("Specify the types of comparisons to emit GPR-only code for."),
110 cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."),
111 clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."),
112 clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."),
113 clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."),
114 clEnumValN(ICGPR_NonExtIn, "nonextin",
115 "Only comparisons where inputs don't need [sz]ext."),
116 clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."),
117 clEnumValN(ICGPR_ZextI32, "zexti32",
118 "Only i32 comparisons with zext result."),
119 clEnumValN(ICGPR_ZextI64, "zexti64",
120 "Only i64 comparisons with zext result."),
121 clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."),
122 clEnumValN(ICGPR_SextI32, "sexti32",
123 "Only i32 comparisons with sext result."),
124 clEnumValN(ICGPR_SextI64, "sexti64",
125 "Only i64 comparisons with sext result.")));
90126 namespace {
91127
92128 //===--------------------------------------------------------------------===//
160196
161197 bool tryBitfieldInsert(SDNode *N);
162198 bool tryBitPermutation(SDNode *N);
199 bool tryIntCompareInGPR(SDNode *N);
163200
164201 /// SelectCC - Select a comparison of the specified values with the
165202 /// specified condition code, returning the CR# of the expression.
20632100 }
20642101 };
20652102
2103 class IntegerCompareEliminator {
2104 SelectionDAG *CurDAG;
2105 PPCDAGToDAGISel *S;
2106 // Conversion type for interpreting results of a 32-bit instruction as
2107 // a 64-bit value or vice versa.
2108 enum ExtOrTruncConversion { Ext, Trunc };
2109
2110 // Modifiers to guide how an ISD::SETCC node's result is to be computed
2111 // in a GPR.
2112 // ZExtOrig - use the original condition code, zero-extend value
2113 // ZExtInvert - invert the condition code, zero-extend value
2114 // SExtOrig - use the original condition code, sign-extend value
2115 // SExtInvert - invert the condition code, sign-extend value
2116 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
2117
2118 // Comparisons against zero to emit GPR code sequences for. Each of these
2119 // sequences may need to be emitted for two or more equivalent patterns.
2120 // For example (a >= 0) == (a > -1). The direction of the comparison ()
2121 // matters as well as the extension type: sext (-1/0), zext (1/0).
2122 // GEZExt - (zext (LHS >= 0))
2123 // GESExt - (sext (LHS >= 0))
2124 // LEZExt - (zext (LHS <= 0))
2125 // LESExt - (sext (LHS <= 0))
2126 enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
2127
2128 SDNode *tryEXTEND(SDNode *N);
2129 SDNode *tryLogicOpOfCompares(SDNode *N);
2130 SDValue computeLogicOpInGPR(SDValue LogicOp);
2131 SDValue signExtendInputIfNeeded(SDValue Input);
2132 SDValue zeroExtendInputIfNeeded(SDValue Input);
2133 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
2134 SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2135 ZeroCompare CmpTy);
2136 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2137 int64_t RHSValue, SDLoc dl);
2138 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2139 int64_t RHSValue, SDLoc dl);
2140 SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2141 int64_t RHSValue, SDLoc dl);
2142 SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2143 int64_t RHSValue, SDLoc dl);
2144 SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
2145
2146 public:
2147 IntegerCompareEliminator(SelectionDAG *DAG,
2148 PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) {
2149 assert(CurDAG->getTargetLoweringInfo()
2150 .getPointerTy(CurDAG->getDataLayout()).getSizeInBits() == 64 &&
2151 "Only expecting to use this on 64 bit targets.");
2152 }
2153 SDNode *Select(SDNode *N) {
2154 if (CmpInGPR == ICGPR_None)
2155 return nullptr;
2156 switch (N->getOpcode()) {
2157 default: break;
2158 case ISD::ZERO_EXTEND:
2159 if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 ||
2160 CmpInGPR == ICGPR_SextI64)
2161 return nullptr;
2162 case ISD::SIGN_EXTEND:
2163 if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 ||
2164 CmpInGPR == ICGPR_ZextI64)
2165 return nullptr;
2166 return tryEXTEND(N);
2167 case ISD::AND:
2168 case ISD::OR:
2169 case ISD::XOR:
2170 return tryLogicOpOfCompares(N);
2171 }
2172 return nullptr;
2173 }
2174 };
2175
2176 static bool isLogicOp(unsigned Opc) {
2177 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2178 }
2179 // The obvious case for wanting to keep the value in a GPR. Namely, the
2180 // result of the comparison is actually needed in a GPR.
2181 SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) {
2182 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2183 N->getOpcode() == ISD::SIGN_EXTEND) &&
2184 "Expecting a zero/sign extend node!");
2185 SDValue WideRes;
2186 // If we are zero-extending the result of a logical operation on i1
2187 // values, we can keep the values in GPRs.
2188 if (isLogicOp(N->getOperand(0).getOpcode()) &&
2189 N->getOperand(0).getValueType() == MVT::i1 &&
2190 N->getOpcode() == ISD::ZERO_EXTEND)
2191 WideRes = computeLogicOpInGPR(N->getOperand(0));
2192 else if (N->getOperand(0).getOpcode() != ISD::SETCC)
2193 return nullptr;
2194 else
2195 WideRes =
2196 getSETCCInGPR(N->getOperand(0),
2197 N->getOpcode() == ISD::SIGN_EXTEND ?
2198 SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig);
2199
2200 if (!WideRes)
2201 return nullptr;
2202
2203 SDLoc dl(N);
2204 bool Input32Bit = WideRes.getValueType() == MVT::i32;
2205 bool Output32Bit = N->getValueType(0) == MVT::i32;
2206
2207 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2208 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2209
2210 SDValue ConvOp = WideRes;
2211 if (Input32Bit != Output32Bit)
2212 ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext :
2213 ExtOrTruncConversion::Trunc);
2214 return ConvOp.getNode();
2215 }
2216
2217 // Attempt to perform logical operations on the results of comparisons while
2218 // keeping the values in GPRs. Without doing so, these would end up being
2219 // lowered to CR-logical operations which suffer from significant latency and
2220 // low ILP.
2221 SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) {
2222 if (N->getValueType(0) != MVT::i1)
2223 return nullptr;
2224 assert(isLogicOp(N->getOpcode()) &&
2225 "Expected a logic operation on setcc results.");
2226 SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0));
2227 if (!LoweredLogical)
2228 return nullptr;
2229
2230 SDLoc dl(N);
2231 bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2232 unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt;
2233 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2234 SDValue LHS = LoweredLogical.getOperand(0);
2235 SDValue RHS = LoweredLogical.getOperand(1);
2236 SDValue WideOp;
2237 SDValue OpToConvToRecForm;
2238
2239 // Look through any 32-bit to 64-bit implicit extend nodes to find the
2240 // opcode that is input to the XORI.
2241 if (IsBitwiseNegate &&
2242 LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2243 OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1);
2244 else if (IsBitwiseNegate)
2245 // If the input to the XORI isn't an extension, that's what we're after.
2246 OpToConvToRecForm = LoweredLogical.getOperand(0);
2247 else
2248 // If this is not an XORI, it is a reg-reg logical op and we can convert
2249 // it to record-form.
2250 OpToConvToRecForm = LoweredLogical;
2251
2252 // Get the record-form version of the node we're looking to use to get the
2253 // CR result from.
2254 uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
2255 int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2256
2257 // Convert the right node to record-form. This is either the logical we're
2258 // looking at or it is the input node to the negation (if we're looking at
2259 // a bitwise negation).
2260 if (NewOpc != -1 && IsBitwiseNegate) {
2261 // The input to the XORI has a record-form. Use it.
2262 assert(LoweredLogical.getConstantOperandVal(1) == 1 &&
2263 "Expected a PPC::XORI8 only for bitwise negation.");
2264 // Emit the record-form instruction.
2265 std::vector Ops;
2266 for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++)
2267 Ops.push_back(OpToConvToRecForm.getOperand(i));
2268
2269 WideOp =
2270 SDValue(CurDAG->getMachineNode(NewOpc, dl,
2271 OpToConvToRecForm.getValueType(),
2272 MVT::Glue, Ops), 0);
2273 } else {
2274 assert((NewOpc != -1 || !IsBitwiseNegate) &&
2275 "No record form available for AND8/OR8/XOR8?");
2276 WideOp =
2277 SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
2278 MVT::i64, MVT::Glue, LHS, RHS), 0);
2279 }
2280
2281 // Select this node to a single bit from CR0 set by the record-form node
2282 // just created. For bitwise negation, use the EQ bit which is the equivalent
2283 // of negating the result (i.e. it is a bit set when the result of the
2284 // operation is zero).
2285 SDValue SRIdxVal =
2286 CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32);
2287 SDValue CRBit =
2288 SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
2289 MVT::i1, CR0Reg, SRIdxVal,
2290 WideOp.getValue(1)), 0);
2291 return CRBit.getNode();
2292 }
2293
2294 // Lower a logical operation on i1 values into a GPR sequence if possible.
2295 // The result can be kept in a GPR if requested.
2296 // Three types of inputs can be handled:
2297 // - SETCC
2298 // - TRUNCATE
2299 // - Logical operation (AND/OR/XOR)
2300 // There is also a special case that is handled (namely a complement operation
2301 // achieved with xor %a, -1).
2302 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) {
2303 assert(isLogicOp(LogicOp.getOpcode()) &&
2304 "Can only handle logic operations here.");
2305 assert(LogicOp.getValueType() == MVT::i1 &&
2306 "Can only handle logic operations on i1 values here.");
2307 SDLoc dl(LogicOp);
2308 SDValue LHS, RHS;
2309
2310 // Special case: xor %a, -1
2311 bool IsBitwiseNegation = isBitwiseNot(LogicOp);
2312
2313 // Produces a GPR sequence for each operand of the binary logic operation.
2314 // For SETCC, it produces the respective comparison, for TRUNCATE it truncates
2315 // the value in a GPR and for logic operations, it will recursively produce
2316 // a GPR sequence for the operation.
2317 auto getLogicOperand = [&] (SDValue Operand) -> SDValue {
2318 unsigned OperandOpcode = Operand.getOpcode();
2319 if (OperandOpcode == ISD::SETCC)
2320 return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig);
2321 else if (OperandOpcode == ISD::TRUNCATE) {
2322 SDValue InputOp = Operand.getOperand(0);
2323 EVT InVT = InputOp.getValueType();
2324 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2325 PPC::RLDICL, dl, InVT, InputOp,
2326 S->getI64Imm(0, dl),
2327 S->getI64Imm(63, dl)), 0);
2328 } else if (isLogicOp(OperandOpcode))
2329 return computeLogicOpInGPR(Operand);
2330 return SDValue();
2331 };
2332 LHS = getLogicOperand(LogicOp.getOperand(0));
2333 RHS = getLogicOperand(LogicOp.getOperand(1));
2334
2335 // If a GPR sequence can't be produced for the LHS we can't proceed.
2336 // Not producing a GPR sequence for the RHS is only a problem if this isn't
2337 // a bitwise negation operation.
2338 if (!LHS || (!RHS && !IsBitwiseNegation))
2339 return SDValue();
2340
2341 NumLogicOpsOnComparison++;
2342
2343 // We will use the inputs as 64-bit values.
2344 if (LHS.getValueType() == MVT::i32)
2345 LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext);
2346 if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32)
2347 RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext);
2348
2349 unsigned NewOpc;
2350 switch (LogicOp.getOpcode()) {
2351 default: llvm_unreachable("Unknown logic operation.");
2352 case ISD::AND: NewOpc = PPC::AND8; break;
2353 case ISD::OR: NewOpc = PPC::OR8; break;
2354 case ISD::XOR: NewOpc = PPC::XOR8; break;
2355 }
2356
2357 if (IsBitwiseNegation) {
2358 RHS = S->getI64Imm(1, dl);
2359 NewOpc = PPC::XORI8;
2360 }
2361
2362 return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0);
2363
2364 }
2365
2366 /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
2367 /// Otherwise just reinterpret it as a 64-bit value.
2368 /// Useful when emitting comparison code for 32-bit values without using
2369 /// the compare instruction (which only considers the lower 32-bits).
2370 SDValue IntegerCompareEliminator::signExtendInputIfNeeded(SDValue Input) {
2371 assert(Input.getValueType() == MVT::i32 &&
2372 "Can only sign-extend 32-bit values here.");
2373 unsigned Opc = Input.getOpcode();
2374
2375 // The value was sign extended and then truncated to 32-bits. No need to
2376 // sign extend it again.
2377 if (Opc == ISD::TRUNCATE &&
2378 (Input.getOperand(0).getOpcode() == ISD::AssertSext ||
2379 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
2380 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2381
2382 LoadSDNode *InputLoad = dyn_cast(Input);
2383 // The input is a sign-extending load. All ppc sign-extending loads
2384 // sign-extend to the full 64-bits.
2385 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2386 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2387
2388 ConstantSDNode *InputConst = dyn_cast(Input);
2389 // We don't sign-extend constants.
2390 if (InputConst)
2391 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2392
2393 SDLoc dl(Input);
2394 SignExtensionsAdded++;
2395 return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl,
2396 MVT::i64, Input), 0);
2397 }
2398
2399 /// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
2400 /// Otherwise just reinterpret it as a 64-bit value.
2401 /// Useful when emitting comparison code for 32-bit values without using
2402 /// the compare instruction (which only considers the lower 32-bits).
2403 SDValue IntegerCompareEliminator::zeroExtendInputIfNeeded(SDValue Input) {
2404 assert(Input.getValueType() == MVT::i32 &&
2405 "Can only zero-extend 32-bit values here.");
2406 unsigned Opc = Input.getOpcode();
2407
2408 // The only condition under which we can omit the actual extend instruction:
2409 // - The value is a positive constant
2410 // - The value comes from a load that isn't a sign-extending load
2411 // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
2412 bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
2413 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2414 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
2415 if (IsTruncateOfZExt)
2416 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2417
2418 ConstantSDNode *InputConst = dyn_cast(Input);
2419 if (InputConst && InputConst->getSExtValue() >= 0)
2420 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2421
2422 LoadSDNode *InputLoad = dyn_cast(Input);
2423 // The input is a load that doesn't sign-extend (it will be zero-extended).
2424 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
2425 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
2426
2427 // None of the above, need to zero-extend.
2428 SDLoc dl(Input);
2429 ZeroExtensionsAdded++;
2430 return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input,
2431 S->getI64Imm(0, dl),
2432 S->getI64Imm(32, dl)), 0);
2433 }
2434
2435 // Handle a 32-bit value in a 64-bit register and vice-versa. These are of
2436 // course not actual zero/sign extensions that will generate machine code,
2437 // they're just a way to reinterpret a 32 bit value in a register as a
2438 // 64 bit value and vice-versa.
2439 SDValue IntegerCompareEliminator::addExtOrTrunc(SDValue NatWidthRes,
2440 ExtOrTruncConversion Conv) {
2441 SDLoc dl(NatWidthRes);
2442
2443 // For reinterpreting 32-bit values as 64 bit values, we generate
2444 // INSERT_SUBREG IMPLICIT_DEF:i64, , TargetConstant:i32<1>
2445 if (Conv == ExtOrTruncConversion::Ext) {
2446 SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
2447 SDValue SubRegIdx =
2448 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2449 return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
2450 ImDef, NatWidthRes, SubRegIdx), 0);
2451 }
2452
2453 assert(Conv == ExtOrTruncConversion::Trunc &&
2454 "Unknown convertion between 32 and 64 bit values.");
2455 // For reinterpreting 64-bit values as 32-bit values, we just need to
2456 // EXTRACT_SUBREG (i.e. extract the low word).
2457 SDValue SubRegIdx =
2458 CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
2459 return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
2460 NatWidthRes, SubRegIdx), 0);
2461 }
2462
2463 // Produce a GPR sequence for compound comparisons (<=, >=) against zero.
2464 // Handle both zero-extensions and sign-extensions.
2465 SDValue
2466 IntegerCompareEliminator::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2467 ZeroCompare CmpTy) {
2468 EVT InVT = LHS.getValueType();
2469 bool Is32Bit = InVT == MVT::i32;
2470 SDValue ToExtend;
2471
2472 // Produce the value that needs to be either zero or sign extended.
2473 switch (CmpTy) {
2474 case ZeroCompare::GEZExt:
2475 case ZeroCompare::GESExt:
2476 ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
2477 dl, InVT, LHS, LHS), 0);
2478 break;
2479 case ZeroCompare::LEZExt:
2480 case ZeroCompare::LESExt: {
2481 if (Is32Bit) {
2482 // Upper 32 bits cannot be undefined for this sequence.
2483 LHS = signExtendInputIfNeeded(LHS);
2484 SDValue Neg =
2485 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2486 ToExtend =
2487 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2488 Neg, S->getI64Imm(1, dl),
2489 S->getI64Imm(63, dl)), 0);
2490 } else {
2491 SDValue Addi =
2492 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2493 S->getI64Imm(~0ULL, dl)), 0);
2494 ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2495 Addi, LHS), 0);
2496 }
2497 break;
2498 }
2499 }
2500
2501 // For 64-bit sequences, the extensions are the same for the GE/LE cases.
2502 if (!Is32Bit &&
2503 (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
2504 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2505 ToExtend, S->getI64Imm(1, dl),
2506 S->getI64Imm(63, dl)), 0);
2507 if (!Is32Bit &&
2508 (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
2509 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
2510 S->getI64Imm(63, dl)), 0);
2511
2512 assert(Is32Bit && "Should have handled the 32-bit sequences above.");
2513 // For 32-bit sequences, the extensions differ between GE/LE cases.
2514 switch (CmpTy) {
2515 case ZeroCompare::GEZExt: {
2516 SDValue ShiftOps[] = { ToExtend, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2517 S->getI32Imm(31, dl) };
2518 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2519 ShiftOps), 0);
2520 }
2521 case ZeroCompare::GESExt:
2522 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
2523 S->getI32Imm(31, dl)), 0);
2524 case ZeroCompare::LEZExt:
2525 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend,
2526 S->getI32Imm(1, dl)), 0);
2527 case ZeroCompare::LESExt:
2528 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend,
2529 S->getI32Imm(-1, dl)), 0);
2530 }
2531
2532 // The above case covers all the enumerators so it can't have a default clause
2533 // to avoid compiler warnings.
2534 llvm_unreachable("Unknown zero-comparison type.");
2535 }
2536
2537 /// Produces a zero-extended result of comparing two 32-bit values according to
2538 /// the passed condition code.
2539 SDValue
2540 IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
2541 ISD::CondCode CC,
2542 int64_t RHSValue, SDLoc dl) {
2543 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2544 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Sext)
2545 return SDValue();
2546 bool IsRHSZero = RHSValue == 0;
2547 bool IsRHSOne = RHSValue == 1;
2548 bool IsRHSNegOne = RHSValue == -1LL;
2549 switch (CC) {
2550 default: return SDValue();
2551 case ISD::SETEQ: {
2552 // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
2553 // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
2554 SDValue Xor = IsRHSZero ? LHS :
2555 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2556 SDValue Clz =
2557 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2558 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2559 S->getI32Imm(31, dl) };
2560 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2561 ShiftOps), 0);
2562 }
2563 case ISD::SETNE: {
2564 // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1)
2565 // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1)
2566 SDValue Xor = IsRHSZero ? LHS :
2567 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2568 SDValue Clz =
2569 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2570 SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl),
2571 S->getI32Imm(31, dl) };
2572 SDValue Shift =
2573 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2574 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2575 S->getI32Imm(1, dl)), 0);
2576 }
2577 case ISD::SETGE: {
2578 // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
2579 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
2580 if(IsRHSZero)
2581 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2582
2583 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2584 // by swapping inputs and falling through.
2585 std::swap(LHS, RHS);
2586 ConstantSDNode *RHSConst = dyn_cast(RHS);
2587 IsRHSZero = RHSConst && RHSConst->isNullValue();
2588 LLVM_FALLTHROUGH;
2589 }
2590 case ISD::SETLE: {
2591 if (CmpInGPR == ICGPR_NonExtIn)
2592 return SDValue();
2593 // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
2594 // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
2595 if(IsRHSZero) {
2596 if (CmpInGPR == ICGPR_NonExtIn)
2597 return SDValue();
2598 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2599 }
2600
2601 // The upper 32-bits of the register can't be undefined for this sequence.
2602 LHS = signExtendInputIfNeeded(LHS);
2603 RHS = signExtendInputIfNeeded(RHS);
2604 SDValue Sub =
2605 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2606 SDValue Shift =
2607 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub,
2608 S->getI64Imm(1, dl), S->getI64Imm(63, dl)),
2609 0);
2610 return
2611 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl,
2612 MVT::i64, Shift, S->getI32Imm(1, dl)), 0);
2613 }
2614 case ISD::SETGT: {
2615 // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63)
2616 // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31)
2617 // (zext (setcc %a, 0, setgt)) -> (lshr (- %a), 63)
2618 // Handle SETLT -1 (which is equivalent to SETGE 0).
2619 if (IsRHSNegOne)
2620 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2621
2622 if (IsRHSZero) {
2623 if (CmpInGPR == ICGPR_NonExtIn)
2624 return SDValue();
2625 // The upper 32-bits of the register can't be undefined for this sequence.
2626 LHS = signExtendInputIfNeeded(LHS);
2627 RHS = signExtendInputIfNeeded(RHS);
2628 SDValue Neg =
2629 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2630 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2631 Neg, S->getI32Imm(1, dl), S->getI32Imm(63, dl)), 0);
2632 }
2633 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
2634 // (%b < %a) by swapping inputs and falling through.
2635 std::swap(LHS, RHS);
2636 ConstantSDNode *RHSConst = dyn_cast(RHS);
2637 IsRHSZero = RHSConst && RHSConst->isNullValue();
2638 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2639 LLVM_FALLTHROUGH;
2640 }
2641 case ISD::SETLT: {
2642 // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
2643 // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1)
2644 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31)
2645 // Handle SETLT 1 (which is equivalent to SETLE 0).
2646 if (IsRHSOne) {
2647 if (CmpInGPR == ICGPR_NonExtIn)
2648 return SDValue();
2649 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2650 }
2651
2652 if (IsRHSZero) {
2653 SDValue ShiftOps[] = { LHS, S->getI32Imm(1, dl), S->getI32Imm(31, dl),
2654 S->getI32Imm(31, dl) };
2655 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2656 ShiftOps), 0);
2657 }
2658
2659 if (CmpInGPR == ICGPR_NonExtIn)
2660 return SDValue();
2661 // The upper 32-bits of the register can't be undefined for this sequence.
2662 LHS = signExtendInputIfNeeded(LHS);
2663 RHS = signExtendInputIfNeeded(RHS);
2664 SDValue SUBFNode =
2665 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2666 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2667 SUBFNode, S->getI64Imm(1, dl),
2668 S->getI64Imm(63, dl)), 0);
2669 }
2670 case ISD::SETUGE:
2671 // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
2672 // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
2673 std::swap(LHS, RHS);
2674 LLVM_FALLTHROUGH;
2675 case ISD::SETULE: {
2676 if (CmpInGPR == ICGPR_NonExtIn)
2677 return SDValue();
2678 // The upper 32-bits of the register can't be undefined for this sequence.
2679 LHS = zeroExtendInputIfNeeded(LHS);
2680 RHS = zeroExtendInputIfNeeded(RHS);
2681 SDValue Subtract =
2682 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2683 SDValue SrdiNode =
2684 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2685 Subtract, S->getI64Imm(1, dl),
2686 S->getI64Imm(63, dl)), 0);
2687 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
2688 S->getI32Imm(1, dl)), 0);
2689 }
2690 case ISD::SETUGT:
2691 // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
2692 // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
2693 std::swap(LHS, RHS);
2694 LLVM_FALLTHROUGH;
2695 case ISD::SETULT: {
2696 if (CmpInGPR == ICGPR_NonExtIn)
2697 return SDValue();
2698 // The upper 32-bits of the register can't be undefined for this sequence.
2699 LHS = zeroExtendInputIfNeeded(LHS);
2700 RHS = zeroExtendInputIfNeeded(RHS);
2701 SDValue Subtract =
2702 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2703 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2704 Subtract, S->getI64Imm(1, dl),
2705 S->getI64Imm(63, dl)), 0);
2706 }
2707 }
2708 }
2709
2710 /// Produces a sign-extended result of comparing two 32-bit values according to
2711 /// the passed condition code.
2712 SDValue
2713 IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
2714 ISD::CondCode CC,
2715 int64_t RHSValue, SDLoc dl) {
2716 if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 ||
2717 CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Zext)
2718 return SDValue();
2719 bool IsRHSZero = RHSValue == 0;
2720 bool IsRHSOne = RHSValue == 1;
2721 bool IsRHSNegOne = RHSValue == -1LL;
2722
2723 switch (CC) {
2724 default: return SDValue();
2725 case ISD::SETEQ: {
2726 // (sext (setcc %a, %b, seteq)) ->
2727 // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
2728 // (sext (setcc %a, 0, seteq)) ->
2729 // (ashr (shl (ctlz %a), 58), 63)
2730 SDValue CountInput = IsRHSZero ? LHS :
2731 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2732 SDValue Cntlzw =
2733 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
2734 SDValue SHLOps[] = { Cntlzw, S->getI32Imm(27, dl),
2735 S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2736 SDValue Slwi =
2737 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0);
2738 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0);
2739 }
2740 case ISD::SETNE: {
2741 // Bitwise xor the operands, count leading zeros, shift right by 5 bits and
2742 // flip the bit, finally take 2's complement.
2743 // (sext (setcc %a, %b, setne)) ->
2744 // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1))
2745 // Same as above, but the first xor is not needed.
2746 // (sext (setcc %a, 0, setne)) ->
2747 // (neg (xor (lshr (ctlz %a), 5), 1))
2748 SDValue Xor = IsRHSZero ? LHS :
2749 SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
2750 SDValue Clz =
2751 SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
2752 SDValue ShiftOps[] =
2753 { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), S->getI32Imm(31, dl) };
2754 SDValue Shift =
2755 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
2756 SDValue Xori =
2757 SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
2758 S->getI32Imm(1, dl)), 0);
2759 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
2760 }
2761 case ISD::SETGE: {
2762 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
2763 // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
2764 if (IsRHSZero)
2765 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2766
2767 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2768 // by swapping inputs and falling through.
2769 std::swap(LHS, RHS);
2770 ConstantSDNode *RHSConst = dyn_cast(RHS);
2771 IsRHSZero = RHSConst && RHSConst->isNullValue();
2772 LLVM_FALLTHROUGH;
2773 }
2774 case ISD::SETLE: {
2775 if (CmpInGPR == ICGPR_NonExtIn)
2776 return SDValue();
2777 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
2778 // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
2779 if (IsRHSZero)
2780 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
2781
2782 // The upper 32-bits of the register can't be undefined for this sequence.
2783 LHS = signExtendInputIfNeeded(LHS);
2784 RHS = signExtendInputIfNeeded(RHS);
2785 SDValue SUBFNode =
2786 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue,
2787 LHS, RHS), 0);
2788 SDValue Srdi =
2789 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2790 SUBFNode, S->getI64Imm(1, dl),
2791 S->getI64Imm(63, dl)), 0);
2792 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi,
2793 S->getI32Imm(-1, dl)), 0);
2794 }
2795 case ISD::SETGT: {
2796 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63)
2797 // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31)
2798 // (sext (setcc %a, 0, setgt)) -> (ashr (- %a), 63)
2799 if (IsRHSNegOne)
2800 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2801 if (IsRHSZero) {
2802 if (CmpInGPR == ICGPR_NonExtIn)
2803 return SDValue();
2804 // The upper 32-bits of the register can't be undefined for this sequence.
2805 LHS = signExtendInputIfNeeded(LHS);
2806 RHS = signExtendInputIfNeeded(RHS);
2807 SDValue Neg =
2808 SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0);
2809 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg,
2810 S->getI64Imm(63, dl)), 0);
2811 }
2812 // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as
2813 // (%b < %a) by swapping inputs and falling through.
2814 std::swap(LHS, RHS);
2815 ConstantSDNode *RHSConst = dyn_cast(RHS);
2816 IsRHSZero = RHSConst && RHSConst->isNullValue();
2817 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2818 LLVM_FALLTHROUGH;
2819 }
2820 case ISD::SETLT: {
2821 // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
2822 // (sext (setcc %a, 1, setgt)) -> (add (lshr (- %a), 63), -1)
2823 // (sext (setcc %a, 0, setgt)) -> (ashr %a, 31)
2824 if (IsRHSOne) {
2825 if (CmpInGPR == ICGPR_NonExtIn)
2826 return SDValue();
2827 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
2828 }
2829 if (IsRHSZero)
2830 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
2831 S->getI32Imm(31, dl)), 0);
2832
2833 if (CmpInGPR == ICGPR_NonExtIn)
2834 return SDValue();
2835 // The upper 32-bits of the register can't be undefined for this sequence.
2836 LHS = signExtendInputIfNeeded(LHS);
2837 RHS = signExtendInputIfNeeded(RHS);
2838 SDValue SUBFNode =
2839 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2840 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
2841 SUBFNode, S->getI64Imm(63, dl)), 0);
2842 }
2843 case ISD::SETUGE:
2844 // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
2845 // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
2846 std::swap(LHS, RHS);
2847 LLVM_FALLTHROUGH;
2848 case ISD::SETULE: {
2849 if (CmpInGPR == ICGPR_NonExtIn)
2850 return SDValue();
2851 // The upper 32-bits of the register can't be undefined for this sequence.
2852 LHS = zeroExtendInputIfNeeded(LHS);
2853 RHS = zeroExtendInputIfNeeded(RHS);
2854 SDValue Subtract =
2855 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0);
2856 SDValue Shift =
2857 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract,
2858 S->getI32Imm(1, dl), S->getI32Imm(63,dl)),
2859 0);
2860 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
2861 S->getI32Imm(-1, dl)), 0);
2862 }
2863 case ISD::SETUGT:
2864 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
2865 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
2866 std::swap(LHS, RHS);
2867 LLVM_FALLTHROUGH;
2868 case ISD::SETULT: {
2869 if (CmpInGPR == ICGPR_NonExtIn)
2870 return SDValue();
2871 // The upper 32-bits of the register can't be undefined for this sequence.
2872 LHS = zeroExtendInputIfNeeded(LHS);
2873 RHS = zeroExtendInputIfNeeded(RHS);
2874 SDValue Subtract =
2875 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
2876 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
2877 Subtract, S->getI64Imm(63, dl)), 0);
2878 }
2879 }
2880 }
2881
2882 /// Produces a zero-extended result of comparing two 64-bit values according to
2883 /// the passed condition code.
2884 SDValue
2885 IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
2886 ISD::CondCode CC,
2887 int64_t RHSValue, SDLoc dl) {
2888 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
2889 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Sext)
2890 return SDValue();
2891 bool IsRHSZero = RHSValue == 0;
2892 bool IsRHSOne = RHSValue == 1;
2893 bool IsRHSNegOne = RHSValue == -1LL;
2894 switch (CC) {
2895 default: return SDValue();
2896 case ISD::SETEQ: {
2897 // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
2898 // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
2899 SDValue Xor = IsRHSZero ? LHS :
2900 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
2901 SDValue Clz =
2902 SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
2903 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
2904 S->getI64Imm(58, dl),
2905 S->getI64Imm(63, dl)), 0);
2906 }
2907 case ISD::SETNE: {
2908 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
2909 // (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA)
2910 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
2911 // (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA)
2912 SDValue Xor = IsRHSZero ? LHS :
2913 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
2914 SDValue AC =
2915 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
2916 Xor, S->getI32Imm(~0U, dl)), 0);
2917 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
2918 Xor, AC.getValue(1)), 0);
2919 }
2920 case ISD::SETGE: {
2921 // {subc.reg, subc.CA} = (subcarry %a, %b)
2922 // (zext (setcc %a, %b, setge)) ->
2923 // (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
2924 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
2925 if (IsRHSZero)
2926 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2927 std::swap(LHS, RHS);
2928 ConstantSDNode *RHSConst = dyn_cast(RHS);
2929 IsRHSZero = RHSConst && RHSConst->isNullValue();
2930 LLVM_FALLTHROUGH;
2931 }
2932 case ISD::SETLE: {
2933 // {subc.reg, subc.CA} = (subcarry %b, %a)
2934 // (zext (setcc %a, %b, setge)) ->
2935 // (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
2936 // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
2937 if (IsRHSZero)
2938 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2939 SDValue ShiftL =
2940 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
2941 S->getI64Imm(1, dl),
2942 S->getI64Imm(63, dl)), 0);
2943 SDValue ShiftR =
2944 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
2945 S->getI64Imm(63, dl)), 0);
2946 SDValue SubtractCarry =
2947 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
2948 LHS, RHS), 1);
2949 return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
2950 ShiftR, ShiftL, SubtractCarry), 0);
2951 }
2952 case ISD::SETGT: {
2953 // {subc.reg, subc.CA} = (subcarry %b, %a)
2954 // (zext (setcc %a, %b, setgt)) ->
2955 // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
2956 // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63)
2957 if (IsRHSNegOne)
2958 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2959 if (IsRHSZero) {
2960 SDValue Addi =
2961 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2962 S->getI64Imm(~0ULL, dl)), 0);
2963 SDValue Nor =
2964 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
2965 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
2966 S->getI64Imm(1, dl),
2967 S->getI64Imm(63, dl)), 0);
2968 }
2969 std::swap(LHS, RHS);
2970 ConstantSDNode *RHSConst = dyn_cast(RHS);
2971 IsRHSZero = RHSConst && RHSConst->isNullValue();
2972 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
2973 LLVM_FALLTHROUGH;
2974 }
2975 case ISD::SETLT: {
2976 // {subc.reg, subc.CA} = (subcarry %a, %b)
2977 // (zext (setcc %a, %b, setlt)) ->
2978 // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
2979 // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63)
2980 if (IsRHSOne)
2981 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2982 if (IsRHSZero)
2983 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
2984 S->getI64Imm(1, dl),
2985 S->getI64Imm(63, dl)), 0);
2986 SDValue SRADINode =
2987 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
2988 LHS, S->getI64Imm(63, dl)), 0);
2989 SDValue SRDINode =
2990 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2991 RHS, S->getI64Imm(1, dl),
2992 S->getI64Imm(63, dl)), 0);
2993 SDValue SUBFC8Carry =
2994 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
2995 RHS, LHS), 1);
2996 SDValue ADDE8Node =
2997 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
2998 SRDINode, SRADINode, SUBFC8Carry), 0);
2999 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3000 ADDE8Node, S->getI64Imm(1, dl)), 0);
3001 }
3002 case ISD::SETUGE:
3003 // {subc.reg, subc.CA} = (subcarry %a, %b)
3004 // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
3005 std::swap(LHS, RHS);
3006 LLVM_FALLTHROUGH;
3007 case ISD::SETULE: {
3008 // {subc.reg, subc.CA} = (subcarry %b, %a)
3009 // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
3010 SDValue SUBFC8Carry =
3011 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3012 LHS, RHS), 1);
3013 SDValue SUBFE8Node =
3014 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue,
3015 LHS, LHS, SUBFC8Carry), 0);
3016 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64,
3017 SUBFE8Node, S->getI64Imm(1, dl)), 0);
3018 }
3019 case ISD::SETUGT:
3020 // {subc.reg, subc.CA} = (subcarry %b, %a)
3021 // (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA)
3022 std::swap(LHS, RHS);
3023 LLVM_FALLTHROUGH;
3024 case ISD::SETULT: {
3025 // {subc.reg, subc.CA} = (subcarry %a, %b)
3026 // (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA)
3027 SDValue SubtractCarry =
3028 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3029 RHS, LHS), 1);
3030 SDValue ExtSub =
3031 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3032 LHS, LHS, SubtractCarry), 0);
3033 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3034 ExtSub), 0);
3035 }
3036 }
3037 }
3038
3039 /// Produces a sign-extended result of comparing two 64-bit values according to
3040 /// the passed condition code.
3041 SDValue
3042 IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
3043 ISD::CondCode CC,
3044 int64_t RHSValue, SDLoc dl) {
3045 if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 ||
3046 CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext)
3047 return SDValue();
3048 bool IsRHSZero = RHSValue == 0;
3049 bool IsRHSOne = RHSValue == 1;
3050 bool IsRHSNegOne = RHSValue == -1LL;
3051 switch (CC) {
3052 default: return SDValue();
3053 case ISD::SETEQ: {
3054 // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
3055 // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
3056 // {addcz.reg, addcz.CA} = (addcarry %a, -1)
3057 // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
3058 SDValue AddInput = IsRHSZero ? LHS :
3059 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3060 SDValue Addic =
3061 SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
3062 AddInput, S->getI32Imm(~0U, dl)), 0);
3063 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
3064 Addic, Addic.getValue(1)), 0);
3065 }
3066 case ISD::SETNE: {
3067 // {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b))
3068 // (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA)
3069 // {subfcz.reg, subfcz.CA} = (subcarry 0, %a)
3070 // (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA)
3071 SDValue Xor = IsRHSZero ? LHS :
3072 SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
3073 SDValue SC =
3074 SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
3075 Xor, S->getI32Imm(0, dl)), 0);
3076 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
3077 SC, SC.getValue(1)), 0);
3078 }
3079 case ISD::SETGE: {
3080 // {subc.reg, subc.CA} = (subcarry %a, %b)
3081 // (zext (setcc %a, %b, setge)) ->
3082 // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
3083 // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
3084 if (IsRHSZero)
3085 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3086 std::swap(LHS, RHS);
3087 ConstantSDNode *RHSConst = dyn_cast(RHS);
3088 IsRHSZero = RHSConst && RHSConst->isNullValue();
3089 LLVM_FALLTHROUGH;
3090 }
3091 case ISD::SETLE: {
3092 // {subc.reg, subc.CA} = (subcarry %b, %a)
3093 // (zext (setcc %a, %b, setge)) ->
3094 // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
3095 // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
3096 if (IsRHSZero)
3097 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3098 SDValue ShiftR =
3099 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
3100 S->getI64Imm(63, dl)), 0);
3101 SDValue ShiftL =
3102 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
3103 S->getI64Imm(1, dl),
3104 S->getI64Imm(63, dl)), 0);
3105 SDValue SubtractCarry =
3106 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3107 LHS, RHS), 1);
3108 SDValue Adde =
3109 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
3110 ShiftR, ShiftL, SubtractCarry), 0);
3111 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
3112 }
3113 case ISD::SETGT: {
3114 // {subc.reg, subc.CA} = (subcarry %b, %a)
3115 // (zext (setcc %a, %b, setgt)) ->
3116 // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1)
3117 // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63)
3118 if (IsRHSNegOne)
3119 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
3120 if (IsRHSZero) {
3121 SDValue Add =
3122 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
3123 S->getI64Imm(-1, dl)), 0);
3124 SDValue Nor =
3125 SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
3126 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
3127 S->getI64Imm(63, dl)), 0);
3128 }
3129 std::swap(LHS, RHS);
3130 ConstantSDNode *RHSConst = dyn_cast(RHS);
3131 IsRHSZero = RHSConst && RHSConst->isNullValue();
3132 IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
3133 LLVM_FALLTHROUGH;
3134 }
3135 case ISD::SETLT: {
3136 // {subc.reg, subc.CA} = (subcarry %a, %b)
3137 // (zext (setcc %a, %b, setlt)) ->
3138 // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1)
3139 // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63)
3140 if (IsRHSOne)
3141 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3142 if (IsRHSZero) {
3143 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
3144 S->getI64Imm(63, dl)), 0);
3145 }
3146 SDValue SRADINode =
3147 SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3148 LHS, S->getI64Imm(63, dl)), 0);
3149 SDValue SRDINode =
3150 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3151 RHS, S->getI64Imm(1, dl),
3152 S->getI64Imm(63, dl)), 0);
3153 SDValue SUBFC8Carry =
3154 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3155 RHS, LHS), 1);
3156 SDValue ADDE8Node =
3157 SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
3158 SRDINode, SRADINode, SUBFC8Carry), 0);
3159 SDValue XORI8Node =
3160 SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
3161 ADDE8Node, S->getI64Imm(1, dl)), 0);
3162 return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
3163 XORI8Node), 0);
3164 }
3165 case ISD::SETUGE:
3166 // {subc.reg, subc.CA} = (subcarry %a, %b)
3167 // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
3168 std::swap(LHS, RHS);
3169 LLVM_FALLTHROUGH;
3170 case ISD::SETULE: {
3171 // {subc.reg, subc.CA} = (subcarry %b, %a)
3172 // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
3173 SDValue SubtractCarry =
3174 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3175 LHS, RHS), 1);
3176 SDValue ExtSub =
3177 SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS,
3178 LHS, SubtractCarry), 0);
3179 return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64,
3180 ExtSub, ExtSub), 0);
3181 }
3182 case ISD::SETUGT:
3183 // {subc.reg, subc.CA} = (subcarry %b, %a)
3184 // (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA)
3185 std::swap(LHS, RHS);
3186 LLVM_FALLTHROUGH;
3187 case ISD::SETULT: {
3188 // {subc.reg, subc.CA} = (subcarry %a, %b)
3189 // (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA)
3190 SDValue SubCarry =
3191 SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
3192 RHS, LHS), 1);
3193 return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
3194 LHS, LHS, SubCarry), 0);
3195 }
3196 }
3197 }
3198
3199 /// Do all uses of this SDValue need the result in a GPR?
3200 /// This is meant to be used on values that have type i1 since
3201 /// it is somewhat meaningless to ask if values of other types
3202 /// should be kept in GPR's.
3203 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
3204 assert(Compare.getOpcode() == ISD::SETCC &&
3205 "An ISD::SETCC node required here.");
3206
3207 // For values that have a single use, the caller should obviously already have
3208 // checked if that use is an extending use. We check the other uses here.
3209 if (Compare.hasOneUse())
3210 return true;
3211 // We want the value in a GPR if it is being extended, used for a select, or
3212 // used in logical operations.
3213 for (auto CompareUse : Compare.getNode()->uses())
3214 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3215 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3216 CompareUse->getOpcode() != ISD::SELECT &&
3217 !isLogicOp(CompareUse->getOpcode())) {
3218 OmittedForNonExtendUses++;
3219 return false;
3220 }
3221 return true;
3222 }
3223
3224 /// Returns an equivalent of a SETCC node but with the result the same width as
3225 /// the inputs. This can nalso be used for SELECT_CC if either the true or false
3226 /// values is a power of two while the other is zero.
3227 SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare,
3228 SetccInGPROpts ConvOpts) {
3229 assert((Compare.getOpcode() == ISD::SETCC ||
3230 Compare.getOpcode() == ISD::SELECT_CC) &&
3231 "An ISD::SETCC node required here.");
3232
3233 // Don't convert this comparison to a GPR sequence because there are uses
3234 // of the i1 result (i.e. uses that require the result in the CR).
3235 if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG))
3236 return SDValue();
3237
3238 SDValue LHS = Compare.getOperand(0);
3239 SDValue RHS = Compare.getOperand(1);
3240
3241 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
3242 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
3243 ISD::CondCode CC =
3244 cast(Compare.getOperand(CCOpNum))->get();
3245 EVT InputVT = LHS.getValueType();
3246 if (InputVT != MVT::i32 && InputVT != MVT::i64)
3247 return SDValue();
3248
3249 if (ConvOpts == SetccInGPROpts::ZExtInvert ||
3250 ConvOpts == SetccInGPROpts::SExtInvert)
3251 CC = ISD::getSetCCInverse(CC, true);
3252
3253 bool Inputs32Bit = InputVT == MVT::i32;
3254
3255 SDLoc dl(Compare);
3256 ConstantSDNode *RHSConst = dyn_cast(RHS);
3257 int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
3258 bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
3259 ConvOpts == SetccInGPROpts::SExtInvert;
3260
3261 if (IsSext && Inputs32Bit)
3262 return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3263 else if (Inputs32Bit)
3264 return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3265 else if (IsSext)
3266 return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
3267 return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
3268 }
3269
20663270 } // end anonymous namespace
3271
3272 bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) {
3273 if (N->getValueType(0) != MVT::i32 &&
3274 N->getValueType(0) != MVT::i64)
3275 return false;
3276
3277 // This optimization will emit code that assumes 64-bit registers
3278 // so we don't want to run it in 32-bit mode. Also don't run it
3279 // on functions that are not to be optimized.
3280 if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
3281 return false;
3282
3283 switch (N->getOpcode()) {
3284 default: break;
3285 case ISD::ZERO_EXTEND:
3286 case ISD::SIGN_EXTEND:
3287 case ISD::AND:
3288 case ISD::OR:
3289 case ISD::XOR: {
3290 IntegerCompareEliminator ICmpElim(CurDAG, this);
3291 if (SDNode *New = ICmpElim.Select(N)) {
3292 ReplaceNode(N, New);
3293 return true;
3294 }
3295 }
3296 }
3297 return false;
3298 }
20673299
20683300 bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
20693301 if (N->getValueType(0) != MVT::i32 &&
25753807
25763808 // Try matching complex bit permutations before doing anything else.
25773809 if (tryBitPermutation(N))
3810 return;
3811
3812 // Try to emit integer compares as GPR-only sequences (i.e. no use of CR).
3813 if (tryIntCompareInGPR(N))
25783814 return;
25793815
25803816 switch (N->getOpcode()) {
None ; XFAIL: *
1 ; The purpose of the test case is to ensure that a spill that happens during
21 ; intermediate calculations for a comparison performed in a GPR spills the
32 ; full register. Some i32 comparisons performed in GPRs use code that uses
43 ; the full 64-bits of the register in intermediate stages. Spilling such a value
54 ; as a 32-bit value is incorrect.
65 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
7 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
87 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
98 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
10 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
9 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1110 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1211 @glob = common local_unnamed_addr global i64 0, align 8
1312 @.str = private unnamed_addr constant [12 x i8] c"Value = %d\0A\00", align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
0 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
1 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
32 target datalayout = "E-m:e-i64:64-n32:64"
43 target triple = "powerpc64-unknown-linux-gnu"
54
None ; XFAIL: *
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
21 target triple = "powerpc64-unknown-linux-gnu"
3 ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
2 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
43 ; Function Attrs: norecurse nounwind readnone
54 define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
65 entry:
212211 ret i32 %retval.0
213212
214213 ; CHECK-LABEL: @testComplexISEL
215 ; CHECK-DAG: [[LI:r[0-9]+]], 1
216 ; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
217 ; CHECK: bnelr cr0
214 ; CHECK: cmplwi r3, 0
215 ; CHECK: li r3, 1
216 ; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
217 ; CHECK: clrldi r3, r3, 32
218 ; CHECK: blr
219 ; CHECK: [[TGT]]
218220 ; CHECK: xor [[XOR:r[0-9]+]]
219221 ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
220222 ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
1 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
32 target datalayout = "e-m:e-i64:64-n32:64"
43 target triple = "powerpc64le-unknown-linux-gnu"
54
3433 ; Check 16 bytes - requires 2 loads for each param (or use vectors?).
3534 define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
3635 ; CHECK-LABEL: zeroEqualityTest01:
37 ; CHECK: # BB#0: # %loadbb
36 ; CHECK: # BB#0:
3837 ; CHECK-NEXT: ld 5, 0(3)
3938 ; CHECK-NEXT: ld 6, 0(4)
4039 ; CHECK-NEXT: cmpld 5, 6
4443 ; CHECK-NEXT: ld 4, 8(4)
4544 ; CHECK-NEXT: cmpld 3, 4
4645 ; CHECK-NEXT: li 3, 0
47 ; CHECK-NEXT: beqlr 0
46 ; CHECK-NEXT: beq 0, .LBB1_3
4847 ; CHECK-NEXT: .LBB1_2: # %res_block
4948 ; CHECK-NEXT: li 3, 1
49 ; CHECK-NEXT: .LBB1_3: # %endblock
50 ; CHECK-NEXT: clrldi 3, 3, 32
5051 ; CHECK-NEXT: blr
5152 %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
5253 %not.tobool = icmp ne i32 %call, 0
5758 ; Check 7 bytes - requires 3 loads for each param.
5859 define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) {
5960 ; CHECK-LABEL: zeroEqualityTest03:
60 ; CHECK: # BB#0: # %loadbb
61 ; CHECK: # BB#0:
6162 ; CHECK-NEXT: lwz 5, 0(3)
6263 ; CHECK-NEXT: lwz 6, 0(4)
6364 ; CHECK-NEXT: cmplw 5, 6
7273 ; CHECK-NEXT: lbz 4, 6(4)
7374 ; CHECK-NEXT: cmplw 3, 4
7475 ; CHECK-NEXT: li 3, 0
75 ; CHECK-NEXT: beqlr 0
76 ; CHECK-NEXT: beq 0, .LBB2_4
7677 ; CHECK-NEXT: .LBB2_3: # %res_block
7778 ; CHECK-NEXT: li 3, 1
79 ; CHECK-NEXT: .LBB2_4: # %endblock
80 ; CHECK-NEXT: clrldi 3, 3, 32
7881 ; CHECK-NEXT: blr
7982 %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
8083 %not.lnot = icmp ne i32 %call, 0
8588 ; Validate with > 0
8689 define signext i32 @zeroEqualityTest04() {
8790 ; CHECK-LABEL: zeroEqualityTest04:
88 ; CHECK: # BB#0: # %loadbb
91 ; CHECK: # BB#0:
8992 ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest02.buffer1@toc@ha
9093 ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest02.buffer2@toc@ha
9194 ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest02.buffer1@toc@l
107110 ; CHECK-NEXT: li 12, -1
108111 ; CHECK-NEXT: isel 5, 12, 11, 0
109112 ; CHECK-NEXT: .LBB3_3: # %endblock
110 ; CHECK-NEXT: neg 3, 5
113 ; CHECK-NEXT: extsw 3, 5
114 ; CHECK-NEXT: neg 3, 3
111115 ; CHECK-NEXT: rldicl 3, 3, 1, 63
112116 ; CHECK-NEXT: xori 3, 3, 1
113117 ; CHECK-NEXT: blr
120124 ; Validate with < 0
121125 define signext i32 @zeroEqualityTest05() {
122126 ; CHECK-LABEL: zeroEqualityTest05:
123 ; CHECK: # BB#0: # %loadbb
127 ; CHECK: # BB#0:
124128 ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest03.buffer1@toc@ha
125129 ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest03.buffer2@toc@ha
126130 ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest03.buffer1@toc@l
166170
167171 define signext i32 @equalityFoldOneConstant(i8* %X) {
168172 ; CHECK-LABEL: equalityFoldOneConstant:
169 ; CHECK: # BB#0: # %loadbb
170 ; CHECK-NEXT: li 4, 1
171 ; CHECK-NEXT: ld 5, 0(3)
172 ; CHECK-NEXT: sldi 4, 4, 32
173 ; CHECK-NEXT: cmpld 5, 4
173 ; CHECK: # BB#0:
174 ; CHECK-NEXT: li 5, 1
175 ; CHECK-NEXT: ld 4, 0(3)
176 ; CHECK-NEXT: sldi 5, 5, 32
177 ; CHECK-NEXT: cmpld 4, 5
174178 ; CHECK-NEXT: bne 0, .LBB6_2
175179 ; CHECK-NEXT: # BB#1: # %loadbb1
176180 ; CHECK-NEXT: li 4, 3
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
0 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
1 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
32 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
43 target triple = "powerpc64-unknown-linux-gnu"
54
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
0 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
1 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
32 target datalayout = "E-m:e-i64:64-n32:64"
43 target triple = "powerpc64-unknown-linux-gnu"
54
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
1 ; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
32
43 define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) {
54 ; CHECK-LABEL: all_bits_clear:
418417 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
419418 ; CHECK-LABEL: ne_neg1_and_ne_zero:
420419 ; CHECK: # BB#0:
420 ; CHECK-NEXT: li 4, 1
421421 ; CHECK-NEXT: addi 3, 3, 1
422 ; CHECK-NEXT: li 4, 0
423 ; CHECK-NEXT: li 12, 1
424 ; CHECK-NEXT: cmpldi 3, 1
425 ; CHECK-NEXT: isel 3, 12, 4, 1
422 ; CHECK-NEXT: subfc 3, 3, 4
423 ; CHECK-NEXT: subfe 3, 4, 4
424 ; CHECK-NEXT: neg 3, 3
426425 ; CHECK-NEXT: blr
427426 %cmp1 = icmp ne i64 %x, -1
428427 %cmp2 = icmp ne i64 %x, 0
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 %struct.tree_common = type { i8, [3 x i8] }
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 %struct.tree_common = type { i8, [3 x i8] }
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
98
None ; XFAIL: *
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
11 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
33 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
44 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
66 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i8 0, align 1
98
109 define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
11 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
33 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
44 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
66 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i16 0, align 2
98
109 define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
105104 store i32 %conv1, i32* @glob
106105 ret void
107106 ; CHECK-LABEL: @test_igeui_sext_z_store
108 ; CHECK: li [[REG1:r[0-9]+]], -1
109 ; CHECK: stw [[REG1]]
110 ; CHECK: blr
107 ; CHECK: li [[REG1:r[0-9]+]], 0
108 ; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
109 ; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
110 ; CHECK: stw [[REG3]]
111 ; CHECK: blr
111112 }
112113
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i64 0, align 8
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_igeull(i64 %a, i64 %b) {
11 entry:
12 %cmp = icmp uge i64 %a, %b
13 %conv = zext i1 %cmp to i32
14 ret i32 %conv
15 ; CHECK-LABEL: test_igeull:
16 ; CHECK: subfc {{r[0-9]+}}, r4, r3
17 ; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
18 ; CHECK-NEXT: addi r3, [[REG1]], 1
19 ; CHECK: blr
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
24 entry:
25 %cmp = icmp uge i64 %a, %b
26 %sub = sext i1 %cmp to i32
27 ret i32 %sub
28 ; CHECK-LABEL: @test_igeull_sext
29 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
30 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
31 ; CHECK: not r3, [[REG2]]
32 ; CHECK: blr
33 }
34
35 ; Function Attrs: norecurse nounwind readnone
36 define signext i32 @test_igeull_z(i64 %a) {
37 entry:
38 %cmp = icmp uge i64 %a, 0
39 %sub = zext i1 %cmp to i32
40 ret i32 %sub
41 ; CHECK-LABEL: @test_igeull_z
42 ; CHECK: li r3, 1
43 ; CHECK-NEXT: blr
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define signext i32 @test_igeull_sext_z(i64 %a) {
48 entry:
49 %cmp = icmp uge i64 %a, 0
50 %sub = sext i1 %cmp to i32
51 ret i32 %sub
52 ; CHECK-LABEL: @test_igeull_sext_z
53 ; CHECK: li r3, -1
54 ; CHECK-NEXT: blr
55 }
56
57 ; Function Attrs: norecurse nounwind
58 define void @test_igeull_store(i64 %a, i64 %b) {
59 entry:
60 %cmp = icmp uge i64 %a, %b
61 %conv1 = zext i1 %cmp to i64
62 store i64 %conv1, i64* @glob
63 ret void
64 ; CHECK-LABEL: test_igeull_store:
65 ; CHECK: subfc {{r[0-9]+}}, r4, r3
66 ; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
67 ; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
68 ; CHECK: blr
69 }
70
71 ; Function Attrs: norecurse nounwind
72 define void @test_igeull_sext_store(i64 %a, i64 %b) {
73 entry:
74 %cmp = icmp uge i64 %a, %b
75 %conv1 = sext i1 %cmp to i64
76 store i64 %conv1, i64* @glob
77 ret void
78 ; CHECK-LABEL: @test_igeull_sext_store
79 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
80 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
81 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
82 ; CHECK: std [[REG3]]
83 ; CHECK: blr
84 }
85
86 ; Function Attrs: norecurse nounwind
87 define void @test_igeull_z_store(i64 %a) {
88 entry:
89 %cmp = icmp uge i64 %a, 0
90 %conv1 = zext i1 %cmp to i64
91 store i64 %conv1, i64* @glob
92 ret void
93 ; CHECK-LABEL: @test_igeull_z_store
94 ; CHECK: li [[REG1:r[0-9]+]], 1
95 ; CHECK: std [[REG1]]
96 ; CHECK: blr
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_igeull_sext_z_store(i64 %a) {
101 entry:
102 %cmp = icmp uge i64 %a, 0
103 %conv1 = sext i1 %cmp to i64
104 store i64 %conv1, i64* @glob
105 ret void
106 ; CHECK-LABEL: @test_igeull_sext_z_store
107 ; CHECK: li [[REG1:r[0-9]+]], -1
108 ; CHECK: std [[REG1]]
109 ; CHECK: blr
110 }
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
105104 store i16 %conv3, i16* @glob
106105 ret void
107106 ; CHECK-LABEL: @test_igeus_sext_z_store
108 ; CHECK: lis [[REG1:r[0-9]+]], 0
107 ; CHECK: li [[REG1:r[0-9]+]], 0
109108 ; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
110109 ; CHECK: sth [[REG2]]
111110 ; CHECK: blr
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i8 0, align 1
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i16 0, align 2
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i64 0, align 8
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_ileull(i64 %a, i64 %b) {
11 entry:
12 %cmp = icmp ule i64 %a, %b
13 %conv = zext i1 %cmp to i32
14 ret i32 %conv
15 ; CHECK-LABEL: test_ileull:
16 ; CHECK: subfc {{r[0-9]+}}, r3, r4
17 ; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
18 ; CHECK-NEXT: addi r3, [[REG1]], 1
19 ; CHECK-NEXT: blr
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
24 entry:
25 %cmp = icmp ule i64 %a, %b
26 %sub = sext i1 %cmp to i32
27 ret i32 %sub
28 ; CHECK-LABEL: @test_ileull_sext
29 ; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
30 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
31 ; CHECK: not r3, [[REG2]]
32 ; CHECK: blr
33 }
34
35 ; Function Attrs: norecurse nounwind readnone
36 define signext i32 @test_ileull_z(i64 %a) {
37 entry:
38 %cmp = icmp ule i64 %a, 0
39 %conv = zext i1 %cmp to i32
40 ret i32 %conv
41 ; CHECK-LABEL: test_ileull_z
42 ; CHECK: cntlzd [[REG1:r[0-9]+]], r3
43 ; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
44 ; CHECK-NEXT: blr
45 }
46
47 ; Function Attrs: norecurse nounwind readnone
48 define signext i32 @test_ileull_sext_z(i64 %a) {
49 entry:
50 %cmp = icmp ule i64 %a, 0
51 %sub = sext i1 %cmp to i32
52 ret i32 %sub
53 ; CHECK-LABEL: @test_ileull_sext_z
54 ; CHECK: addic [[REG1:r[0-9]+]], r3, -1
55 ; CHECK: subfe r3, [[REG1]]
56 ; CHECK: blr
57 }
58
59 ; Function Attrs: norecurse nounwind
60 define void @test_ileull_store(i64 %a, i64 %b) {
61 entry:
62 %cmp = icmp ule i64 %a, %b
63 %conv1 = zext i1 %cmp to i64
64 store i64 %conv1, i64* @glob
65 ret void
66 ; CHECK-LABEL: test_ileull_store:
67 ; CHECK: subfc {{r[0-9]+}}, r3, r4
68 ; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
69 ; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
70 ; CHECK: blr
71 }
72
73 ; Function Attrs: norecurse nounwind
74 define void @test_ileull_sext_store(i64 %a, i64 %b) {
75 entry:
76 %cmp = icmp ule i64 %a, %b
77 %conv1 = sext i1 %cmp to i64
78 store i64 %conv1, i64* @glob
79 ret void
80 ; CHECK-LABEL: @test_ileull_sext_store
81 ; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
82 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
83 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
84 ; CHECK: std [[REG3]]
85 ; CHECK: blr
86 }
87
88 ; Function Attrs: norecurse nounwind
89 define void @test_ileull_z_store(i64 %a) {
90 entry:
91 %cmp = icmp ule i64 %a, 0
92 %conv1 = zext i1 %cmp to i64
93 store i64 %conv1, i64* @glob
94 ret void
95 ; CHECK-LABEL: test_ileull_z_store:
96 ; CHECK: cntlzd [[REG1:r[0-9]+]], r3
97 ; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
98 ; CHECK: blr
99 }
100
101 ; Function Attrs: norecurse nounwind
102 define void @test_ileull_sext_z_store(i64 %a) {
103 entry:
104 %cmp = icmp ule i64 %a, 0
105 %conv1 = sext i1 %cmp to i64
106 store i64 %conv1, i64* @glob
107 ret void
108 ; CHECK-LABEL: @test_ileull_sext_z_store
109 ; CHECK: addic [[REG1:r[0-9]+]], r3, -1
110 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
111 ; CHECK: std [[REG2]]
112 ; CHECK: blr
113 }
114
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
98 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
98 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87 ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
98
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
43 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
54 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
76 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
87
98 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i8 0, align 1
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i16 0, align 2
98
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
105104 store i32 %sub, i32* @glob
106105 ret void
107106 ; CHECK-LABEL: @test_llgeui_sext_z_store
108 ; CHECK: li [[REG1:r[0-9]+]], -1
109 ; CHECK: stw [[REG1]]
110 ; CHECK: blr
107 ; CHECK: li [[REG1:r[0-9]+]], 0
108 ; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
109 ; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
110 ; CHECK: stw [[REG3]]
111 ; CHECK: blr
111112 }
112113
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i64 0, align 8
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llgeull(i64 %a, i64 %b) {
11 entry:
12 %cmp = icmp uge i64 %a, %b
13 %conv1 = zext i1 %cmp to i64
14 ret i64 %conv1
15 ; CHECK-LABEL: test_llgeull:
16 ; CHECK: subfc {{r[0-9]+}}, r4, r3
17 ; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
18 ; CHECK-NEXT: addi r3, [[REG1]], 1
19 ; CHECK: blr
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define i64 @test_llgeull_sext(i64 %a, i64 %b) {
24 entry:
25 %cmp = icmp uge i64 %a, %b
26 %conv1 = sext i1 %cmp to i64
27 ret i64 %conv1
28 ; CHECK-LABEL: @test_llgeull_sext
29 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
30 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
31 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
32 ; CHECK: blr
33 }
34
35 ; Function Attrs: norecurse nounwind readnone
36 define i64 @test_llgeull_z(i64 %a) {
37 entry:
38 %cmp = icmp uge i64 %a, 0
39 %conv1 = zext i1 %cmp to i64
40 ret i64 %conv1
41 ; CHECK-LABEL: @test_llgeull_z
42 ; CHECK: li r3, 1
43 ; CHECK-NEXT: blr
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define i64 @test_llgeull_sext_z(i64 %a) {
48 entry:
49 %cmp = icmp uge i64 %a, 0
50 %conv1 = sext i1 %cmp to i64
51 ret i64 %conv1
52 ; CHECK-LABEL: @test_llgeull_sext_z
53 ; CHECK: li r3, -1
54 ; CHECK-NEXT: blr
55 }
56
57 ; Function Attrs: norecurse nounwind
58 define void @test_llgeull_store(i64 %a, i64 %b) {
59 entry:
60 %cmp = icmp uge i64 %a, %b
61 %conv1 = zext i1 %cmp to i64
62 store i64 %conv1, i64* @glob
63 ret void
64 ; CHECK-LABEL: test_llgeull_store:
65 ; CHECK: subfc {{r[0-9]+}}, r4, r3
66 ; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
67 ; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
68 ; CHECK: blr
69 }
70
71 ; Function Attrs: norecurse nounwind
72 define void @test_llgeull_sext_store(i64 %a, i64 %b) {
73 entry:
74 %cmp = icmp uge i64 %a, %b
75 %conv1 = sext i1 %cmp to i64
76 store i64 %conv1, i64* @glob
77 ret void
78 ; CHECK-LABEL: @test_llgeull_sext_store
79 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
80 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
81 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
82 ; CHECK: std [[REG3]]
83 ; CHECK: blr
84 }
85
86 ; Function Attrs: norecurse nounwind
87 define void @test_llgeull_z_store(i64 %a) {
88 entry:
89 %cmp = icmp uge i64 %a, 0
90 %conv1 = zext i1 %cmp to i64
91 store i64 %conv1, i64* @glob
92 ret void
93 ; CHECK-LABEL: @test_llgeull_z_store
94 ; CHECK: li [[REG1:r[0-9]+]], 1
95 ; CHECK: std [[REG1]]
96 ; CHECK: blr
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_llgeull_sext_z_store(i64 %a) {
101 entry:
102 store i64 -1, i64* @glob
103 ret void
104 ; CHECK-LABEL: @test_llgeull_sext_z_store
105 ; CHECK: li [[REG1:r[0-9]+]], -1
106 ; CHECK: std [[REG1]]
107 ; CHECK: blr
108 }
109
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
105104 store i16 %conv1, i16* @glob
106105 ret void
107106 ; CHECK-LABEL: @test_llgeus_sext_z_store
108 ; CHECK: lis [[REG1:r[0-9]+]], 0
107 ; CHECK: li [[REG1:r[0-9]+]], 0
109108 ; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
110109 ; CHECK: sth [[REG2]]
111110 ; CHECK: blr
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
98 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87 @glob = common local_unnamed_addr global i64 0, align 8
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
98 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i64 0, align 8
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llleull(i64 %a, i64 %b) {
11 entry:
12 %cmp = icmp ule i64 %a, %b
13 %conv1 = zext i1 %cmp to i64
14 ret i64 %conv1
15 ; CHECK-LABEL: test_llleull:
16 ; CHECK: subfc {{r[0-9]+}}, r3, r4
17 ; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
18 ; CHECK-NEXT: addi r3, [[REG1]], 1
19 ; CHECK: blr
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define i64 @test_llleull_sext(i64 %a, i64 %b) {
24 entry:
25 %cmp = icmp ule i64 %a, %b
26 %conv1 = sext i1 %cmp to i64
27 ret i64 %conv1
28 ; CHECK-LABEL: @test_llleull_sext
29 ; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
30 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
31 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
32 ; CHECK: blr
33 }
34
35 ; Function Attrs: norecurse nounwind readnone
36 define i64 @test_llleull_z(i64 %a) {
37 entry:
38 %cmp = icmp ule i64 %a, 0
39 %conv1 = zext i1 %cmp to i64
40 ret i64 %conv1
41 ; CHECK-LABEL: test_llleull_z
42 ; CHECK: cntlzd [[REG1:r[0-9]+]], r3
43 ; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
44 ; CHECK-NEXT: blr
45 }
46
47 ; Function Attrs: norecurse nounwind readnone
48 define i64 @test_llleull_sext_z(i64 %a) {
49 entry:
50 %cmp = icmp ule i64 %a, 0
51 %conv1 = sext i1 %cmp to i64
52 ret i64 %conv1
53 ; CHECK-LABEL: @test_llleull_sext_z
54 ; CHECK: addic [[REG1:r[0-9]+]], r3, -1
55 ; CHECK: subfe r3, [[REG1]]
56 ; CHECK: blr
57 }
58
59 ; Function Attrs: norecurse nounwind
60 define void @test_llleull_store(i64 %a, i64 %b) {
61 entry:
62 %cmp = icmp ule i64 %a, %b
63 %conv1 = zext i1 %cmp to i64
64 store i64 %conv1, i64* @glob
65 ret void
66 ; CHECK-LABEL: test_llleull_store:
67 ; CHECK: subfc {{r[0-9]+}}, r3, r4
68 ; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
69 ; CHECK: addi r3, [[REG1]], 1
70 ; CHECK: blr
71 }
72
73 ; Function Attrs: norecurse nounwind
74 define void @test_llleull_sext_store(i64 %a, i64 %b) {
75 entry:
76 %cmp = icmp ule i64 %a, %b
77 %conv1 = sext i1 %cmp to i64
78 store i64 %conv1, i64* @glob
79 ret void
80 ; CHECK-LABEL: @test_llleull_sext_store
81 ; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
82 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
83 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
84 ; CHECK: std [[REG3]]
85 ; CHECK: blr
86 }
87
88 ; Function Attrs: norecurse nounwind
89 define void @test_llleull_z_store(i64 %a) {
90 entry:
91 %cmp = icmp ule i64 %a, 0
92 %conv1 = zext i1 %cmp to i64
93 store i64 %conv1, i64* @glob
94 ret void
95 ; CHECK-LABEL: test_llleull_z_store:
96 ; CHECK: cntlzd [[REG1:r[0-9]+]], r3
97 ; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
98 ; CHECK: blr
99 }
100
101 ; Function Attrs: norecurse nounwind
102 define void @test_llleull_sext_z_store(i64 %a) {
103 entry:
104 %cmp = icmp ule i64 %a, 0
105 %conv1 = sext i1 %cmp to i64
106 store i64 %conv1, i64* @glob
107 ret void
108 ; CHECK-LABEL: @test_llleull_sext_z_store
109 ; CHECK: addic [[REG1:r[0-9]+]], r3, -1
110 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
111 ; CHECK: std [[REG2]]
112 ; CHECK: blr
113 }
114
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i8 0, align 1
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i32 0, align 4
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76
87 @glob = common local_unnamed_addr global i16 0, align 2
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87
None ; XFAIL: *
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
1 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
32 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
43 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
65 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
76 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
87