llvm.org GIT mirror llvm / b318cc1
Fixed a case of ARM disassembly getting an assert on a bad encoding of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 8 years ago
2 changed file(s) with 15 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
24092409 case ARM::VST2b8wb_register:
24102410 case ARM::VST2b16wb_register:
24112411 case ARM::VST2b32wb_register:
2412 if (Rm == 0xF)
2413 return MCDisassembler::Fail;
24122414 Inst.addOperand(MCOperand::CreateImm(0));
24132415 break;
24142416 case ARM::VST3d8_UPD:
0 # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
1
2 # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
3 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 # -------------------------------------------------------------------------------------------------
5 # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
6 # -------------------------------------------------------------------------------------------------
7 #
8 # A8.6.391 VST1 (multiple single elements)
9 # This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128]
10 # But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if
11 # contains two or four registers. rdar://11220250
12 0x00 0xf9 0x2f 0x06