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[AArch64][TableGen] Skip tied result operands for InstAlias Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318650 91177308-0d34-0410-b5e6-96231b3b80d8 Sander de Smalen 1 year, 10 months ago
24 changed file(s) with 276 addition(s) and 266 deletion(s). Raw diff Collapse all Expand all
579579 defm MOVZ : MoveImmediate<0b10, "movz">;
580580
581581 // First group of aliases covers an implicit "lsl #0".
582 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
583 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
582 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;
583 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;
584584 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
585585 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
586586 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
597597 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
598598 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
599599
600 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
601 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
602 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
603 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
600 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>;
601 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>;
602 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>;
603 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>;
604604
605605 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
606606 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
608608 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
609609 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
610610
611 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
612 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
611 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>;
612 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>;
613613
614614 // Final group of aliases covers true "mov $Rd, $imm" cases.
615615 multiclass movw_mov_alias
45174517 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
45184518 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
45194519
4520 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4521 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4522 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4523 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4520 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4521 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4522 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4523 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
45244524
45254525 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
45264526 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
45274527 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
45284528 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
45294529
4530 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4531 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4532 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4533 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4530 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4531 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4532 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4533 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
45344534
45354535 // AdvSIMD FMOV
45364536 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
1616 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
1717 ; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
1818 ; CHECK-OPT-NOT: fmov
19 ; CHECK: ins.d v0[1], [[COPY_REG2]]
19 ; CHECK: mov.d v0[1], [[COPY_REG2]]
2020 ; CHECK-NEXT: ret
2121 ;
2222 ; GENERIC-LABEL: bar:
2828 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
2929 ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
3030 ; GENERIC-OPT-NOT: fmov
31 ; GENERIC: ins v0.d[1], [[COPY_REG2]]
31 ; GENERIC: mov v0.d[1], [[COPY_REG2]]
3232 ; GENERIC-NEXT: ret
3333 %add = add <2 x i64> %a, %b
3434 %vgetq_lane = extractelement <2 x i64> %add, i32 0
44 define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
55 ; CHECK-LABEL: one_lane:
66 ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
7 ; CHECK-NEXT: ins.b v[[REG]][0], w1
7 ; CHECK-NEXT: mov.b v[[REG]][0], w1
88 ; v and q are aliases, and str is preferred against st.16b when possible
99 ; rdar://11246289
1010 ; CHECK: str q[[REG]], [x0]
2121 ; copy for lane zero.
2222 define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
2323 ; CHECK-LABEL: foo:
24 ; CHECK-NOT: ins.s v0[0], v0[0]
25 ; CHECK: ins.s v0[1], v1[0]
26 ; CHECK: ins.s v0[2], v2[0]
27 ; CHECK: ins.s v0[3], v3[0]
24 ; CHECK-NOT: mov.s v0[0], v0[0]
25 ; CHECK: mov.s v0[1], v1[0]
26 ; CHECK: mov.s v0[2], v2[0]
27 ; CHECK: mov.s v0[3], v3[0]
2828 ; CHECK: ret
2929 %1 = insertelement <4 x float> undef, float %a, i32 0
3030 %2 = insertelement <4 x float> %1, float %b, i32 1
260260 define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
261261 ; CHECK-LABEL: f:
262262 ; CHECK-NEXT: fmov s0, w0
263 ; CHECK-NEXT: ins.s v0[1], w1
263 ; CHECK-NEXT: mov.s v0[1], w1
264264 ; CHECK-NEXT: ret
265265 %vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
266266 %vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
270270 define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
271271 ; CHECK-LABEL: g:
272272 ; CHECK-NEXT: fmov s0, w0
273 ; CHECK-NEXT: ins.s v0[1], w1
274 ; CHECK-NEXT: ins.s v0[2], w1
275 ; CHECK-NEXT: ins.s v0[3], w0
273 ; CHECK-NEXT: mov.s v0[1], w1
274 ; CHECK-NEXT: mov.s v0[2], w1
275 ; CHECK-NEXT: mov.s v0[3], w0
276276 ; CHECK-NEXT: ret
277277 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
278278 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
284284 define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
285285 ; CHECK-LABEL: h:
286286 ; CHECK-NEXT: fmov d0, x0
287 ; CHECK-NEXT: ins.d v0[1], x1
287 ; CHECK-NEXT: mov.d v0[1], x1
288288 ; CHECK-NEXT: ret
289289 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
290290 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
61796179 ; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
61806180 ; CHECK-NEXT: str q0, [x3]
61816181 ; CHECK-NEXT: ldr q0, [x4]
6182 ; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
6182 ; CHECK-NEXT: mov.s v0[1], v[[LD]][0]
61836183 ; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2
61846184 ; CHECK-NEXT: str [[POST]], [x1]
61856185 ; CHECK-NEXT: ret
22
33 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
44 ; CHECK-LABEL: ins16bw:
5 ; CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
5 ; CHECK: mov {{v[0-9]+}}.b[15], {{w[0-9]+}}
66 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
77 ret <16 x i8> %tmp3
88 }
99
1010 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
1111 ; CHECK-LABEL: ins8hw:
12 ; CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
12 ; CHECK: mov {{v[0-9]+}}.h[6], {{w[0-9]+}}
1313 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
1414 ret <8 x i16> %tmp3
1515 }
1616
1717 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
1818 ; CHECK-LABEL: ins4sw:
19 ; CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
19 ; CHECK: mov {{v[0-9]+}}.s[2], {{w[0-9]+}}
2020 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
2121 ret <4 x i32> %tmp3
2222 }
2323
2424 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
2525 ; CHECK-LABEL: ins2dw:
26 ; CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
26 ; CHECK: mov {{v[0-9]+}}.d[1], {{x[0-9]+}}
2727 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
2828 ret <2 x i64> %tmp3
2929 }
3030
3131 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
3232 ; CHECK-LABEL: ins8bw:
33 ; CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
33 ; CHECK: mov {{v[0-9]+}}.b[5], {{w[0-9]+}}
3434 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
3535 ret <8 x i8> %tmp3
3636 }
3737
3838 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
3939 ; CHECK-LABEL: ins4hw:
40 ; CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
40 ; CHECK: mov {{v[0-9]+}}.h[3], {{w[0-9]+}}
4141 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
4242 ret <4 x i16> %tmp3
4343 }
4444
4545 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
4646 ; CHECK-LABEL: ins2sw:
47 ; CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
47 ; CHECK: mov {{v[0-9]+}}.s[1], {{w[0-9]+}}
4848 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
4949 ret <2 x i32> %tmp3
5050 }
5151
5252 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
5353 ; CHECK-LABEL: ins16b16:
54 ; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
54 ; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
5555 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
5656 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
5757 ret <16 x i8> %tmp4
5959
6060 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
6161 ; CHECK-LABEL: ins8h8:
62 ; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
62 ; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
6363 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
6464 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
6565 ret <8 x i16> %tmp4
6767
6868 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
6969 ; CHECK-LABEL: ins4s4:
70 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
70 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
7171 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
7272 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
7373 ret <4 x i32> %tmp4
7575
7676 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
7777 ; CHECK-LABEL: ins2d2:
78 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
78 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
7979 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
8080 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
8181 ret <2 x i64> %tmp4
8383
8484 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
8585 ; CHECK-LABEL: ins4f4:
86 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
86 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
8787 %tmp3 = extractelement <4 x float> %tmp1, i32 2
8888 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
8989 ret <4 x float> %tmp4
9191
9292 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
9393 ; CHECK-LABEL: ins2df2:
94 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
94 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
9595 %tmp3 = extractelement <2 x double> %tmp1, i32 0
9696 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
9797 ret <2 x double> %tmp4
9999
100100 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
101101 ; CHECK-LABEL: ins8b16:
102 ; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
102 ; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
103103 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
104104 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
105105 ret <16 x i8> %tmp4
107107
108108 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
109109 ; CHECK-LABEL: ins4h8:
110 ; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
110 ; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
111111 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
112112 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
113113 ret <8 x i16> %tmp4
115115
116116 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
117117 ; CHECK-LABEL: ins2s4:
118 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
118 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
119119 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
120120 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
121121 ret <4 x i32> %tmp4
123123
124124 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
125125 ; CHECK-LABEL: ins1d2:
126 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
126 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
127127 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
128128 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
129129 ret <2 x i64> %tmp4
131131
132132 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
133133 ; CHECK-LABEL: ins2f4:
134 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
134 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
135135 %tmp3 = extractelement <2 x float> %tmp1, i32 1
136136 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
137137 ret <4 x float> %tmp4
147147
148148 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
149149 ; CHECK-LABEL: ins16b8:
150 ; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
150 ; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
151151 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
152152 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
153153 ret <8 x i8> %tmp4
155155
156156 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
157157 ; CHECK-LABEL: ins8h4:
158 ; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
158 ; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
159159 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
160160 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
161161 ret <4 x i16> %tmp4
163163
164164 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
165165 ; CHECK-LABEL: ins4s2:
166 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
166 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
167167 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
168168 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
169169 ret <2 x i32> %tmp4
171171
172172 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
173173 ; CHECK-LABEL: ins2d1:
174 ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
174 ; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
175175 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
176176 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
177177 ret <1 x i64> %tmp4
179179
180180 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
181181 ; CHECK-LABEL: ins4f2:
182 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
182 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
183183 %tmp3 = extractelement <4 x float> %tmp1, i32 2
184184 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
185185 ret <2 x float> %tmp4
195195
196196 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
197197 ; CHECK-LABEL: ins8b8:
198 ; CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
198 ; CHECK: mov {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
199199 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
200200 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
201201 ret <8 x i8> %tmp4
203203
204204 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
205205 ; CHECK-LABEL: ins4h4:
206 ; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
206 ; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
207207 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
208208 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
209209 ret <4 x i16> %tmp4
211211
212212 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
213213 ; CHECK-LABEL: ins2s2:
214 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
214 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
215215 %tmp3 = extractelement <2 x i32> %tmp1, i32 0
216216 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
217217 ret <2 x i32> %tmp4
219219
220220 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
221221 ; CHECK-LABEL: ins1d1:
222 ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
222 ; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
223223 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
224224 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
225225 ret <1 x i64> %tmp4
227227
228228 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
229229 ; CHECK-LABEL: ins2f2:
230 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
230 ; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
231231 %tmp3 = extractelement <2 x float> %tmp1, i32 0
232232 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
233233 ret <2 x float> %tmp4
235235
236236 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
237237 ; CHECK-LABEL: ins1df1:
238 ; CHECK-NOT: ins {{v[0-9]+}}
238 ; CHECK-NOT: mov {{v[0-9]+}}
239239 %tmp3 = extractelement <1 x double> %tmp1, i32 0
240240 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
241241 ret <1 x double> %tmp4
387387
388388 define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
389389 ; CHECK-LABEL: test_vcopy_lane_s8:
390 ; CHECK: ins {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
390 ; CHECK: mov {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
391391 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32>
392392 ret <8 x i8> %vset_lane
393393 }
394394
395395 define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
396396 ; CHECK-LABEL: test_vcopyq_laneq_s8:
397 ; CHECK: ins {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
397 ; CHECK: mov {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
398398 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32>
399399 ret <16 x i8> %vset_lane
400400 }
401401
402402 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
403403 ; CHECK-LABEL: test_vcopy_lane_swap_s8:
404 ; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
404 ; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
405405 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32>
406406 ret <8 x i8> %vset_lane
407407 }
408408
409409 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
410410 ; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
411 ; CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
411 ; CHECK: mov {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
412412 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32>
413413 ret <16 x i8> %vset_lane
414414 }
906906 ; CHECK-DAG: and [[MASKED_IDX:x[0-9]+]], x0, #0x7
907907 ; CHECK: bfi [[PTR:x[0-9]+]], [[MASKED_IDX]], #1, #3
908908 ; CHECK-DAG: ldr h[[R:[0-9]+]], {{\[}}[[PTR]]{{\]}}
909 ; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
910 ; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
911 ; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
909 ; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
910 ; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
911 ; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
912912 define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
913913 %tmp = extractelement <8 x i16> %x, i32 %idx
914914 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
926926 ; CHECK: bfi x9, [[MASKED_IDX]], #1, #2
927927 ; CHECK: st1 { v0.h }[0], [x9]
928928 ; CHECK-DAG: ldr d[[R:[0-9]+]]
929 ; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
930 ; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
931 ; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
929 ; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
930 ; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
931 ; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
932932 define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
933933 %tmp = extractelement <8 x i16> %x, i32 0
934934 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
11241124 ; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
11251125 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
11261126 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
1127 ; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}}
1127 ; CHECK: mov {{v[0-9]+}}.s[1], w{{[0-9]+}}
11281128 entry:
11291129 %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
11301130 %d = insertelement <2 x i32> undef, i32 %c, i32 0
11361136
11371137 define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
11381138 ; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
1139 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1139 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
11401140 entry:
11411141 %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32>
11421142 ret <16 x i8> %vecinit30
11441144
11451145 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
11461146 ; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
1147 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1147 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
11481148 entry:
11491149 %vecext = extractelement <8 x i8> %x, i32 0
11501150 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
11681168
11691169 define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
11701170 ; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
1171 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1171 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
11721172 entry:
11731173 %vecext = extractelement <16 x i8> %x, i32 0
11741174 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
12071207
12081208 define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
12091209 ; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
1210 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1210 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
12111211 entry:
12121212 %vecext = extractelement <8 x i8> %x, i32 0
12131213 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
12461246
12471247 define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
12481248 ; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
1249 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1249 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
12501250 entry:
12511251 %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32>
12521252 ret <8 x i16> %vecinit14
12541254
12551255 define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
12561256 ; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
1257 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1257 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
12581258 entry:
12591259 %vecext = extractelement <4 x i16> %x, i32 0
12601260 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
12701270
12711271 define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
12721272 ; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
1273 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1273 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
12741274 entry:
12751275 %vecext = extractelement <8 x i16> %x, i32 0
12761276 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
12931293
12941294 define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
12951295 ; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
1296 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1296 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
12971297 entry:
12981298 %vecext = extractelement <4 x i16> %x, i32 0
12991299 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
13161316
13171317 define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
13181318 ; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
1319 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1319 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
13201320 entry:
13211321 %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32>
13221322 ret <4 x i32> %vecinit6
13241324
13251325 define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
13261326 ; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
1327 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1327 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
13281328 entry:
13291329 %vecext = extractelement <2 x i32> %x, i32 0
13301330 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
13361336
13371337 define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
13381338 ; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
1339 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1339 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
13401340 entry:
13411341 %vecext = extractelement <4 x i32> %x, i32 0
13421342 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
13511351
13521352 define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
13531353 ; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
1354 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1354 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
13551355 entry:
13561356 %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32>
13571357 ret <4 x i32> %vecinit6
13881388
13891389 define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
13901390 ; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
1391 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1391 ; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
13921392 entry:
13931393 %vecext = extractelement <1 x i64> %x, i32 0
13941394 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
6767 define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
6868 ; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
6969 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
70 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
70 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
7171 ; CHECK-NEXT: ret
7272 entry:
7373 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
7979 define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
8080 ; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
8181 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
82 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
82 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
8383 ; CHECK-NEXT: ret
8484 entry:
8585 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
9191 define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
9292 ; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
9393 ; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
94 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
94 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
9595 ; CHECK-NEXT: ret
9696 entry:
9797 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
102102 define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
103103 ; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
104104 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
105 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
105 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
106106 ; CHECK-NEXT: ret
107107 entry:
108108 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
114114 define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
115115 ; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
116116 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
117 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
117 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
118118 ; CHECK-NEXT: ret
119119 entry:
120120 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
126126 define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
127127 ; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
128128 ; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
129 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
129 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
130130 ; CHECK-NEXT: ret
131131 entry:
132132 %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
6767 define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
6868 ; CHECK-LABEL: test_vminv_s8_used_by_laneop:
6969 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
70 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
70 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
7171 ; CHECK-NEXT: ret
7272 entry:
7373 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
7979 define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
8080 ; CHECK-LABEL: test_vminv_s16_used_by_laneop:
8181 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
82 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
82 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
8383 ; CHECK-NEXT: ret
8484 entry:
8585 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
9191 define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
9292 ; CHECK-LABEL: test_vminv_s32_used_by_laneop:
9393 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
94 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
94 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
9595 ; CHECK-NEXT: ret
9696 entry:
9797 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
102102 define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
103103 ; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
104104 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
105 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
105 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
106106 ; CHECK-NEXT: ret
107107 entry:
108108 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
114114 define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
115115 ; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
116116 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
117 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
117 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
118118 ; CHECK-NEXT: ret
119119 entry:
120120 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
126126 define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
127127 ; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
128128 ; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
129 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
129 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
130130 ; CHECK-NEXT: ret
131131 entry:
132132 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
125125 ; CHECK-LABEL: nosplat_v4i32:
126126 ; CHECK: str w0,
127127 ; CHECK: ldr q[[REG1:[0-9]+]],
128 ; CHECK-DAG: ins v[[REG1]].s[1], w0
129 ; CHECK-DAG: ins v[[REG1]].s[2], w0
130 ; CHECK-DAG: ins v[[REG1]].s[3], w0
128 ; CHECK-DAG: mov v[[REG1]].s[1], w0
129 ; CHECK-DAG: mov v[[REG1]].s[2], w0
130 ; CHECK-DAG: mov v[[REG1]].s[3], w0
131131 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
132132 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
133133 ; CHECK: ret
147147 entry:
148148
149149 ; CHECK-LABEL: nosplat2_v4i32:
150 ; CHECK: ins v[[REG1]].s[1], w0
151 ; CHECK-DAG: ins v[[REG1]].s[2], w0
152 ; CHECK-DAG: ins v[[REG1]].s[3], w0
150 ; CHECK: mov v[[REG1]].s[1], w0
151 ; CHECK-DAG: mov v[[REG1]].s[2], w0
152 ; CHECK-DAG: mov v[[REG1]].s[3], w0
153153 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
154154 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
155155 ; CHECK: ret
8888 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
8989 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
9090 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
91 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
91 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
9292 ; CHECK-NEXT: ret
9393 entry:
9494 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
100100 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
101101 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
102102 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
103 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
103 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
104104 ; CHECK-NEXT: ret
105105 entry:
106106 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
112112 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
113113 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
114114 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
115 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
115 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
116116 ; CHECK-NEXT: ret
117117 entry:
118118 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
123123 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
124124 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
125125 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
126 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
126 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
127127 ; CHECK-NEXT: ret
128128 entry:
129129 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
135135 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
136136 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
137137 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
138 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
138 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
139139 ; CHECK-NEXT: ret
140140 entry:
141141 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
147147 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
148148 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
149149 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
150 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
150 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
151151 ; CHECK-NEXT: ret
152152 entry:
153153 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
8888 define <8 x i8> @test_vminv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
8989 ; CHECK-LABEL: test_vminv_u8_used_by_laneop:
9090 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
91 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
91 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
9292 ; CHECK-NEXT: ret
9393 entry:
9494 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
100100 define <4 x i16> @test_vminv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
101101 ; CHECK-LABEL: test_vminv_u16_used_by_laneop:
102102 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
103 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
103 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
104104 ; CHECK-NEXT: ret
105105 entry:
106106 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2)
112112 define <2 x i32> @test_vminv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
113113 ; CHECK-LABEL: test_vminv_u32_used_by_laneop:
114114 ; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
115 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
115 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
116116 ; CHECK-NEXT: ret
117117 entry:
118118 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2)
123123 define <16 x i8> @test_vminvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
124124 ; CHECK-LABEL: test_vminvq_u8_used_by_laneop:
125125 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
126 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
126 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
127127 ; CHECK-NEXT: ret
128128 entry:
129129 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2)
135135 define <8 x i16> @test_vminvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
136136 ; CHECK-LABEL: test_vminvq_u16_used_by_laneop:
137137 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
138 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
138 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
139139 ; CHECK-NEXT: ret
140140 entry:
141141 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2)
147147 define <4 x i32> @test_vminvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
148148 ; CHECK-LABEL: test_vminvq_u32_used_by_laneop:
149149 ; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1
150 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
150 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
151151 ; CHECK-NEXT: ret
152152 entry:
153153 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2)
1313 define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
1414 ; CHECK-LABEL: test_vaddv_s8_used_by_laneop:
1515 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
16 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
16 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
1717 ; CHECK-NEXT: ret
1818 entry:
1919 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
3636 define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
3737 ; CHECK-LABEL: test_vaddv_s16_used_by_laneop:
3838 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
39 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
39 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
4040 ; CHECK-NEXT: ret
4141 entry:
4242 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
5959 define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
6060 ; CHECK-LABEL: test_vaddv_s32_used_by_laneop:
6161 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
62 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
62 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
6363 ; CHECK-NEXT: ret
6464 entry:
6565 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
8080 define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
8181 ; CHECK-LABEL: test_vaddv_s64_used_by_laneop:
8282 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
83 ; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
83 ; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
8484 ; CHECK-NEXT: ret
8585 entry:
8686 %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
102102 define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
103103 ; CHECK-LABEL: test_vaddv_u8_used_by_laneop:
104104 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
105 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
105 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
106106 ; CHECK-NEXT: ret
107107 entry:
108108 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)
136136 define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
137137 ; CHECK-LABEL: test_vaddv_u16_used_by_laneop:
138138 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
139 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
140140 ; CHECK-NEXT: ret
141141 entry:
142142 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)
170170 define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
171171 ; CHECK-LABEL: test_vaddv_u32_used_by_laneop:
172172 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
173 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
173 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
174174 ; CHECK-NEXT: ret
175175 entry:
176176 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)
219219 define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
220220 ; CHECK-LABEL: test_vaddv_u64_used_by_laneop:
221221 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
222 ; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
222 ; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
223223 ; CHECK-NEXT: ret
224224 entry:
225225 %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)
253253 define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
254254 ; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:
255255 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
256 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
256 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
257257 ; CHECK-NEXT: ret
258258 entry:
259259 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)
276276 define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
277277 ; CHECK-LABEL: test_vaddvq_s16_used_by_laneop:
278278 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
279 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
279 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
280280 ; CHECK-NEXT: ret
281281 entry:
282282 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)
298298 define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
299299 ; CHECK-LABEL: test_vaddvq_s32_used_by_laneop:
300300 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
301 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
301 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
302302 ; CHECK-NEXT: ret
303303 entry:
304304 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)
320320 define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
321321 ; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:
322322 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
323 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
323 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
324324 ; CHECK-NEXT: ret
325325 entry:
326326 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)
343343 define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
344344 ; CHECK-LABEL: test_vaddvq_u16_used_by_laneop:
345345 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
346 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
346 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
347347 ; CHECK-NEXT: ret
348348 entry:
349349 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)
365365 define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
366366 ; CHECK-LABEL: test_vaddvq_u32_used_by_laneop:
367367 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
368 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
368 ; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
369369 ; CHECK-NEXT: ret
370370 entry:
371371 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)
55 define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
66 entry:
77 ; CHECK-LABEL: test:
8 ; CHECK: ins.d v0[1], v1[0]
8 ; CHECK: mov.d v0[1], v1[0]
99 %0 = bitcast <16 x i8> %q0 to <2 x i64>
1010 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
1111 %1 = bitcast <16 x i8> %q1 to <2 x i64>
88
99 ; CHECK-LABEL: test0f
1010 ; CHECK: movi.2d v[[TEMP:[0-9]+]], #0000000000000000
11 ; CHECK: ins.s v[[TEMP]][0], v{{[0-9]+}}[0]
11 ; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
1212 ; CHECK: str q[[TEMP]], [x0]
1313 ; CHECK: ret
1414
2626 ; CHECK-LABEL: test1f
2727 ; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000
2828 ; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0]
29 ; CHECK: ins.s v[[TEMP2]][0], v0[0]
29 ; CHECK: mov.s v[[TEMP2]][0], v0[0]
3030 ; CHECK: str q[[TEMP2]], [x0]
3131 ; CHECK: ret
3232 }
1010 ; CHECK-DAG: fmov s0, [[REG2]]
1111 ; CHECK-DAG: mov [[REG3:w[0-9]+]], v0.s[1]
1212 ; CHECK-DAG: rbit [[REG4:w[0-9]+]], [[REG3]]
13 ; CHECK-DAG: ins v0.s[1], [[REG4]]
13 ; CHECK-DAG: mov v0.s[1], [[REG4]]
1414 ; CHECK-DAG: ushr v0.2s, v0.2s, #16
1515 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
1616 ret <2 x i16> %b
3737 define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 {
3838 entry:
3939 ; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8:
40 ; CHECK-NEXT: fmov s0, w0
41 ; CHECK-NEXT: ins.h v0[1], w1
42 ; CHECK-NEXT: ins.h v0[3], w1
40 ; CHECK-NEXT: fmov s0, w0
41 ; CHECK-NEXT: mov.h v0[1], w1
42 ; CHECK-NEXT: mov.h v0[3], w1
4343 ; CHECK-NEXT: ret
4444 %tx = trunc i32 %x to i16
4545 %ty = trunc i32 %y to i16
5353 entry:
5454 ; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup:
5555 ; CHECK-NEXT: fmov s0, w1
56 ; CHECK-NEXT: ins.s v0[1], w0
56 ; CHECK-NEXT: mov.s v0[1], w0
5757 ; CHECK-NEXT: ret
5858 %bx = bitcast i32 %x to <4 x i8>
5959 %by = bitcast i32 %y to <4 x i8>
6565 entry:
6666 ; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup:
6767 ; CHECK-NEXT: fmov s0, w0
68 ; CHECK-NEXT: ins.s v0[1], w1
69 ; CHECK-NEXT: ins.s v0[2], w1
70 ; CHECK-NEXT: ins.s v0[3], w0
68 ; CHECK-NEXT: mov.s v0[1], w1
69 ; CHECK-NEXT: mov.s v0[2], w1
70 ; CHECK-NEXT: mov.s v0[3], w0
7171 ; CHECK-NEXT: ret
7272 %bx = bitcast i32 %x to <2 x i16>
7373 %by = bitcast i32 %y to <2 x i16>
8484 ; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8:
8585 ; CHECK-NEXT: fmov s[[X:[0-9]+]], w0
8686 ; CHECK-NEXT: mov.16b v0, v[[X]]
87 ; CHECK-NEXT: ins.h v0[1], v1[0]
88 ; CHECK-NEXT: ins.h v0[2], v[[X]][0]
89 ; CHECK-NEXT: ins.h v0[3], v1[0]
87 ; CHECK-NEXT: mov.h v0[1], v1[0]
88 ; CHECK-NEXT: mov.h v0[2], v[[X]][0]
89 ; CHECK-NEXT: mov.h v0[3], v1[0]
9090 ; CHECK-NEXT: ret
9191 %t = trunc i32 %x to i16
9292 %0 = bitcast i16 %t to <2 x i8>
9999 entry:
100100 ; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8:
101101 ; CHECK-NEXT: mov.16b v0, v1
102 ; CHECK-NEXT: ins.h v0[1], v2[0]
103 ; CHECK-NEXT: ins.h v0[2], v1[0]
104 ; CHECK-NEXT: ins.h v0[3], v2[0]
102 ; CHECK-NEXT: mov.h v0[1], v2[0]
103 ; CHECK-NEXT: mov.h v0[2], v1[0]
104 ; CHECK-NEXT: mov.h v0[3], v2[0]
105105 ; CHECK-NEXT: ret
106106 %0 = bitcast half %x to <2 x i8>
107107 %y0 = bitcast half %y to <2 x i8>
1010 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
1111 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
1212 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
13 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
14 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
13 ; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
14 ; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
1515
1616 %1 = sitofp <16 x i32> %a to <16 x half>
1717 ret <16 x half> %1
4343 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
4444 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
4545 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
46 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
47 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
46 ; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
47 ; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
4848
4949 %1 = sitofp <16 x i64> %a to <16 x half>
5050 ret <16 x half> %1
6161 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
6262 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
6363 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
64 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
65 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
64 ; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
65 ; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
6666
6767 %1 = uitofp <16 x i32> %a to <16 x half>
6868 ret <16 x half> %1
9494 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
9595 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
9696 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
97 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
98 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
97 ; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
98 ; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
9999
100100 %1 = uitofp <16 x i64> %a to <16 x half>
101101 ret <16 x half> %1
101101 }
102102
103103 define <4 x half> @d_to_h(<4 x double> %a) {
104 ; CHECK-COMMON-LABEL: d_to_h:
105 ; CHECK-COMMON: mov
106 ; CHECK-COMMON: fcvt
107 ; CHECK-COMMON: fcvt
108 ; CHECK-COMMON: fcvt
109 ; CHECK-COMMON: mov
110 ; CHECK-COMMON: ins
111 ; CHECK-COMMON: ins
112 ; CHECK-COMMON: fcvt
113 ; CHECK-COMMON: ins
114 ; CHECK-COMMON: ret
104 ; CHECK-LABEL: d_to_h:
105 ; CHECK-DAG: fcvt h
106 ; CHECK-DAG: fcvt h
107 ; CHECK-DAG: fcvt h
108 ; CHECK-DAG: fcvt h
109 ; CHECK-DAG: mov v{{[0-9]+}}.h
110 ; CHECK-DAG: mov v{{[0-9]+}}.h
111 ; CHECK-DAG: mov v{{[0-9]+}}.h
112 ; CHECK-DAG: mov v{{[0-9]+}}.h
115113 %1 = fptrunc <4 x double> %a to <4 x half>
116114 ret <4 x half> %1
117115 }
125123 }
126124
127125 define <4 x double> @h_to_d(<4 x half> %a) {
128 ; CHECK-COMMON-LABEL: h_to_d:
129 ; CHECK-COMMON: mov
130 ; CHECK-COMMON: fcvt
131 ; CHECK-COMMON: mov
132 ; CHECK-COMMON: mov
133 ; CHECK-COMMON: fcvt
134 ; CHECK-COMMON: fcvt
135 ; CHECK-COMMON: fcvt
136 ; CHECK-COMMON: ins
137 ; CHECK-COMMON: ins
138 ; CHECK-COMMON: mov
139 ; CHECK-COMMON: ret
126 ; CHECK-LABEL: h_to_d:
127 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
128 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
129 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
130 ; CHECK-DAG: fcvt
131 ; CHECK-DAG: fcvt
132 ; CHECK-DAG: fcvt
133 ; CHECK-DAG: fcvt
140134 %1 = fpext <4 x half> %a to <4 x double>
141135 ret <4 x double> %1
142136 }
201201 ; CHECK-LABEL: s_to_h:
202202 ; CHECK-DAG: fcvtn v0.4h, v0.4s
203203 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
204 ; CHECK: ins v0.d[1], [[REG]].d[0]
204 ; CHECK: mov v0.d[1], [[REG]].d[0]
205205 %1 = fptrunc <8 x float> %a to <8 x half>
206206 ret <8 x half> %1
207207 }
220220 ; CHECK-DAG: fcvt h
221221 ; CHECK-DAG: fcvt h
222222 ; CHECK-DAG: fcvt h
223 ; CHECK-DAG: ins v{{[0-9]+}}.h
224 ; CHECK-DAG: ins v{{[0-9]+}}.h
225 ; CHECK-DAG: ins v{{[0-9]+}}.h
226 ; CHECK-DAG: ins v{{[0-9]+}}.h
227 ; CHECK-DAG: ins v{{[0-9]+}}.h
228 ; CHECK-DAG: ins v{{[0-9]+}}.h
229 ; CHECK-DAG: ins v{{[0-9]+}}.h
230 ; CHECK-DAG: ins v{{[0-9]+}}.h
223 ; CHECK-DAG: mov v{{[0-9]+}}.h
224 ; CHECK-DAG: mov v{{[0-9]+}}.h
225 ; CHECK-DAG: mov v{{[0-9]+}}.h
226 ; CHECK-DAG: mov v{{[0-9]+}}.h
227 ; CHECK-DAG: mov v{{[0-9]+}}.h
228 ; CHECK-DAG: mov v{{[0-9]+}}.h
229 ; CHECK-DAG: mov v{{[0-9]+}}.h
230 ; CHECK-DAG: mov v{{[0-9]+}}.h
231231 %1 = fptrunc <8 x double> %a to <8 x half>
232232 ret <8 x half> %1
233233 }
242242
243243 define <8 x double> @h_to_d(<8 x half> %a) {
244244 ; CHECK-LABEL: h_to_d:
245 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
246 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
247 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
248 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
249 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
250 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
251 ; CHECK-DAG: mov h{{[0-9]+}}, v0.h
245252 ; CHECK-DAG: fcvt d
246253 ; CHECK-DAG: fcvt d
247254 ; CHECK-DAG: fcvt d
250257 ; CHECK-DAG: fcvt d
251258 ; CHECK-DAG: fcvt d
252259 ; CHECK-DAG: fcvt d
253 ; CHECK-DAG: ins
254 ; CHECK-DAG: ins
255 ; CHECK-DAG: ins
256 ; CHECK-DAG: ins
257260 %1 = fpext <8 x half> %a to <8 x double>
258261 ret <8 x double> %1
259262 }
283286 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
284287 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
285288 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
286 ; CHECK: ins v0.d[1], v[[LOREG]].d[0]
289 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
287290 %1 = sitofp <8 x i8> %a to <8 x half>
288291 ret <8 x half> %1
289292 }
297300 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
298301 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
299302 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
300 ; CHECK: ins v0.d[1], v[[LOREG]].d[0]
303 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
301304 %1 = sitofp <8 x i16> %a to <8 x half>
302305 ret <8 x half> %1
303306 }
309312 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
310313 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
311314 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
312 ; CHECK: ins v0.d[1], v[[REG]].d[0]
315 ; CHECK: mov v0.d[1], v[[REG]].d[0]
313316 %1 = sitofp <8 x i32> %a to <8 x half>
314317 ret <8 x half> %1
315318 }
335338 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
336339 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
337340 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
338 ; CHECK: ins v0.d[1], v[[LOREG]].d[0]
341 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
339342 %1 = uitofp <8 x i8> %a to <8 x half>
340343 ret <8 x half> %1
341344 }
349352 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
350353 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
351354 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
352 ; CHECK: ins v0.d[1], v[[LOREG]].d[0]
355 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
353356 %1 = uitofp <8 x i16> %a to <8 x half>
354357 ret <8 x half> %1
355358 }
361364 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
362365 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
363366 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
364 ; CHECK: ins v0.d[1], v[[REG]].d[0]
367 ; CHECK: mov v0.d[1], v[[REG]].d[0]
365368 %1 = uitofp <8 x i32> %a to <8 x half>
366369 ret <8 x half> %1
367370 }
3434 ; }
3535 define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {
3636 ; CHECK-LABEL: lane_64_64:
37 ; CHECK: ins
37 ; CHECK: mov v{{[0-9]+}}.h
3838 entry:
3939 %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32>
4040 ret <4 x half> %0
4545 ; }
4646 define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {
4747 ; CHECK-LABEL: lane_128_64:
48 ; CHECK: ins
48 ; CHECK: mov v{{[0-9]+}}.h
4949 entry:
5050 %0 = bitcast <4 x half> %b to <4 x i16>
5151 %vget_lane = extractelement <4 x i16> %0, i32 2
6060 ; }
6161 define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {
6262 ; CHECK-LABEL: lane_64_128:
63 ; CHECK: ins
63 ; CHECK: mov v{{[0-9]+}}.h
6464 entry:
6565 %0 = bitcast <8 x half> %b to <8 x i16>
6666 %vgetq_lane = extractelement <8 x i16> %0, i32 5
7575 ; }
7676 define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {
7777 ; CHECK-LABEL: lane_128_128:
78 ; CHECK: ins
78 ; CHECK: mov v{{[0-9]+}}.h
7979 entry:
8080 %0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32>
8181 ret <8 x half> %0
224224 define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
225225 entry:
226226 ; CHECK-LABEL: vcombine:
227 ; CHECK: ins
227 ; CHECK: mov v0.d[1], v1.d[0]
228228 %shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32>
229229 ret <8 x half> %shuffle.i
230230 }
252252 define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {
253253 ; CHECK-LABEL: set_lane_64:
254254 ; CHECK: fmov
255 ; CHECK: ins
255 ; CHECK: mov v{{[0-9]+}}.h
256256 entry:
257257 %0 = bitcast half %b to i16
258258 %1 = bitcast <4 x half> %a to <4 x i16>
266266 define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {
267267 ; CHECK-LABEL: set_lane_128:
268268 ; CHECK: fmov
269 ; CHECK: ins
269 ; CHECK: mov v{{[0-9]+}}.h
270270 entry:
271271 %0 = bitcast half %b to i16
272272 %1 = bitcast <8 x half> %a to <8 x i16>
105105 ; CHECK-NEXT: bit.16b v3, v1, v4
106106 ; CHECK-NEXT: mov d1, v2[1]
107107 ; CHECK-NEXT: fcvt s1, d1
108 ; CHECK-NEXT: ins.s v0[1], v3[0]
109 ; CHECK-NEXT: ins.s v0[2], v6[0]
108 ; CHECK-NEXT: mov.s v0[1], v3[0]
109 ; CHECK-NEXT: mov.s v0[2], v6[0]
110110 ; CHECK-NEXT: bit.16b v7, v1, v4
111 ; CHECK-NEXT: ins.s v0[3], v7[0]
111 ; CHECK-NEXT: mov.s v0[3], v7[0]
112112 ; CHECK-NEXT: ret
113113 %tmp0 = fptrunc <4 x double> %b to <4 x float>
114114 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)
219219 ins v2.h[1], w5
220220 ins v2.b[1], w5
221221
222 ; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
223 ; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
224 ; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
225 ; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
226
227 ; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
228 ; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
229 ; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
230 ; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
222 ; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
223 ; CHECK: mov.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
224 ; CHECK: mov.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
225 ; CHECK: mov.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
226
227 ; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
228 ; CHECK: mov.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
229 ; CHECK: mov.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
230 ; CHECK: mov.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
231231
232232 ins.d v2[1], v15[1]
233233 ins.s v2[1], v15[1]
239239 ins v2.h[7], v15.h[3]
240240 ins v2.b[10], v15.b[5]
241241
242 ; CHECK: ins.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]
243 ; CHECK: ins.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]
244 ; CHECK: ins.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]
245 ; CHECK: ins.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]
246
247 ; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
248 ; CHECK: ins.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]
249 ; CHECK: ins.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]
250 ; CHECK: ins.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]
242 ; CHECK: mov.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]
243 ; CHECK: mov.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]
244 ; CHECK: mov.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]
245 ; CHECK: mov.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]
246
247 ; CHECK: mov.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
248 ; CHECK: mov.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]
249 ; CHECK: mov.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]
250 ; CHECK: mov.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]
251251
252252 ; MOV aliases for the above INS instructions.
253253 mov.d v2[1], x5
270270 mov v8.h[7], v17.h[3]
271271 mov v9.b[10], v18.b[5]
272272
273 ; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
274 ; CHECK: ins.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]
275 ; CHECK: ins.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]
276 ; CHECK: ins.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]
277 ; CHECK: ins.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]
278 ; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]
279 ; CHECK: ins.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]
280 ; CHECK: ins.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]
281 ; CHECK: ins.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]
282 ; CHECK: ins.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]
283 ; CHECK: ins.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]
284 ; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]
285 ; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
286 ; CHECK: ins.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]
287 ; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]
288 ; CHECK: ins.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]
273 ; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
274 ; CHECK: mov.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]
275 ; CHECK: mov.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]
276 ; CHECK: mov.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]
277 ; CHECK: mov.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]
278 ; CHECK: mov.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]
279 ; CHECK: mov.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]
280 ; CHECK: mov.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]
281 ; CHECK: mov.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]
282 ; CHECK: mov.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]
283 ; CHECK: mov.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]
284 ; CHECK: mov.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]
285 ; CHECK: mov.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
286 ; CHECK: mov.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]
287 ; CHECK: mov.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]
288 ; CHECK: mov.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]
289289
290290
291291 and.8b v0, v0, v0
138138 0xa2 0x1c 0x06 0x4e
139139 0xa2 0x1c 0x03 0x4e
140140
141 # CHECK: ins.d v2[1], x5
142 # CHECK: ins.s v2[1], w5
143 # CHECK: ins.h v2[1], w5
144 # CHECK: ins.b v2[1], w5
145
146 # CHECK: ins.d v2[1], x5
147 # CHECK: ins.s v2[1], w5
148 # CHECK: ins.h v2[1], w5
149 # CHECK: ins.b v2[1], w5
141 # CHECK: mov.d v2[1], x5
142 # CHECK: mov.s v2[1], w5
143 # CHECK: mov.h v2[1], w5
144 # CHECK: mov.b v2[1], w5
145
146 # CHECK: mov.d v2[1], x5
147 # CHECK: mov.s v2[1], w5
148 # CHECK: mov.h v2[1], w5
149 # CHECK: mov.b v2[1], w5
150150
151151 0xe2 0x45 0x18 0x6e
152152 0xe2 0x25 0x0c 0x6e
158158 0xe2 0x35 0x1e 0x6e
159159 0xe2 0x2d 0x15 0x6e
160160
161 # CHECK: ins.d v2[1], v15[1]
162 # CHECK: ins.s v2[1], v15[1]
163 # CHECK: ins.h v2[1], v15[1]
164 # CHECK: ins.b v2[1], v15[1]
165
166 # CHECK: ins.d v2[1], v15[0]
167 # CHECK: ins.s v2[3], v15[2]
168 # CHECK: ins.h v2[7], v15[3]
169 # CHECK: ins.b v2[10], v15[5]
161 # CHECK: mov.d v2[1], v15[1]
162 # CHECK: mov.s v2[1], v15[1]
163 # CHECK: mov.h v2[1], v15[1]
164 # CHECK: mov.b v2[1], v15[1]
165
166 # CHECK: mov.d v2[1], v15[0]
167 # CHECK: mov.s v2[3], v15[2]
168 # CHECK: mov.h v2[7], v15[3]
169 # CHECK: mov.b v2[10], v15[5]
170170
171171 # INS/DUP (non-standard)
172172 0x60 0x0c 0x08 0x4e
195195 0xe2 0x35 0x1e 0x6e
196196 0xe2 0x2d 0x15 0x6e
197197
198 # CHECK: ins.d v2[1], v15[1]
199 # CHECK: ins.s v2[1], v15[1]
200 # CHECK: ins.h v2[1], v15[1]
201 # CHECK: ins.b v2[1], v15[1]
202
203 # CHECK: ins.d v2[1], v15[0]
204 # CHECK: ins.s v2[3], v15[2]
205 # CHECK: ins.h v2[7], v15[3]
206 # CHECK: ins.b v2[10], v15[5]
198 # CHECK: mov.d v2[1], v15[1]
199 # CHECK: mov.s v2[1], v15[1]
200 # CHECK: mov.h v2[1], v15[1]
201 # CHECK: mov.b v2[1], v15[1]
202
203 # CHECK: mov.d v2[1], v15[0]
204 # CHECK: mov.s v2[3], v15[2]
205 # CHECK: mov.h v2[7], v15[3]
206 # CHECK: mov.b v2[10], v15[5]
207207
208208 0x00 0x1c 0x20 0x0e
209209 0x00 0x1c 0x20 0x4e
819819 }
820820
821821 unsigned NumMIOps = 0;
822 for (auto &Operand : CGA.ResultOperands)
823 NumMIOps += Operand.getMINumOperands();
822 for (auto &ResultInstOpnd : CGA.ResultInst->Operands)
823 NumMIOps += ResultInstOpnd.MINumOperands;
824824
825825 std::string Cond;
826826 Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
830830
831831 unsigned MIOpNum = 0;
832832 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
833 // Skip over tied operands as they're not part of an alias declaration.
834 auto &Operands = CGA.ResultInst->Operands;
835 unsigned OpNum = Operands.getSubOperandNumber(MIOpNum).first;
836 if (Operands[OpNum].MINumOperands == 1 &&
837 Operands[OpNum].getTiedRegister() != -1) {
838 // Tied operands of different RegisterClass should be explicit within
839 // an instruction's syntax and so cannot be skipped.
840 int TiedOpNum = Operands[OpNum].getTiedRegister();
841 if (Operands[OpNum].Rec->getName() ==
842 Operands[TiedOpNum].Rec->getName())
843 ++MIOpNum;
844 }
845
833846 std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";
834847
835848 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];