llvm.org GIT mirror llvm / b2e9db4
Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook." This reverts commit r212851, because it broke the memset lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212855 91177308-0d34-0410-b5e6-96231b3b80d8 Juergen Ributzka 5 years ago
1 changed file(s) with 53 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
7373 const LoadInst *LI) override;
7474
7575 bool FastLowerArguments() override;
76 bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
7776
7877 #include "X86GenFastISel.inc"
7978
124123 bool X86SelectFPExt(const Instruction *I);
125124 bool X86SelectFPTrunc(const Instruction *I);
126125
126 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
127127 bool X86SelectCall(const Instruction *I);
128128
129129 bool DoSelectCall(const Instruction *I, const char *MemIntName);
21652165 return true;
21662166 }
21672167
2168 static bool isCommutativeIntrinsic(IntrinsicInst const *II) {
2169 switch (II->getIntrinsicID()) {
2168 static bool isCommutativeIntrinsic(IntrinsicInst const &I) {
2169 switch (I.getIntrinsicID()) {
21702170 case Intrinsic::sadd_with_overflow:
21712171 case Intrinsic::uadd_with_overflow:
21722172 case Intrinsic::smul_with_overflow:
21772177 }
21782178 }
21792179
2180 bool X86FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
2180 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
21812181 // FIXME: Handle more intrinsics.
2182 switch (II->getIntrinsicID()) {
2182 switch (I.getIntrinsicID()) {
21832183 default: return false;
21842184 case Intrinsic::frameaddress: {
2185 Type *RetTy = II->getCalledFunction()->getReturnType();
2185 Type *RetTy = I.getCalledFunction()->getReturnType();
21862186
21872187 MVT VT;
21882188 if (!isTypeLegal(RetTy, VT))
22222222 // movq (%rax), %rax
22232223 // ...
22242224 unsigned DestReg;
2225 unsigned Depth = cast(II->getOperand(0))->getZExtValue();
2225 unsigned Depth = cast(I.getOperand(0))->getZExtValue();
22262226 while (Depth--) {
22272227 DestReg = createResultReg(RC);
22282228 addDirectMem(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
22302230 SrcReg = DestReg;
22312231 }
22322232
2233 UpdateValueMap(II, SrcReg);
2233 UpdateValueMap(&I, SrcReg);
22342234 return true;
22352235 }
22362236 case Intrinsic::memcpy: {
2237 const MemCpyInst *MCI = cast(II);
2237 const MemCpyInst &MCI = cast(I);
22382238 // Don't handle volatile or variable length memcpys.
2239 if (MCI->isVolatile())
2240 return false;
2241
2242 if (isa(MCI->getLength())) {
2239 if (MCI.isVolatile())
2240 return false;
2241
2242 if (isa(MCI.getLength())) {
22432243 // Small memcpy's are common enough that we want to do them
22442244 // without a call if possible.
2245 uint64_t Len = cast(MCI->getLength())->getZExtValue();
2245 uint64_t Len = cast(MCI.getLength())->getZExtValue();
22462246 if (IsMemcpySmall(Len)) {
22472247 X86AddressMode DestAM, SrcAM;
2248 if (!X86SelectAddress(MCI->getRawDest(), DestAM) ||
2249 !X86SelectAddress(MCI->getRawSource(), SrcAM))
2248 if (!X86SelectAddress(MCI.getRawDest(), DestAM) ||
2249 !X86SelectAddress(MCI.getRawSource(), SrcAM))
22502250 return false;
22512251 TryEmitSmallMemcpy(DestAM, SrcAM, Len);
22522252 return true;
22542254 }
22552255
22562256 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2257 if (!MCI->getLength()->getType()->isIntegerTy(SizeWidth))
2258 return false;
2259
2260 if (MCI->getSourceAddressSpace() > 255 || MCI->getDestAddressSpace() > 255)
2261 return false;
2262
2263 return LowerCallTo(II, "memcpy", II->getNumArgOperands() - 2);
2257 if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth))
2258 return false;
2259
2260 if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255)
2261 return false;
2262
2263 return DoSelectCall(&I, "memcpy");
22642264 }
22652265 case Intrinsic::memset: {
2266 const MemSetInst *MSI = cast(II);
2267
2268 if (MSI->isVolatile())
2266 const MemSetInst &MSI = cast(I);
2267
2268 if (MSI.isVolatile())
22692269 return false;
22702270
22712271 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2272 if (!MSI->getLength()->getType()->isIntegerTy(SizeWidth))
2273 return false;
2274
2275 if (MSI->getDestAddressSpace() > 255)
2276 return false;
2277
2278 return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
2272 if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth))
2273 return false;
2274
2275 if (MSI.getDestAddressSpace() > 255)
2276 return false;
2277
2278 return DoSelectCall(&I, "memset");
22792279 }
22802280 case Intrinsic::stackprotector: {
22812281 // Emit code to store the stack guard onto the stack.
22822282 EVT PtrTy = TLI.getPointerTy();
22832283
2284 const Value *Op1 = II->getArgOperand(0); // The guard's value.
2285 const AllocaInst *Slot = cast(II->getArgOperand(1));
2284 const Value *Op1 = I.getArgOperand(0); // The guard's value.
2285 const AllocaInst *Slot = cast(I.getArgOperand(1));
22862286
22872287 MFI.setStackProtectorIndex(FuncInfo.StaticAllocaMap[Slot]);
22882288
22932293 return true;
22942294 }
22952295 case Intrinsic::dbg_declare: {
2296 const DbgDeclareInst *DI = cast(II);
2296 const DbgDeclareInst *DI = cast(&I);
22972297 X86AddressMode AM;
22982298 assert(DI->getAddress() && "Null address should be checked earlier!");
22992299 if (!X86SelectAddress(DI->getAddress(), AM))
23132313 if (!Subtarget->hasSSE1())
23142314 return false;
23152315
2316 Type *RetTy = II->getCalledFunction()->getReturnType();
2316 Type *RetTy = I.getCalledFunction()->getReturnType();
23172317
23182318 MVT VT;
23192319 if (!isTypeLegal(RetTy, VT))
23352335 case MVT::f64: Opc = SqrtOpc[1][HasAVX]; RC = &X86::FR64RegClass; break;
23362336 }
23372337
2338 const Value *SrcVal = II->getArgOperand(0);
2338 const Value *SrcVal = I.getArgOperand(0);
23392339 unsigned SrcReg = getRegForValue(SrcVal);
23402340
23412341 if (SrcReg == 0)
23582358
23592359 MIB.addReg(SrcReg);
23602360
2361 UpdateValueMap(II, ResultReg);
2361 UpdateValueMap(&I, ResultReg);
23622362 return true;
23632363 }
23642364 case Intrinsic::sadd_with_overflow:
23692369 case Intrinsic::umul_with_overflow: {
23702370 // This implements the basic lowering of the xalu with overflow intrinsics
23712371 // into add/sub/mul followed by either seto or setb.
2372 const Function *Callee = II->getCalledFunction();
2372 const Function *Callee = I.getCalledFunction();
23732373 auto *Ty = cast(Callee->getReturnType());
23742374 Type *RetTy = Ty->getTypeAtIndex(0U);
23752375 Type *CondTy = Ty->getTypeAtIndex(1);
23812381 if (VT < MVT::i8 || VT > MVT::i64)
23822382 return false;
23832383
2384 const Value *LHS = II->getArgOperand(0);
2385 const Value *RHS = II->getArgOperand(1);
2384 const Value *LHS = I.getArgOperand(0);
2385 const Value *RHS = I.getArgOperand(1);
23862386
23872387 // Canonicalize immediate to the RHS.
23882388 if (isa(LHS) && !isa(RHS) &&
2389 isCommutativeIntrinsic(II))
2389 isCommutativeIntrinsic(I))
23902390 std::swap(LHS, RHS);
23912391
23922392 unsigned BaseOpc, CondOpc;
2393 switch (II->getIntrinsicID()) {
2393 switch (I.getIntrinsicID()) {
23942394 default: llvm_unreachable("Unexpected intrinsic!");
23952395 case Intrinsic::sadd_with_overflow:
23962396 BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break;
24672467 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
24682468 ResultReg2);
24692469
2470 UpdateValueMap(II, ResultReg, 2);
2470 UpdateValueMap(&I, ResultReg, 2);
24712471 return true;
24722472 }
24732473 case Intrinsic::x86_sse_cvttss2si:
24752475 case Intrinsic::x86_sse2_cvttsd2si:
24762476 case Intrinsic::x86_sse2_cvttsd2si64: {
24772477 bool IsInputDouble;
2478 switch (II->getIntrinsicID()) {
2478 switch (I.getIntrinsicID()) {
24792479 default: llvm_unreachable("Unexpected intrinsic.");
24802480 case Intrinsic::x86_sse_cvttss2si:
24812481 case Intrinsic::x86_sse_cvttss2si64:
24912491 break;
24922492 }
24932493
2494 Type *RetTy = II->getCalledFunction()->getReturnType();
2494 Type *RetTy = I.getCalledFunction()->getReturnType();
24952495 MVT VT;
24962496 if (!isTypeLegal(RetTy, VT))
24972497 return false;
25112511 }
25122512
25132513 // Check if we can fold insertelement instructions into the convert.
2514 const Value *Op = II->getArgOperand(0);
2514 const Value *Op = I.getArgOperand(0);
25152515 while (auto *IE = dyn_cast(Op)) {
25162516 const Value *Index = IE->getOperand(2);
25172517 if (!isa(Index))
25332533 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
25342534 .addReg(Reg);
25352535
2536 UpdateValueMap(II, ResultReg);
2536 UpdateValueMap(&I, ResultReg);
25372537 return true;
25382538 }
25392539 }
26412641 // Can't handle inline asm yet.
26422642 if (isa(Callee))
26432643 return false;
2644
2645 // Handle intrinsic calls.
2646 if (const IntrinsicInst *II = dyn_cast(CI))
2647 return X86VisitIntrinsicCall(*II);
26442648
26452649 // Allow SelectionDAG isel to handle tail calls.
26462650 if (cast(I)->isTailCall())