llvm.org GIT mirror llvm / b2e69d9
ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures. There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276013 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 3 years ago
2 changed file(s) with 31 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
294294 FeatureV7Clrex]>;
295295 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
296296 "Support ARM v8 instructions",
297 [HasV7Ops, FeatureAcquireRelease]>;
297 [HasV7Ops, FeatureAcquireRelease,
298 FeatureT2XtPk]>;
298299 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
299300 "Support ARM v8.1a instructions",
300301 [HasV8Ops]>;
387388 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
388389
389390 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
390 FeatureDSP]>;
391 FeatureDSP,
392 FeatureT2XtPk]>;
391393
392394 def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
393395
408410 FeatureNEON,
409411 FeatureDB,
410412 FeatureDSP,
411 FeatureAClass]>;
413 FeatureAClass,
414 FeatureT2XtPk]>;
412415
413416 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
414417 FeatureDB,
415418 FeatureDSP,
416419 FeatureHWDiv,
417 FeatureRClass]>;
420 FeatureRClass,
421 FeatureT2XtPk]>;
418422
419423 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
420424 FeatureThumb2,
569573 FeatureSlowFPBrcc,
570574 FeatureHasSlowFPVMLx,
571575 FeatureVMLxForwarding,
572 FeatureT2XtPk,
573576 FeatureMP,
574577 FeatureVFP4]>;
575578
580583 FeatureHasVMLxHazards,
581584 FeatureHasSlowFPVMLx,
582585 FeatureVMLxForwarding,
583 FeatureT2XtPk,
584586 FeatureMP,
585587 FeatureVFP4,
586588 FeatureHWDiv,
594596 FeatureSlowFPBrcc,
595597 FeatureHasVMLxHazards,
596598 FeatureHasSlowFPVMLx,
597 FeatureVMLxForwarding,
598 FeatureT2XtPk]>;
599 FeatureVMLxForwarding]>;
599600
600601 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
601602 FeatureHasRetAddrStack,
602603 FeatureTrustZone,
603604 FeatureHasVMLxHazards,
604605 FeatureVMLxForwarding,
605 FeatureT2XtPk,
606606 FeatureFP16,
607607 FeatureAvoidPartialCPSR,
608608 FeatureExpandMLx,
617617 FeatureHasRetAddrStack,
618618 FeatureTrustZone,
619619 FeatureVMLxForwarding,
620 FeatureT2XtPk,
621620 FeatureVFP4,
622621 FeatureHWDiv,
623622 FeatureHWDivARM,
631630 FeatureHasRetAddrStack,
632631 FeatureMuxedUnits,
633632 FeatureTrustZone,
634 FeatureT2XtPk,
635633 FeatureVFP4,
636634 FeatureMP,
637635 FeatureCheckVLDnAlign,
646644 FeatureTrustZone,
647645 FeatureMP,
648646 FeatureVMLxForwarding,
649 FeatureT2XtPk,
650647 FeatureVFP4,
651648 FeatureHWDiv,
652649 FeatureHWDivARM,
661658 FeatureMuxedUnits,
662659 FeatureCheckVLDnAlign,
663660 FeatureVMLxForwarding,
664 FeatureT2XtPk,
665661 FeatureFP16,
666662 FeatureAvoidPartialCPSR,
667663 FeatureVFP4,
671667 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
672668 FeatureHasRetAddrStack,
673669 FeatureNEONForFP,
674 FeatureT2XtPk,
675670 FeatureVFP4,
676671 FeatureMP,
677672 FeatureHWDiv,
690685 // FIXME: R4 has currently the same ProcessorModel as A8.
691686 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
692687 FeatureHasRetAddrStack,
693 FeatureAvoidPartialCPSR,
694 FeatureT2XtPk]>;
688 FeatureAvoidPartialCPSR]>;
695689
696690 // FIXME: R4F has currently the same ProcessorModel as A8.
697691 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
700694 FeatureHasSlowFPVMLx,
701695 FeatureVFP3,
702696 FeatureD16,
703 FeatureAvoidPartialCPSR,
704 FeatureT2XtPk]>;
697 FeatureAvoidPartialCPSR]>;
705698
706699 // FIXME: R5 has currently the same ProcessorModel as A8.
707700 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
711704 FeatureSlowFPBrcc,
712705 FeatureHWDivARM,
713706 FeatureHasSlowFPVMLx,
714 FeatureAvoidPartialCPSR,
715 FeatureT2XtPk]>;
707 FeatureAvoidPartialCPSR]>;
716708
717709 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
718710 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
724716 FeatureSlowFPBrcc,
725717 FeatureHWDivARM,
726718 FeatureHasSlowFPVMLx,
727 FeatureAvoidPartialCPSR,
728 FeatureT2XtPk]>;
719 FeatureAvoidPartialCPSR]>;
729720
730721 def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
731722 FeatureHasRetAddrStack,
736727 FeatureSlowFPBrcc,
737728 FeatureHWDivARM,
738729 FeatureHasSlowFPVMLx,
739 FeatureAvoidPartialCPSR,
740 FeatureT2XtPk]>;
730 FeatureAvoidPartialCPSR]>;
741731
742732 def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
743733 def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
754744 def : ProcNoItin<"cortex-a32", [ARMv8a,
755745 FeatureHWDiv,
756746 FeatureHWDivARM,
757 FeatureT2XtPk,
758747 FeatureCrypto,
759748 FeatureCRC]>;
760749
761750 def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
762751 FeatureHWDiv,
763752 FeatureHWDivARM,
764 FeatureT2XtPk,
765753 FeatureCrypto,
766754 FeatureCRC]>;
767755
768756 def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
769757 FeatureHWDiv,
770758 FeatureHWDivARM,
771 FeatureT2XtPk,
772759 FeatureCrypto,
773760 FeatureCRC]>;
774761
775762 def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
776763 FeatureHWDiv,
777764 FeatureHWDivARM,
778 FeatureT2XtPk,
779765 FeatureCrypto,
780766 FeatureCRC]>;
781767
782768 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
783769 FeatureHWDiv,
784770 FeatureHWDivARM,
785 FeatureT2XtPk,
786771 FeatureCrypto,
787772 FeatureCRC]>;
788773
789774 def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
790775 FeatureHWDiv,
791776 FeatureHWDivARM,
792 FeatureT2XtPk,
793777 FeatureCrypto,
794778 FeatureCRC]>;
795779
797781 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
798782 FeatureHasRetAddrStack,
799783 FeatureNEONForFP,
800 FeatureT2XtPk,
801784 FeatureVFP4,
802785 FeatureMP,
803786 FeatureHWDiv,
811794 def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
812795 FeatureHWDiv,
813796 FeatureHWDivARM,
814 FeatureT2XtPk,
815797 FeatureCrypto,
816798 FeatureCRC]>;
817799
0 @ RUN: llvm-mc -triple thumbv7 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
1 @ RUN: llvm-mc -triple thumbv8 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
2 @ RUN: llvm-mc -triple thumbv7em %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
3 @ RUN: llvm-mc -triple thumbv6t2 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
4
5 @ RUN: not llvm-mc -triple thumbv6 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
6 @ RUN: not llvm-mc -triple thumbv7m %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
7 @ RUN: not llvm-mc -triple thumbv8m.main %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
8 @ RUN: not llvm-mc -triple thumbv8m.base %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
9
10 @ Instruction is "v6T2, v7" in ARMARM-AR, "v7em" in ARMARM-M. So it's
11 @ valid on everything v6t2 upwards, except v7m. Also apparently not on
12 @ v8m (going by present behaviour).
13 pkhbt r1, r2, r3, lsl #24
14
15 @ CHECK-VALID: pkhbt r1, r2, r3, lsl #24 @ encoding: [0xc2,0xea,0x03,0x61]
16 @ CHECK-INVALID: error: