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Convert more NEON tests to use FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83497 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
6 changed file(s) with 118 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmax\\.s8} %t | count 2
2 ; RUN: grep {vmax\\.s16} %t | count 2
3 ; RUN: grep {vmax\\.s32} %t | count 2
4 ; RUN: grep {vmax\\.u8} %t | count 2
5 ; RUN: grep {vmax\\.u16} %t | count 2
6 ; RUN: grep {vmax\\.u32} %t | count 2
7 ; RUN: grep {vmax\\.f32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
81
92 define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vmaxs8:
4 ;CHECK: vmax.s8
105 %tmp1 = load <8 x i8>* %A
116 %tmp2 = load <8 x i8>* %B
127 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
149 }
1510
1611 define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vmaxs16:
13 ;CHECK: vmax.s16
1714 %tmp1 = load <4 x i16>* %A
1815 %tmp2 = load <4 x i16>* %B
1916 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2118 }
2219
2320 define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vmaxs32:
22 ;CHECK: vmax.s32
2423 %tmp1 = load <2 x i32>* %A
2524 %tmp2 = load <2 x i32>* %B
2625 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2827 }
2928
3029 define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
30 ;CHECK: vmaxu8:
31 ;CHECK: vmax.u8
3132 %tmp1 = load <8 x i8>* %A
3233 %tmp2 = load <8 x i8>* %B
3334 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
3536 }
3637
3738 define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
39 ;CHECK: vmaxu16:
40 ;CHECK: vmax.u16
3841 %tmp1 = load <4 x i16>* %A
3942 %tmp2 = load <4 x i16>* %B
4043 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
4245 }
4346
4447 define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
48 ;CHECK: vmaxu32:
49 ;CHECK: vmax.u32
4550 %tmp1 = load <2 x i32>* %A
4651 %tmp2 = load <2 x i32>* %B
4752 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
4954 }
5055
5156 define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
57 ;CHECK: vmaxf32:
58 ;CHECK: vmax.f32
5259 %tmp1 = load <2 x float>* %A
5360 %tmp2 = load <2 x float>* %B
5461 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
5663 }
5764
5865 define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
66 ;CHECK: vmaxQs8:
67 ;CHECK: vmax.s8
5968 %tmp1 = load <16 x i8>* %A
6069 %tmp2 = load <16 x i8>* %B
6170 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
6372 }
6473
6574 define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
75 ;CHECK: vmaxQs16:
76 ;CHECK: vmax.s16
6677 %tmp1 = load <8 x i16>* %A
6778 %tmp2 = load <8 x i16>* %B
6879 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
7081 }
7182
7283 define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
84 ;CHECK: vmaxQs32:
85 ;CHECK: vmax.s32
7386 %tmp1 = load <4 x i32>* %A
7487 %tmp2 = load <4 x i32>* %B
7588 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
7790 }
7891
7992 define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
93 ;CHECK: vmaxQu8:
94 ;CHECK: vmax.u8
8095 %tmp1 = load <16 x i8>* %A
8196 %tmp2 = load <16 x i8>* %B
8297 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
8499 }
85100
86101 define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
102 ;CHECK: vmaxQu16:
103 ;CHECK: vmax.u16
87104 %tmp1 = load <8 x i16>* %A
88105 %tmp2 = load <8 x i16>* %B
89106 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
91108 }
92109
93110 define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
111 ;CHECK: vmaxQu32:
112 ;CHECK: vmax.u32
94113 %tmp1 = load <4 x i32>* %A
95114 %tmp2 = load <4 x i32>* %B
96115 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
98117 }
99118
100119 define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
120 ;CHECK: vmaxQf32:
121 ;CHECK: vmax.f32
101122 %tmp1 = load <4 x float>* %A
102123 %tmp2 = load <4 x float>* %B
103124 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmin\\.s8} %t | count 2
2 ; RUN: grep {vmin\\.s16} %t | count 2
3 ; RUN: grep {vmin\\.s32} %t | count 2
4 ; RUN: grep {vmin\\.u8} %t | count 2
5 ; RUN: grep {vmin\\.u16} %t | count 2
6 ; RUN: grep {vmin\\.u32} %t | count 2
7 ; RUN: grep {vmin\\.f32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
81
92 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
3 ;CHECK: vmins8:
4 ;CHECK: vmin.s8
105 %tmp1 = load <8 x i8>* %A
116 %tmp2 = load <8 x i8>* %B
127 %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
149 }
1510
1611 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
12 ;CHECK: vmins16:
13 ;CHECK: vmin.s16
1714 %tmp1 = load <4 x i16>* %A
1815 %tmp2 = load <4 x i16>* %B
1916 %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
2118 }
2219
2320 define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
21 ;CHECK: vmins32:
22 ;CHECK: vmin.s32
2423 %tmp1 = load <2 x i32>* %A
2524 %tmp2 = load <2 x i32>* %B
2625 %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
2827 }
2928
3029 define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
30 ;CHECK: vminu8:
31 ;CHECK: vmin.u8
3132 %tmp1 = load <8 x i8>* %A
3233 %tmp2 = load <8 x i8>* %B
3334 %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
3536 }
3637
3738 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
39 ;CHECK: vminu16:
40 ;CHECK: vmin.u16
3841 %tmp1 = load <4 x i16>* %A
3942 %tmp2 = load <4 x i16>* %B
4043 %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
4245 }
4346
4447 define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
48 ;CHECK: vminu32:
49 ;CHECK: vmin.u32
4550 %tmp1 = load <2 x i32>* %A
4651 %tmp2 = load <2 x i32>* %B
4752 %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
4954 }
5055
5156 define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
57 ;CHECK: vminf32:
58 ;CHECK: vmin.f32
5259 %tmp1 = load <2 x float>* %A
5360 %tmp2 = load <2 x float>* %B
5461 %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
5663 }
5764
5865 define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
66 ;CHECK: vminQs8:
67 ;CHECK: vmin.s8
5968 %tmp1 = load <16 x i8>* %A
6069 %tmp2 = load <16 x i8>* %B
6170 %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
6372 }
6473
6574 define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
75 ;CHECK: vminQs16:
76 ;CHECK: vmin.s16
6677 %tmp1 = load <8 x i16>* %A
6778 %tmp2 = load <8 x i16>* %B
6879 %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
7081 }
7182
7283 define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
84 ;CHECK: vminQs32:
85 ;CHECK: vmin.s32
7386 %tmp1 = load <4 x i32>* %A
7487 %tmp2 = load <4 x i32>* %B
7588 %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
7790 }
7891
7992 define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
93 ;CHECK: vminQu8:
94 ;CHECK: vmin.u8
8095 %tmp1 = load <16 x i8>* %A
8196 %tmp2 = load <16 x i8>* %B
8297 %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
8499 }
85100
86101 define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
102 ;CHECK: vminQu16:
103 ;CHECK: vmin.u16
87104 %tmp1 = load <8 x i16>* %A
88105 %tmp2 = load <8 x i16>* %B
89106 %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
91108 }
92109
93110 define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
111 ;CHECK: vminQu32:
112 ;CHECK: vmin.u32
94113 %tmp1 = load <4 x i32>* %A
95114 %tmp2 = load <4 x i32>* %B
96115 %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
98117 }
99118
100119 define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
120 ;CHECK: vminQf32:
121 ;CHECK: vmin.f32
101122 %tmp1 = load <4 x float>* %A
102123 %tmp2 = load <4 x float>* %B
103124 %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmla\\.i8} %t | count 2
2 ; RUN: grep {vmla\\.i16} %t | count 2
3 ; RUN: grep {vmla\\.i32} %t | count 2
4 ; RUN: grep {vmla\\.f32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
51
62 define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
3 ;CHECK: vmlai8:
4 ;CHECK: vmla.i8
75 %tmp1 = load <8 x i8>* %A
86 %tmp2 = load <8 x i8>* %B
97 %tmp3 = load <8 x i8>* %C
1311 }
1412
1513 define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
14 ;CHECK: vmlai16:
15 ;CHECK: vmla.i16
1616 %tmp1 = load <4 x i16>* %A
1717 %tmp2 = load <4 x i16>* %B
1818 %tmp3 = load <4 x i16>* %C
2222 }
2323
2424 define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
25 ;CHECK: vmlai32:
26 ;CHECK: vmla.i32
2527 %tmp1 = load <2 x i32>* %A
2628 %tmp2 = load <2 x i32>* %B
2729 %tmp3 = load <2 x i32>* %C
3133 }
3234
3335 define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
36 ;CHECK: vmlaf32:
37 ;CHECK: vmla.f32
3438 %tmp1 = load <2 x float>* %A
3539 %tmp2 = load <2 x float>* %B
3640 %tmp3 = load <2 x float>* %C
4044 }
4145
4246 define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
47 ;CHECK: vmlaQi8:
48 ;CHECK: vmla.i8
4349 %tmp1 = load <16 x i8>* %A
4450 %tmp2 = load <16 x i8>* %B
4551 %tmp3 = load <16 x i8>* %C
4955 }
5056
5157 define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
58 ;CHECK: vmlaQi16:
59 ;CHECK: vmla.i16
5260 %tmp1 = load <8 x i16>* %A
5361 %tmp2 = load <8 x i16>* %B
5462 %tmp3 = load <8 x i16>* %C
5866 }
5967
6068 define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
69 ;CHECK: vmlaQi32:
70 ;CHECK: vmla.i32
6171 %tmp1 = load <4 x i32>* %A
6272 %tmp2 = load <4 x i32>* %B
6373 %tmp3 = load <4 x i32>* %C
6777 }
6878
6979 define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
80 ;CHECK: vmlaQf32:
81 ;CHECK: vmla.f32
7082 %tmp1 = load <4 x float>* %A
7183 %tmp2 = load <4 x float>* %B
7284 %tmp3 = load <4 x float>* %C
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmlal\\.s8} %t | count 1
2 ; RUN: grep {vmlal\\.s16} %t | count 1
3 ; RUN: grep {vmlal\\.s32} %t | count 1
4 ; RUN: grep {vmlal\\.u8} %t | count 1
5 ; RUN: grep {vmlal\\.u16} %t | count 1
6 ; RUN: grep {vmlal\\.u32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
71
82 define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
3 ;CHECK: vmlals8:
4 ;CHECK: vmlal.s8
95 %tmp1 = load <8 x i16>* %A
106 %tmp2 = load <8 x i8>* %B
117 %tmp3 = load <8 x i8>* %C
1410 }
1511
1612 define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
13 ;CHECK: vmlals16:
14 ;CHECK: vmlal.s16
1715 %tmp1 = load <4 x i32>* %A
1816 %tmp2 = load <4 x i16>* %B
1917 %tmp3 = load <4 x i16>* %C
2220 }
2321
2422 define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
23 ;CHECK: vmlals32:
24 ;CHECK: vmlal.s32
2525 %tmp1 = load <2 x i64>* %A
2626 %tmp2 = load <2 x i32>* %B
2727 %tmp3 = load <2 x i32>* %C
3030 }
3131
3232 define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
33 ;CHECK: vmlalu8:
34 ;CHECK: vmlal.u8
3335 %tmp1 = load <8 x i16>* %A
3436 %tmp2 = load <8 x i8>* %B
3537 %tmp3 = load <8 x i8>* %C
3840 }
3941
4042 define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
43 ;CHECK: vmlalu16:
44 ;CHECK: vmlal.u16
4145 %tmp1 = load <4 x i32>* %A
4246 %tmp2 = load <4 x i16>* %B
4347 %tmp3 = load <4 x i16>* %C
4650 }
4751
4852 define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
53 ;CHECK: vmlalu32:
54 ;CHECK: vmlal.u32
4955 %tmp1 = load <2 x i64>* %A
5056 %tmp2 = load <2 x i32>* %B
5157 %tmp3 = load <2 x i32>* %C
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmls\\.i8} %t | count 2
2 ; RUN: grep {vmls\\.i16} %t | count 2
3 ; RUN: grep {vmls\\.i32} %t | count 2
4 ; RUN: grep {vmls\\.f32} %t | count 2
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
51
62 define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
3 ;CHECK: vmlsi8:
4 ;CHECK: vmls.i8
75 %tmp1 = load <8 x i8>* %A
86 %tmp2 = load <8 x i8>* %B
97 %tmp3 = load <8 x i8>* %C
1311 }
1412
1513 define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
14 ;CHECK: vmlsi16:
15 ;CHECK: vmls.i16
1616 %tmp1 = load <4 x i16>* %A
1717 %tmp2 = load <4 x i16>* %B
1818 %tmp3 = load <4 x i16>* %C
2222 }
2323
2424 define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
25 ;CHECK: vmlsi32:
26 ;CHECK: vmls.i32
2527 %tmp1 = load <2 x i32>* %A
2628 %tmp2 = load <2 x i32>* %B
2729 %tmp3 = load <2 x i32>* %C
3133 }
3234
3335 define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
36 ;CHECK: vmlsf32:
37 ;CHECK: vmls.f32
3438 %tmp1 = load <2 x float>* %A
3539 %tmp2 = load <2 x float>* %B
3640 %tmp3 = load <2 x float>* %C
4044 }
4145
4246 define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
47 ;CHECK: vmlsQi8:
48 ;CHECK: vmls.i8
4349 %tmp1 = load <16 x i8>* %A
4450 %tmp2 = load <16 x i8>* %B
4551 %tmp3 = load <16 x i8>* %C
4955 }
5056
5157 define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
58 ;CHECK: vmlsQi16:
59 ;CHECK: vmls.i16
5260 %tmp1 = load <8 x i16>* %A
5361 %tmp2 = load <8 x i16>* %B
5462 %tmp3 = load <8 x i16>* %C
5866 }
5967
6068 define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
69 ;CHECK: vmlsQi32:
70 ;CHECK: vmls.i32
6171 %tmp1 = load <4 x i32>* %A
6272 %tmp2 = load <4 x i32>* %B
6373 %tmp3 = load <4 x i32>* %C
6777 }
6878
6979 define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
80 ;CHECK: vmlsQf32:
81 ;CHECK: vmls.f32
7082 %tmp1 = load <4 x float>* %A
7183 %tmp2 = load <4 x float>* %B
7284 %tmp3 = load <4 x float>* %C
None ; RUN: llc < %s -march=arm -mattr=+neon > %t
1 ; RUN: grep {vmlsl\\.s8} %t | count 1
2 ; RUN: grep {vmlsl\\.s16} %t | count 1
3 ; RUN: grep {vmlsl\\.s32} %t | count 1
4 ; RUN: grep {vmlsl\\.u8} %t | count 1
5 ; RUN: grep {vmlsl\\.u16} %t | count 1
6 ; RUN: grep {vmlsl\\.u32} %t | count 1
0 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
71
82 define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
3 ;CHECK: vmlsls8:
4 ;CHECK: vmlsl.s8
95 %tmp1 = load <8 x i16>* %A
106 %tmp2 = load <8 x i8>* %B
117 %tmp3 = load <8 x i8>* %C
1410 }
1511
1612 define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
13 ;CHECK: vmlsls16:
14 ;CHECK: vmlsl.s16
1715 %tmp1 = load <4 x i32>* %A
1816 %tmp2 = load <4 x i16>* %B
1917 %tmp3 = load <4 x i16>* %C
2220 }
2321
2422 define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
23 ;CHECK: vmlsls32:
24 ;CHECK: vmlsl.s32
2525 %tmp1 = load <2 x i64>* %A
2626 %tmp2 = load <2 x i32>* %B
2727 %tmp3 = load <2 x i32>* %C
3030 }
3131
3232 define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
33 ;CHECK: vmlslu8:
34 ;CHECK: vmlsl.u8
3335 %tmp1 = load <8 x i16>* %A
3436 %tmp2 = load <8 x i8>* %B
3537 %tmp3 = load <8 x i8>* %C
3840 }
3941
4042 define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
43 ;CHECK: vmlslu16:
44 ;CHECK: vmlsl.u16
4145 %tmp1 = load <4 x i32>* %A
4246 %tmp2 = load <4 x i16>* %B
4347 %tmp3 = load <4 x i16>* %C
4650 }
4751
4852 define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
53 ;CHECK: vmlslu32:
54 ;CHECK: vmlsl.u32
4955 %tmp1 = load <2 x i64>* %A
5056 %tmp2 = load <2 x i32>* %B
5157 %tmp3 = load <2 x i32>* %C